201002610 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種微結構製造方法，特別是指一種全 新的可整合半導體製程之微結構製造方法，其能有效避免 微結構及金屬不當侵蝕破壞。 【先前技術】 按，現今半導體微機電系統包含各種不同的半導體微 型結構，例如：不可動的探針、流道、孔穴結構，或是一 些可動的彈簀、連桿、齒輪（剛體運動或是撓性形變）等結 構。 將上述不同的結構和相關的半導體電路相互整合，即 可構成各種不同的半導體應用；藉由製造方法提昇微機械 結構各種不同的功能，是未來半導體微機電系統的關鍵指 標，也是未來進一步研究晶片時的嚴峻挑戰；若能研發改 進習知的技術，未來的發展性實無法預估。 目前製作微機電感測器及致動器系統皆需要在矽基 層上製作出懸浮式結構；前述製程必須採用了先進的半導 體技術，例如：濕银刻、乾触刻和犧牲層（sacrificial layer)去除等微機電專用作業。 濕钱刻是一種快速有效钱刻，而且不致餘刻其它材料 5 201002610 的『触刻劑』（etchant)，因此，通常濕餘刻對不同材料 會具有相當高的『選擇性』（selectivity)。然而，除了 結晶方向可能影響蝕刻速率外，由於化學反應並不會舞特 定方向有任何的偏好，因此濕蝕刻本質上乃是一種『等向 性蝕刻』（isotropic etching)。等向性蝕刻意味著，濕 餘刻不但會在縱向進行㈣，而且也會有橫向的餘刻效 果也、向钱亥J ^ ‘致所謂『側钱』（⑽d奸⑽）的現象發生； 相反的，在乾姓刻（電漿餘刻）中，電漿是-種部分解 離的氣體，乾飯刻f V5 J取大優點即是『非等向性蝕刻』 (anisotropie etching)。然而，乾㈣的選擇性卻比濕 仙來得低（因為乾_的钕刻機制基本上是-種物理交、 互作用，因此離子的措敏 童牮不但可以移除被蝕刻的薄膜，也 同時會移除遮罩）。 習用係於一碎基居 ^ ^表面形成至少一内具微機電結 構的絕緣層，该微機電 電路，前述習用結齡—t 少-微結構與數個金屬 門題· v分析，仍存在下列問題： 問碭習用絕緣層上 金屬連接層，該金屬連接 層”至屬电路電性連結， 護的金屬連接層將因一緣3進行蝕刻時，不受保 效保護該金屬連接層避H使結構遭受破壞，故如何有 不當侵蝕係為目前極欲解 6 201002610 決之重點所在。 問題二：習用微結構進行蝕刻時，蝕刻液將直接侵蝕 不受保護的微結構而使結構遭受破壞，故如何有效保護該 微結構避免遭受不當侵蝕係為目前極欲解決之重點所在。 問題三：習用微機電結構必須採用光罩（mask)，方能 進行精密钱刻技術，但隨著微機電技術的設計愈來愈精 細，造成光罩之製造愈來愈不容易，如此不但增加生產成 本，故如何採用替代性光罩即可進行精密蝕刻係為目前極 欲解決之重點所在。 而為了能夠有效解決前述相關議題，本發明創作人基 於過去在微機電（Microelectric Machanic System, MEMS) 領域所累積的研發技術與經驗，於數次試驗及多方嘗試 後，終於發展出一種可整合半導體製程之微結構製造方 法。 【發明内容】 本發明可整合半導體製程之微結構製造方法，其目的 之一在於有效避免與外部連接的金屬連接層遭受不當蝕 刻。 為達成上述目的，本發明可整合半導體製程之微結構 製造方法係於一矽基層上表面形成絕緣層，該絕緣層包含 7 201002610 至少一微結構與數個金屬電路，該絕緣層成型一與金屬電 路及外部導體電性連結的金屬連接層，該金屬連接層係外 露於該絕緣層表面上受一保護層覆蓋進行蝕刻。 藉由前述進一步分析將可獲得下述功效：該金屬連接 層受該保護層保護進行钱刻，讓钱刻液無法直接侵钱該金 屬連接層，避免該金屬連接層遭受破壞，最後再藉由敍刻 保護層使外部導體透過與該金屬連接層電性連結後，令該 金屬電路透過打線與外部接合進行訊號傳輸。 本發明可整合半導體製程之微結構製造方法，其目的 之二在於有效避免微結構暴露遭受不當侵蝕。 為達成上述目的，本發明可整合半導體製程之微結構 製造方法係於一矽基層上表面形成絕緣層，該絕緣層包含 至少一微結構與數個金屬電路，該微結構與該金屬電路受 該絕緣層包覆進行飯刻。 藉由前述進一步分析將可獲得下述功效：該微結構受 該絕緣層保護進行蝕刻，無論是採用由上而下蝕刻或由下 而上蝕刻，蝕刻液皆無法直接侵蝕該微結構，避免該微結 構之金屬暴露遭受破壞並產生污染機台腔體的金屬顆粒。 本發明可整合半導體製程之微結構製造方法，其目的 8 201002610 之三在於大幅簡化遮蔽所需的精密度需求進而降低整體 成本。 為達成上述目的，本發明可整合半導體製程之微結構 製造方法係於一矽基層上表面形成絕緣層，該絕緣層包含 至少一微結構與數個金屬電路，該絕緣層上成型一保護層 進行絕緣層及矽基層之蝕刻空間成型。 藉由前述進一步分析將可獲得下述功效：該保護層及 保護蓋遮蔽取代精密光罩效果進行蝕刻，使該微結構達到 懸浮，以及金屬連接層上的保護層被移除，進而減輕使用 光罩耗費的成本；且該保護蓋進行切割時，該金屬連接層 將受該保護層保護免於割傷破損，另該保護蓋的設置將對 該矽基層與該絕緣層進行支撐對抗應力，進而避免受力破 碎提昇製程良率。 有關本發明為達成上述目的，所採用之技術、手段及 其他功效，茲列舉實施例並配合圖式詳細說明如後，相信 本發明之目的、特徵及其他優點，當可由之得一深入而具 體之瞭解。 【實施方式】 本發明實施例請參閱第1圖至第13圖所示，本發明可 整合半導體製程之微結構製造方法詳細說明如下： 9 201002610 請參閱第1圖所示’首先於一石夕基層10上表面丨丨成型 一絕緣層20 ’该纟巴緣層20可為一氧化秒，該絕緣層2〇具有 至少一微結構（M1Cr〇StrUCtUre) 21、複數個金屬電路” 及複數個互補式金屬氧化半導體（complementary Metal-Oxide-Semiconductor, CMOS)齋？々既〇0 兔路層23，該微結 構21、該金屬電路22及該互補式金屬氧化半導體電路層23 分別受該絕緣層20包覆； 該微結構21周側設有該金屬堆疊層24，該金屬堆疊層 24係由鋁銅合金、鎢或鈦等金屬交互堆疊而成，該金屬堆 叠層24外露是用來蝕刻所需空間，該金屬堆疊層24採用能 被姓刻液彳s:飯的材質’前述該微結構21受該絕緣層2 〇包覆 下並未與該金屬堆疊層24接觸； 該絕緣層20表面成型一與該金屬電路22電性連結的 金屬連接層30，該金屬連接層30外露係可用來與外部導體 電性連結，讓該金屬電路22與外部導體進行訊號連結； 該絕緣層20在標準半導體製程的最後於表面沉積一 為鈍化材質的第一保護層40，該第一保護層4〇係採用電漿 輔助化學氣相沉積（Plasma-Enhanced CVD，PECVD)、常壓 化學氣相沉積（Atmospheric Pressure CVD, APCVD)或低 壓化學氣相沉積（L〇w-pressure CVD, LPCVD)等技術進行 沉積，該第一保護層40係由一氮化物（nitride)層及一氧 10 201002610 化物（oxide)層所組成，接著利用曝光、顯影及钱刻等技 術使得特定區域外露而不受該第一保護層4 〇覆苗，前述特 定區域包含該金屬堆疊層24表面、該金屬連接層表面及 包覆該微結構21之絕緣層2 0的表面； 請參閱第2圖所示，該絕緣層20於表面沉積—為氧化 材質的第二保護層50’該第二保護層50係採用電裝辅助化 學氣相沉積（Plasma-Enhanced CVD，PECVD)、常壓化風 ^ 相沉積（Atmospheric Pressure CVD，APCVD)或低壓化與 氣相沉積（Low-Pressure CVD，LPCVD)等技術進行沉積， 使外露於該絕緣層20表面的該金屬堆叠層24、該金屬連接 層30及該第一保護層40分別受該第二保護層50覆蓋； 請參閱第3圖所示，對該金屬堆疊層24表面的第二^呆 護層50及包覆該微結構21之絕緣層20表面的第二保護層 50進行钱刻去除； 請參閱第4圖所示，對該金屬堆疊層24蝕刻（係採用濕、 I虫刻或乾|虫刻），去除該金屬堆疊層24進而形成貫通|亥、絕 緣層20的蝕刻空間201，且於蝕刻過程中，仍被該第二保 護層50覆蓋的部份，將受該第二保護層50作為蝕刻光罩保 201002610 護避免遭受侵蝕，以及受該絕緣層20包覆的該微結構21 也將避免遭受侵蝕； 請參閱第5圖所示，利用該絕緣層20對該矽基層10的 高蝕刻選擇比，對相對該絕緣層20之蝕刻空間201的矽基 層10正面進行蝕刻（係採用深活性離子蝕刻Deep Reactive Ion Etching, DR IE)，去除局部石夕基層10，進而 形成尚未貫通該矽基層10的蝕刻空間101，且於蝕刻過程 中，仍被該第二保護層50覆蓋的部份，將受該第二保護層 50作為蝕刻光罩保護避免遭受侵蝕，以及受該絕緣層20 包覆的該微結構21也將避免遭受侵蝕； 請參閱第6圖所示，該第二保護層50上設置一為玻璃 或為矽晶圓的保護蓋60，該保護蓋60與該第二保護層50 之間透過一黏著層70結合，且該保護蓋60與該第二保護層 50彼此相距一特定距離，該保護蓋60於表面設置一層環氧 化物（epoxy)，該保護蓋60透過該環氧化物彈性缓衝封裝 壓力避免損壞，該矽基層10與該絕緣層20受該保護蓋60 支撐下，使該矽基層10與該絕緣層20於運送時將避免受力 破裂碎掉，因製程所需該矽基層10必須磨薄到300um以 下，磨薄將會因應力產生翹曲，如不使用該保護蓋60作為 12 201002610 支撐將容易破裂碎掉，一旦損毀將言夫， 程良率因此降低； 、°製程失敗，造成製 請參閱第7圖所禾，對相對該絕緣爲 的石夕基層10由背面進行㈣（係採用^20之㈣空間201 银刻），纟除局部石夕基層1◦，使該麵刻離子钕刻或屋 層10，讓該矽基層1〇的蝕刻空間1〇1^間101貫通該矽基 空間201相互連貫通，令該微結構21艰々绝緣層20的银刻 該微結構21受該絕緣層20包覆下，除了戍懸浮狀態；前述 刻光罩，更可避免該微結構21内部的金作為深活性離子蝕 濺出污染機台腔體的金屬顆粒； 屬電路22裸露蝕刻 請參閱第8圖所示’切割該保譜 ’使該金屬連接 蔽’該保護蓋60 灵意6〇 層30上的第二保護層50不受該保護蓋如坻 作為蝕刻光罩對特定區域進行蝕刻去除； 請參閱第9圖所示’該保護蓋6〇於切割時，該金屬連 接層30於該第二保護層5〇保護下，將避免該金屬連接層糾 遭受割傷，對該金屬連接層3Q上的第二保護㈣進行餘 刻，讓該金屬連接層30外露於該絕緣層2〇表面，且於蝕刻 過程中，該微結構21受該絕緣層2〇及該保護蓋6〇保護避免 13 201002610 遭受侵蝕，以及該絕緣層20透過表面特定區域的第一保護 層4 0進行蚀刻，利用氧化層與氮化層的钱刻選擇比，讓特 定區域透過該第一保護層40保護避免遭受侵蝕，使外部導 體透過與該金屬連接層3 0電性連結後，令該金屬電路2 2 透過打線與外部接合進行傳輸訊號。 下列第10圖至第13圖係為第6圖至第9圖之另一實施 態樣： 請參閱第10圖所示，採用等向性乾蝕刻或溼蝕刻沿著 該矽基層10晶格面蝕刻分離矽基層10形成蝕刻空間101， 令該微結構21形成懸浮狀態，或是，採用深活性離子蝕刻 不長侧壁保護的參數，對該矽基層10的蝕刻空間101進行 蝕刻分離矽基層10形成蝕刻空間101，令該微結構21形成 懸浮狀態，前述該微結構21受該絕緣層20包覆下，除了作 為蝕刻光罩，更可避免該微結構21内部的金屬電路22裸露 蝕刻濺出污染機台腔體的金屬顆粒； 請參閱第11圖所示，該第二保護層50上設置一為玻璃 或為矽晶圓的保護蓋60，該保護蓋60與該第二保護層50 之間透過一黏著層70結合，且該保護蓋60與該第二保護層 50彼此相距一特定距離，該保護蓋60於表面設置一層環氧 14 201002610 化物（ePQXy)，該保護蓋6G透過該環氧化物彈性緩衝封穿 ㈣避免損壞，_基層1G與該絕緣層2Q受該保護蓋如 支h下t亥石夕基層！ 〇與該絕緣層2 〇於運送時將 破裂碎掉，因劁# & + ^ 、王所舄該矽基層10必須磨薄到300_以 下’磨2將會m應力產生翹曲，如不使贱賴蓋6〇作為 支撐將㈣破裂碎掉，—旦損毁將宣告製程失敗 程良率因此降低； Λ衣 睛J弟12圖所示，切割該保護蓋6〇，使該金屬連接 層30上的第二保護層5G不受該保護蓋_蔽，該保護蓋60 作為㈣衫對料區域進⑽刻去除； 凊麥閱第13圖所示，該保護蓋6〇於切割時，該金屬連 接層30於該第二保護層50保護下，將避免該金屬連接層30 遭文割傷’對該金屬連接層3〇上的第二保護層5〇進行蝕 刻’讓該金屬連接層3〇外露於該絕緣層2〇表面，且於蝕刻 過程中’該微結構21受該絕緣層2〇及該保護蓋60保護避免 遭受侵餘’以及該絕緣層2〇透過表面特定區域的第一保護 層40進行餘刻’利用氧化層與氮化層的蝕刻選擇比，讓特 定區域透過該第一保護層40保護避免遭受侵蝕，使外部導 體透過與該金屬連接層30電性連結後，令該金屬電路22 15 201002610 透過打線與外部接合進行傳輸訊號。 綜上所述，本發明『產業之可利用性』已顯而易見， 且本案實施例所揭露出的特徵技術，並未見於各刊物及傳 媒，亦未曾被公開使用，更具有不可輕忽的附加功效，故 本發明的『购性』以及『辭性』都已符合專利法規， 麦依法提出發明翻H祈請‘I、予審查並早日賜准專 利，實感德便。 16 201002610 【圖式簡單說明】 第1圖至第13圖係本發明之微結構製造方法示意圖。 【主要元件符號說明】 《本發明》 矽基層10 蝕刻空間101 上表面11 絕緣層20 蝕刻空間201 微結構21 金屬電路22 互補式金屬氧化半導體電路層23 金屬堆疊層24 金屬連接層30 第一保護層40 第二保護層50 保護蓋60 黏著層70 17201002610 IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a microstructure, and more particularly to a novel microfabrication manufacturing method capable of integrating semiconductor processes, which can effectively prevent microstructural and metal undue erosion damage . [Prior Art] According to the present, semiconductor MEMS systems include various semiconductor micro-structures, such as non-movable probes, runners, hole structures, or some movable magazines, connecting rods, gears (rigid body motion or Flexible deformation) and other structures. Integrating the above different structures and related semiconductor circuits into each other can constitute various semiconductor applications; improving various functions of micro-mechanical structures by manufacturing methods is a key indicator of future semiconductor MEMS, and is also a further research wafer in the future. The severe challenges of the time; if we can develop and improve the know-how, the future development cannot be predicted. At present, the fabrication of microcomputer inductive detectors and actuator systems requires the fabrication of a floating structure on the base layer of the crucible; the aforementioned processes must employ advanced semiconductor techniques such as wet silver etching, dry etching and sacrificial layers. Remove special operations such as MEMS. Wet money engraving is a fast and effective money engraving, and it does not leave the etchant of other materials. Therefore, the wet residue usually has a relatively high selectivity for different materials. However, in addition to the fact that the direction of crystallization may affect the etch rate, wet etching is essentially an isotropic etching because the chemical reaction does not have any preference for the particular direction of the dance. Isotropic etching means that the wet residue will not only be carried out in the vertical direction (4), but also the lateral residual effect will be caused to the phenomenon of "the side money" ((10) d (10)). In the dry name engraving (plasma remnant), the plasma is a kind of partially dissociated gas, and the dry rice engraving f V5 J takes the advantage of "anisotropie etching". However, the selectivity of dry (four) is lower than that of wet immortal (because the dry etching mechanism is basically a kind of physical interaction and interaction, so the ion-sensitive virginity can not only remove the etched film, but also The mask will be removed). Conventionally, at least one insulating layer having a microelectromechanical structure is formed on a surface of a broken base, and the microelectromechanical circuit has the following conventional age-t-micro-structure and several metal gates and v analysis, and the following still exist Problem: When the metal connection layer on the insulating layer is used, the metal connection layer is electrically connected to the circuit, and the metal connection layer of the protection layer is etched by the edge 3, and the metal connection layer is not protected by the protection. The structure is damaged, so how to have improper erosion is the focus of the current 2010-0610. Problem 2: When the conventional microstructure is etched, the etching solution will directly erode the unprotected microstructure and damage the structure. How to effectively protect the microstructure from undue erosion is the focus of the current solution. Problem 3: The conventional micro-electromechanical structure must use a mask to perform precise etching techniques, but with the micro-electromechanical technology As the design becomes more and more fine, the manufacture of the mask is becoming more and more difficult, which not only increases the production cost, but how to use the alternative mask to perform the precision etching system. At present, the focus of the solution is to be solved. In order to effectively solve the aforementioned related issues, the creators of the present invention based on the research and development technology and experience accumulated in the field of Microelectric Machanic System (MEMS) in the past, after several trials and multiple attempts Finally, a microfabrication manufacturing method capable of integrating semiconductor processes has been developed. SUMMARY OF THE INVENTION The present invention can integrate a semiconductor fabrication method for microstructure fabrication, one of the purposes of which is to effectively avoid improper etching of a metal connection layer connected to the outside. To achieve the above object, the microstructure manufacturing method of the integrated semiconductor process of the present invention is to form an insulating layer on the upper surface of a base layer, the insulating layer comprising 7 201002610 at least one microstructure and a plurality of metal circuits, the insulating layer forming a metal circuit And a metal connecting layer electrically connected to the outer conductor, the metal connecting layer is exposed on the surface of the insulating layer and covered by a protective layer for etching. By the foregoing further analysis, the following effects can be obtained: the metal connecting layer is protected by the protection Layer protection for money engraving, so that money can not be directly The metal connection layer is prevented from being damaged by the metal connection layer. Finally, the external conductor is electrically connected to the metal connection layer by the engraving protection layer, and then the metal circuit is transmitted through the wire bonding and the external connection for signal transmission. The invention can integrate the microstructure manufacturing method of the semiconductor process, and the second purpose thereof is to effectively avoid the improper exposure of the microstructure exposure. To achieve the above object, the micro-structure manufacturing method of the integrated semiconductor process of the invention can form an insulation on the upper surface of a substrate. a layer, the insulating layer comprising at least one microstructure and a plurality of metal circuits, the microstructure and the metal circuit being covered by the insulating layer for cooking. The foregoing further analysis can obtain the following effects: the microstructure is affected by the The insulating layer protects the etching. Whether it is etched from top to bottom or from bottom to top, the etchant cannot directly erode the microstructure, avoiding metal damage of the microstructure and causing damage to the metal particles of the chamber cavity. . The present invention can integrate a microstructure manufacturing method for a semiconductor process, and its purpose 8 201002610 iii is to greatly simplify the precision requirements required for shielding and thereby reduce the overall cost. In order to achieve the above object, the microstructure manufacturing method of the integrated semiconductor process of the present invention is to form an insulating layer on an upper surface of a base layer, the insulating layer comprising at least one microstructure and a plurality of metal circuits, and a protective layer is formed on the insulating layer. The etching space of the insulating layer and the ruthenium base layer is formed. By the foregoing further analysis, the following effects can be obtained: the protective layer and the protective cover shield are etched instead of the precision reticle effect, the microstructure is suspended, and the protective layer on the metal connecting layer is removed, thereby reducing the use of light. The cost of the cover; and when the protective cover is cut, the metal connecting layer is protected from the damage by the protective layer, and the protective cover is disposed to support the base layer and the insulating layer against stress, thereby Avoid stress and improve process yield. The present invention has been described with reference to the embodiments and the detailed description of the present invention. The objects, features and other advantages of the present invention are believed to be Understand. [Embodiment] Please refer to FIG. 1 to FIG. 13 for the embodiment of the present invention. The microstructure manufacturing method for integrating semiconductor process according to the present invention is described in detail as follows: 9 201002610 Please refer to FIG. 1 first in the first stone layer. 10, the upper surface is formed by an insulating layer 20', the barrier layer 20 may be an oxidation second, the insulating layer 2 has at least one microstructure (M1Cr〇StrUCtUre) 21, a plurality of metal circuits" and a plurality of complementary A metal oxide semiconductor (compoundary metal-Oxide-Semiconductor, CMOS) 々 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔 兔The metal structure layer 24 is provided on the circumferential side of the microstructure 21, and the metal stack layer 24 is formed by alternately stacking metals such as aluminum-copper alloy, tungsten or titanium, and the metal stack layer 24 is exposed for etching. The metal stack layer 24 is made of a material that can be engraved by the surname: s: the microstructure 21 is covered by the insulating layer 2 and is not in contact with the metal stack layer 24; the surface of the insulating layer 20 is formed. With the gold The metal connection layer 30 is electrically connected to the circuit 22, and the exposed portion of the metal connection layer 30 can be electrically connected to the external conductor, and the metal circuit 22 is signal-coupled to the external conductor; the insulating layer 20 is at the end of the standard semiconductor process. Depositing a first passivation layer 40 on the surface, the first protective layer 4 is plasma-assisted chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (Atmospheric Pressure CVD). Deposited by techniques such as APCVD) or low pressure chemical vapor deposition (LPCVD), the first protective layer 40 is composed of a nitride layer and an oxygen 10 201002610 oxide layer. Then, using a technique such as exposure, development, and engraving, the specific region is exposed without being covered by the first protective layer 4, and the specific region includes the surface of the metal stack layer 24, the surface of the metal connection layer, and the microstructure. The surface of the insulating layer 20 of 21; as shown in Fig. 2, the insulating layer 20 is deposited on the surface - a second protective layer 50' of an oxidized material. The second protective layer 50 is electrically assisted. Deposited by techniques such as Plasma-Enhanced CVD (PECVD), Atmospheric Pressure CVD (APCVD) or Low-Pressure CVD (LPCVD) to expose The metal stacked layer 24, the metal connecting layer 30 and the first protective layer 40 on the surface of the insulating layer 20 are respectively covered by the second protective layer 50; as shown in FIG. 3, the surface of the metal stacked layer 24 is The second protective layer 50 and the second protective layer 50 covering the surface of the insulating layer 20 of the microstructure 21 are removed by etching; as shown in FIG. 4, the metal stacked layer 24 is etched (wet, I insert or dry|insect), remove the metal stacked layer 24 to form an etched space 201 of the through-hole, insulating layer 20, and the portion still covered by the second protective layer 50 during the etching process, The second protective layer 50 is used as an etch mask to protect against corrosion, and the microstructure 21 covered by the insulating layer 20 will also be protected from erosion; please refer to FIG. 5 to utilize the insulating layer 20 High etching selectivity ratio to the germanium base layer 10, relative to The front surface of the ruthenium layer 10 of the etched space 201 of the insulating layer 20 is etched (using Deep Reactive Ion Etching, DR IE) to remove the local slab layer 10, thereby forming an etched space 101 that has not penetrated the ruthenium base layer 10. And the portion still covered by the second protective layer 50 during the etching process is protected by the second protective layer 50 as an etch mask to avoid erosion, and the microstructure 21 covered by the insulating layer 20 The protection cover 60 of the glass or the silicon wafer is disposed on the second protective layer 50. The protective cover 60 and the second protective layer 50 pass through a protective cover 60. The adhesive layer 70 is bonded, and the protective cover 60 and the second protective layer 50 are separated from each other by a specific distance. The protective cover 60 is provided with an epoxy layer on the surface, and the protective cover 60 is elastically buffered through the epoxy. The encapsulation pressure is prevented from being damaged, and the crucible base layer 10 and the insulating layer 20 are supported by the protective cover 60, so that the crucible base layer 10 and the insulating layer 20 are prevented from being broken by force during transportation, and the crucible base layer is required for the process. 10 must be thinned to 3 Below 00um, the thinness will be warped due to stress. If the protective cover 60 is not used as the 12 201002610, the support will be easily broken and broken. Once the damage is lost, the process yield will be reduced. Referring to Figure 7, the base layer 10 opposite to the insulation is made from the back side (4) (using the (20) space 201 silver engraving of ^20), and the local stone base layer 1纟 is removed, so that the surface engraving is performed. Or the roof layer 10, the etching space 1〇1^101 of the 矽 base layer 1 贯通 is penetrated through the 矽-based space 201, and the microstructure 21 is hardened by the silver inscription of the insulating layer 20 The insulating layer 20 is covered, except for the suspended state of the crucible; the foregoing engraved mask can prevent the gold inside the microstructure 21 from being splashed as a deep active ion to contaminate the metal particles of the chamber cavity; The 'cutting the spectrum' shown in Fig. 8 causes the metal to be attached to the protective cover 60. The second protective layer 50 on the layer 6 is not etched by the protective cover such as enamel as an etch mask to etch a specific region. Remove; please refer to Figure 9 'The protective cover 6 is cut When cutting, the metal connecting layer 30 is protected by the second protective layer 5〇, and the metal connecting layer is prevented from being cut and cut, and the second protection (4) on the metal connecting layer 3Q is left for the metal connection. The layer 30 is exposed on the surface of the insulating layer 2, and during the etching process, the microstructure 21 is protected by the insulating layer 2 and the protective cover 6 13 13026026, and the insulating layer 20 is transmitted through a specific area of the surface. The first protective layer 40 is etched, and the specific region is shielded from the first protective layer 40 to avoid erosion by the etching ratio of the oxide layer and the nitride layer, so that the external conductor is transmitted through the metal connection layer. After the connection, the metal circuit 2 2 is connected to the external line for transmission of signals. The following 10th to 13th drawings are another embodiment of FIGS. 6 to 9: Referring to FIG. 10, an isotropic dry etching or wet etching is performed along the 矽 base layer 10 lattice plane. The etch-off ruthenium base layer 10 forms an etched space 101, so that the microstructure 21 is in a suspended state, or the etched space 101 of the ruthenium base layer 10 is etched and separated by a deep active ion etch without a side wall protection parameter. The etched space 101 is formed to form the suspended structure 21, and the microstructure 21 is covered by the insulating layer 20. In addition to being used as an etch mask, the metal circuit 22 inside the microstructure 21 can be prevented from being exposed and etched. The metal particles of the chamber cavity are contaminated; as shown in FIG. 11 , the second protective layer 50 is provided with a protective cover 60 of glass or silicon wafer, and the protective cover 60 and the second protective layer 50 The protective cover 60 is disposed on the surface with a layer of epoxy 14 201002610 (ePQXy) through which the protective cover 6G is bonded through an adhesive layer 70 and the protective cover 60 and the second protective layer 50 are separated from each other by a certain distance. Oxide elastic buffer sealing (4) to avoid damage, _ the base layer 1G and the insulation layer 2Q are subject to the protective cover such as the support h under the t-light stone base layer! 〇 and the insulating layer 2 will be broken when transported, because 劁# & + ^, Wang's 矽 base layer 10 must be thinned to 300_ below 'grinding 2' will cause stress to warp, if not If the 贱 盖 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 — — — — — — — — — — — — — — The upper second protective layer 5G is not covered by the protective cover, and the protective cover 60 is removed as a (four) shirt facing area; as shown in FIG. 13 of the buckwheat, the protective cover 6 is cut when the metal is cut. The connection layer 30 is protected by the second protective layer 50, and the metal connection layer 30 is prevented from being cut by the 'etching of the second protective layer 5' on the metal connection layer 3'. Exposed to the surface of the insulating layer 2, and during the etching process, the microstructure 21 is protected by the insulating layer 2 and the protective cover 60 to avoid being invaded, and the first layer of the insulating layer 2 is transmitted through a specific area of the surface. Layer 40 performs the remainder 'using the etching selectivity ratio of the oxide layer and the nitride layer to allow a specific region to pass through the first A protective layer 40 protects against erosion, and the external conductor is electrically connected to the metal connecting layer 30, so that the metal circuit 22 15 201002610 transmits signals by wire bonding and external bonding. In summary, the "industry availability" of the present invention has been apparent, and the feature technology disclosed in the embodiments of the present invention has not been seen in various publications and media, and has not been publicly used, and has an additional effect that cannot be neglected. Therefore, the "purchase" and "resignation" of the present invention have been in compliance with the patent regulations, and Mai has proposed to invent the invention and ask for 'I, review and grant the patent as soon as possible. 16 201002610 [Simple description of the drawings] Figs. 1 to 13 are schematic views showing the manufacturing method of the microstructure of the present invention. [Main component symbol description] "The present invention" 矽 base layer 10 etching space 101 upper surface 11 insulating layer 20 etching space 201 microstructure 21 metal circuit 22 complementary metal oxide semiconductor circuit layer 23 metal stack layer 24 metal connection layer 30 first protection Layer 40 second protective layer 50 protective cover 60 adhesive layer 70 17