TWI483892B - Micro-electromechanical device and method for manufacturing micro-electromechanical device - Google Patents

Micro-electromechanical device and method for manufacturing micro-electromechanical device Download PDF

Info

Publication number
TWI483892B
TWI483892B TW100115989A TW100115989A TWI483892B TW I483892 B TWI483892 B TW I483892B TW 100115989 A TW100115989 A TW 100115989A TW 100115989 A TW100115989 A TW 100115989A TW I483892 B TWI483892 B TW I483892B
Authority
TW
Taiwan
Prior art keywords
layer
substrate
microstructure
conductive layer
electrode
Prior art date
Application number
TW100115989A
Other languages
Chinese (zh)
Other versions
TW201245030A (en
Inventor
Siewseong Tan
Original Assignee
Memsor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memsor Corp filed Critical Memsor Corp
Priority to TW100115989A priority Critical patent/TWI483892B/en
Publication of TW201245030A publication Critical patent/TW201245030A/en
Application granted granted Critical
Publication of TWI483892B publication Critical patent/TWI483892B/en

Links

Landscapes

  • Micromachines (AREA)
  • Pressure Sensors (AREA)

Description

微機電裝置以及製造微機電裝置之方法Microelectromechanical device and method of manufacturing microelectromechanical device

本發明是有關於一種微機電裝置及其製造方法。The present invention relates to a microelectromechanical device and a method of fabricating the same.

隨著半導體製程技術的進步,已推動微機電系統(MEMS)的蓬勃發展。在傳統微機械系統的製造方法中,主動元件製程與微機電製程是分開進行,在分別完成主動元件電路與微機電裝置後,再將兩者整合在同一基材上而完成微機電系統。上述的製造方法又稱為「System In Package」(SIP)。With the advancement of semiconductor process technology, the development of microelectromechanical systems (MEMS) has been promoted. In the manufacturing method of the conventional micromechanical system, the active component process and the microelectromechanical process are performed separately, and after the active component circuit and the microelectromechanical device are respectively completed, the two are integrated on the same substrate to complete the MEMS system. The above manufacturing method is also called "System In Package" (SIP).

另一種習知的製造方式是在形成主動元件電路中諸如金屬氧化物半導體元件(MOS)及雙載子接面電晶體(BJT)等半導體元件後,再進行形成微機電結構的製程,然後再進行主動元件電路的金屬化製程而完成晶圓層級(wafer level)的微機電系統。隨後將晶圓切割成晶片(Die),最後再進行晶片的封裝。Another conventional manufacturing method is to form a microelectromechanical structure after forming semiconductor elements such as a metal oxide semiconductor device (MOS) and a bipolar junction transistor (BJT) in an active device circuit, and then A wafer level MEMS is completed by performing a metallization process of the active device circuit. The wafer is then diced into wafers (Die) and finally wafer packaged.

無論是上述何種製造方式,在微機電裝置的製造過程中,在形成微機電裝置的可移動的構件時,通常必須藉由一研磨步驟才能完成。但是,研磨步驟常伴隨震動發生,而導致微機電裝置中的某些細微結構受損。再者,在某些微機電裝置中,因微機電裝置整體構造之配置關係,其中某些電容結構中的電極之間的間距過大,而造成電容值下降,導致產品性能不佳。Regardless of the manufacturing method described above, in the manufacturing process of the microelectromechanical device, when the movable member of the microelectromechanical device is formed, it usually has to be completed by a grinding step. However, the grinding step is often accompanied by vibrations that cause some of the fine structures in the microelectromechanical device to be damaged. Moreover, in some MEMS devices, due to the overall configuration of the MEMS device, the spacing between the electrodes in some of the capacitor structures is too large, resulting in a decrease in capacitance, resulting in poor product performance.

因此,目前亟需一種新的微機電裝置及製造方法,期能改善上述問題。Therefore, there is a need for a new MEMS device and manufacturing method that can improve the above problems.

本發明之一態樣係提供一種微機電裝置。此微機電裝置包括一基材、一電路層、一微結構、一彈性支撐件、一導電層、一貫穿空間以及一下蓋體。電路層配置在基材的上表面,且電路層包含一主動元件以及一內連接墊。主動元件電性連接內連接墊。貫穿空間貫穿電路層及基材。微結構容置在貫穿空間中,且微結構包含一第一電極,其電性連接主動元件。彈性支撐件實體連接電路層與微結構,使微結構懸吊於貫穿空間中。導電層覆蓋並密封貫穿空間的上開口。導電層與微結構相對配置,且其間存在一第一間隙,使導電層和第一電極形成一第一電容結構。此外,導電層電性連接內連接墊。下蓋體覆蓋貫穿空間的下開口,因此下蓋體和導電層形成一封閉空間圍繞微結構。One aspect of the present invention provides a microelectromechanical device. The MEMS device includes a substrate, a circuit layer, a microstructure, an elastic support member, a conductive layer, a through space, and a lower cover. The circuit layer is disposed on the upper surface of the substrate, and the circuit layer includes an active component and an inner connection pad. The active component is electrically connected to the inner connection pad. The through space penetrates the circuit layer and the substrate. The microstructure is received in the through space, and the microstructure includes a first electrode electrically connected to the active component. The elastic support member physically connects the circuit layer and the microstructure to suspend the microstructure in the through space. The conductive layer covers and seals the upper opening through the space. The conductive layer is disposed opposite to the microstructure, and a first gap exists therebetween, so that the conductive layer and the first electrode form a first capacitor structure. In addition, the conductive layer is electrically connected to the inner connection pad. The lower cover covers the lower opening of the through space, so that the lower cover and the conductive layer form a closed space surrounding the microstructure.

根據本發明一實施例,上述微機電裝置更包括一第二保護層覆蓋並接觸導電層。According to an embodiment of the invention, the microelectromechanical device further includes a second protective layer covering and contacting the conductive layer.

根據本發明一實施例,上述微機電裝置更包括一上蓋體配置於導電層上方,且上蓋體與導電層間存在一第二間隙。According to an embodiment of the invention, the MEMS device further includes an upper cover disposed above the conductive layer, and a second gap exists between the upper cover and the conductive layer.

根據本發明一實施例,上述微機電裝置中的第一間隙具有一寬度為約0.1μm至約10μm。According to an embodiment of the invention, the first gap in the microelectromechanical device has a width of from about 0.1 μm to about 10 μm.

根據本發明一實施例,上述微機電裝置中的第二間隙具有一寬度為約5μm至約100μm。According to an embodiment of the invention, the second gap in the microelectromechanical device has a width of from about 5 μm to about 100 μm.

根據本發明一實施例,上述微機電裝置中的微結構更包括一第二電極,且電路層更包括一第三電極,第二電極與第三電極形成一第二電容結構。According to an embodiment of the invention, the microstructure in the MEMS device further includes a second electrode, and the circuit layer further includes a third electrode, and the second electrode and the third electrode form a second capacitor structure.

本發明之另一態樣係提供一種製造微機電裝置的方法。此方法包括:(a)形成一電路層於一基材之一上表面,電路層包含一具有第一電極之微結構:(b)形成一凹槽貫穿電路層並深入基材,使凹槽之一底部低於基材之上表面,其中凹槽圍繞微結構之周邊的一部分;(c)形成一犧牲層於電路層上,其中犧牲層覆蓋微結構之一上表面,且填充在凹槽內;(d)形成一導電層於犧牲層上,使導電層與第一電極形成一第一電容結構;(e)由基材之下表面一側移除基材的部分,以露出犧牲層;(f)移除犧牲層以釋放微結構;以及(g)配置一下蓋體於基材下方,下蓋體以及導電層形成一封閉空間圍繞微結構。Another aspect of the invention provides a method of making a microelectromechanical device. The method comprises: (a) forming a circuit layer on an upper surface of a substrate, the circuit layer comprising a microstructure having a first electrode: (b) forming a groove extending through the circuit layer and deep into the substrate to make the groove One of the bottoms is lower than the upper surface of the substrate, wherein the recess surrounds a portion of the periphery of the microstructure; (c) a sacrificial layer is formed on the circuit layer, wherein the sacrificial layer covers one of the upper surfaces of the microstructure and is filled in the recess (d) forming a conductive layer on the sacrificial layer such that the conductive layer forms a first capacitive structure with the first electrode; (e) removing a portion of the substrate from a side of the lower surface of the substrate to expose the sacrificial layer (f) removing the sacrificial layer to release the microstructure; and (g) arranging the cover under the substrate, the lower cover and the conductive layer forming a closed space surrounding the microstructure.

根據本發明一實施方式,其中步驟(a)之電路層更包括一主動元件、一內連接墊以及一第一保護層,其中主動元件電性連接第一電極以及內連接墊,且第一保護層位於電路層之一外表面並覆蓋內連接墊。According to an embodiment of the present invention, the circuit layer of the step (a) further includes an active component, an inner connection pad, and a first protection layer, wherein the active component is electrically connected to the first electrode and the inner connection pad, and the first protection The layer is on one of the outer surfaces of the circuit layer and covers the inner connection pads.

根據本發明一實施方式,其中步驟(a)包括形成一介電結構貫穿該電路層以及形成一金屬結構環繞該介電結構。在本實施方式中,步驟(b)包含依序以乾式蝕刻移除介電結構以及濕式蝕刻移除金屬結構以露出該基材;以及移除該露出基材之一部分以形成該凹槽。According to an embodiment of the invention, step (a) includes forming a dielectric structure through the circuit layer and forming a metal structure surrounding the dielectric structure. In the present embodiment, step (b) includes sequentially removing the dielectric structure by dry etching and wet etching to remove the metal structure to expose the substrate; and removing a portion of the exposed substrate to form the recess.

根據本發明一實施方式,步驟(c)包括形成一開口於該犧牲層上,且開口大致對準內連接墊,以露出位於內連接墊上方的第一保護層部分。在一實施例中,上述方法更包括:移出露出之第一保護層部分,以露出內連接墊。According to an embodiment of the invention, step (c) includes forming an opening on the sacrificial layer, and the opening is substantially aligned with the inner connection pad to expose the first protective layer portion above the inner connection pad. In one embodiment, the method further includes removing the exposed first protective layer portion to expose the inner connection pad.

根據本發明一實施方式,步驟(b)之底部與基材之上表面間之一垂直距離為約5 μm至約100 μm。According to an embodiment of the invention, the vertical distance between the bottom of step (b) and the upper surface of the substrate is from about 5 μm to about 100 μm.

根據本發明一實施方式,步驟(c)之犧牲層為有機光阻材料所製成。According to an embodiment of the invention, the sacrificial layer of step (c) is made of an organic photoresist material.

根據本發明一實施方式,步驟(e)包含:使用一研磨製程以由該基材之下表面一側移除該基材的部分,進而露出該犧牲層。According to an embodiment of the invention, step (e) comprises: using a polishing process to remove portions of the substrate from one side of the lower surface of the substrate to expose the sacrificial layer.

根據本發明一實施方式,其中步驟(e)包含:使用一研磨製程以由該基材之下表面一側移除該基材的部分以及以深式反應離子蝕刻經研磨之基材,以露出犧牲層。According to an embodiment of the present invention, the step (e) comprises: using a grinding process to remove a portion of the substrate from a side of the lower surface of the substrate and etching the ground substrate by deep reactive ion etching to expose the sacrifice Floor.

根據本發明一實施方式,步驟(f)係以一氧電漿移除犧牲層。According to an embodiment of the invention, step (f) removes the sacrificial layer with an oxygen plasma.

根據本發明一實施方式,上述方法更包括:形成一第二保護層覆蓋導電層,其中第二保護層具有一厚度為約0.5 μm至約10 μm。According to an embodiment of the invention, the method further includes: forming a second protective layer covering the conductive layer, wherein the second protective layer has a thickness of about 0.5 μm to about 10 μm.

根據本發明一實施方式,上述方法更包括:配置一上蓋體覆蓋導電層。According to an embodiment of the invention, the method further includes: configuring an upper cover to cover the conductive layer.

根據上述本發明實施方式之微機電裝置及其製造方法,俾能提高生產良率、產品穩定性及產品性能。According to the microelectromechanical device and the method of manufacturing the same according to the embodiments of the present invention described above, the production yield, product stability, and product performance can be improved.

請參照第1A圖,其為本發明一實施方式之微機電裝置的上視示意圖。第1A及1B圖係以一微機電加速度偵測器100為例說明,以易於瞭解本發明以下揭露的內容。本發明以下所揭露的微機電裝置及製造方法,可應用在其他產品或領域,因此本發明並不限於微機電加速度偵測器。本發明下文揭露的微機電裝置及製造方法中的實施方式或實施例,在有益的情形下可相互組合或取代,也可在一實施例中附加其他的實施例,而無須進一步的記載或說明。Please refer to FIG. 1A, which is a top view of a microelectromechanical device according to an embodiment of the present invention. 1A and 1B are illustrated by taking a microelectromechanical acceleration detector 100 as an example to facilitate understanding of the following disclosure of the present invention. The microelectromechanical device and the manufacturing method disclosed in the present invention can be applied to other products or fields, and thus the present invention is not limited to the microelectromechanical acceleration detector. The embodiments or the embodiments of the microelectromechanical device and the manufacturing method disclosed in the present invention may be combined or substituted with each other in an advantageous situation, and other embodiments may be added to an embodiment without further description or explanation. .

如第1A圖所示,微機電加速度偵測器100主要包括可動的微結構110、半導體電路120、複數個外連接墊130以及電路層140。半導體電路120大致配置在可動的微結構110之外圍。外連接墊130通常可配置在半導體電路120的外圍,用以連接至一外部電路。As shown in FIG. 1A, the microelectromechanical acceleration detector 100 mainly includes a movable microstructure 110, a semiconductor circuit 120, a plurality of external connection pads 130, and a circuit layer 140. The semiconductor circuit 120 is disposed substantially at the periphery of the movable microstructures 110. The outer connection pads 130 can generally be disposed on the periphery of the semiconductor circuit 120 for connection to an external circuit.

請參照第1A圖,電路層140具有一貫穿空間142,而微結構110容置在其中。微結構包括中心部112、至少一彈性支撐件114以及至少一第二電極116。彈性支撐件114連接中心部112與電路層140,使中心部112懸吊於貫穿空間142中,而呈現可移動的狀態。當一外力作用在中心部112時,中心部112可產生位移;當外力消失時,中心部112可藉由彈性支撐件114的彈性力而回到原來的位置。彈性支撐件114的寬度可例如為約0.1μm至約10μm。第二電極116由中心部112向外延伸至貫穿空間142中。此外,電路層140包含有一第三電極144,第三電極144向貫穿空間142延伸,並與第二電極116形成一電容結構。第二電極116及第三電極144的寬度可例如為約0.1μm至約10μm。Referring to FIG. 1A, the circuit layer 140 has a through space 142 in which the microstructures 110 are housed. The microstructure includes a central portion 112, at least one resilient support member 114, and at least one second electrode 116. The elastic support member 114 connects the central portion 112 and the circuit layer 140 such that the central portion 112 is suspended in the through space 142 to assume a movable state. When an external force acts on the center portion 112, the center portion 112 can be displaced; when the external force disappears, the center portion 112 can be returned to the original position by the elastic force of the elastic support member 114. The width of the elastic support 114 can be, for example, from about 0.1 μm to about 10 μm. The second electrode 116 extends outwardly from the central portion 112 into the through space 142. In addition, the circuit layer 140 includes a third electrode 144 extending toward the through space 142 and forming a capacitor structure with the second electrode 116. The width of the second electrode 116 and the third electrode 144 may be, for example, about 0.1 μm to about 10 μm.

第1B圖繪示本發明另一實施方式之微機電加速度偵測器100,其大致為沿著第1A圖中線段3-3’的剖面示意圖。微機電加速度偵測器100的可動的微結構110藉由類似於第1A圖繪示的彈性支撐件114而被懸吊在貫穿空間142中。微機電加速度偵測器100還包含一導電層390,其配置在微結構110上方。微結構110中具有第一電極334,且第一電極334與導電層390形成一電容結構。下文將更詳細敘述本發明一實施方式之微機電裝置的結構及特徵。FIG. 1B is a cross-sectional view of the microelectromechanical acceleration detector 100 according to another embodiment of the present invention, which is substantially along line 3-3' of FIG. 1A. The movable microstructure 110 of the MEMS acceleration detector 100 is suspended in the through space 142 by an elastic support 114 similar to that shown in FIG. 1A. The microelectromechanical acceleration detector 100 also includes a conductive layer 390 disposed over the microstructures 110. The microstructure 110 has a first electrode 334 therein, and the first electrode 334 and the conductive layer 390 form a capacitor structure. The structure and features of the microelectromechanical device of one embodiment of the present invention will be described in more detail below.

當微機電加速度偵測器100受到y方向的加速度時(如第1A圖所示),第二電極116與第三電極144之間的距離改變,使其間的電容值發生變化。同理,當微機電加速度偵測器100受到z方向的加速度時(如第1B圖所示),第一電極334與導電層390之間的距離改變,使其間的電容值發生變化。半導體電路120量測上述電容值或電容值的變化量,而得以估算微機電加速度偵測器100所受到各方向的加速度。When the MEMS acceleration detector 100 receives the acceleration in the y direction (as shown in FIG. 1A), the distance between the second electrode 116 and the third electrode 144 changes, and the capacitance value therebetween changes. Similarly, when the MEMS acceleration detector 100 is subjected to acceleration in the z direction (as shown in FIG. 1B), the distance between the first electrode 334 and the conductive layer 390 changes, and the capacitance value therebetween changes. The semiconductor circuit 120 measures the amount of change in the capacitance value or the capacitance value to estimate the acceleration of the MEMS acceleration detector 100 in various directions.

第2圖為本發明一實施方式之製造微機電裝置之方法200的流程圖。第3至16圖係繪示本發明實施方式之製造方法中各製程階段的剖面示意圖,其大致為第1圖中線段3-3’的剖面示意圖。2 is a flow chart of a method 200 of fabricating a microelectromechanical device in accordance with an embodiment of the present invention. 3 to 16 are schematic cross-sectional views showing respective process stages in the manufacturing method of the embodiment of the present invention, which is roughly a schematic cross-sectional view of the line segment 3-3' in Fig. 1.

進行步驟210,形成電路層於基材的上表面。在一實施方式中,如第3A圖所示,電路層320包含主動元件322、內連接墊324以及微結構330。微結構330具有第一電極334,其電性連接主動元件322。例如第一電極334可經由第1圖繪示的彈性支撐件114中而電性連接主動元件322。主動元件322可例如為互補式金屬氧化物半導體元件(CMOS)或雙極互補式金屬氧化物半導體元件(BiCMOS)。 內連接墊324位於電路層320的外側表面,且電性連接主動元件322。基材310可例如為矽晶圓或其他適合用以製造半導體元件的基材。Step 210 is performed to form a circuit layer on the upper surface of the substrate. In one embodiment, as shown in FIG. 3A, circuit layer 320 includes active component 322, inner connection pads 324, and microstructures 330. The microstructure 330 has a first electrode 334 electrically connected to the active element 322. For example, the first electrode 334 can be electrically connected to the active component 322 via the elastic support 114 illustrated in FIG. 1 . The active component 322 can be, for example, a complementary metal oxide semiconductor device (CMOS) or a bipolar complementary metal oxide semiconductor device (BiCMOS). The inner connection pad 324 is located on the outer surface of the circuit layer 320 and is electrically connected to the active component 322. Substrate 310 can be, for example, a germanium wafer or other substrate suitable for use in fabricating semiconductor components.

在另一實施方式中,如第3B圖所示,電路層320更包含特徵結構340填充於區域A中。特徵結構340圍繞微結構330之周邊的一部分,並貫穿電路層320。在後續的步驟中,特徵結構340將會被移除而形成第1A及1B圖繪示的貫穿空間142的一部分。換言之,特徵結構340預先填充在後續欲移除的區域A中。在此實施方式中,電路層320更包括一第一保護層326。第一保護層326位於電路層320的外表面,且覆蓋內連接墊324。第一保護層326的材料可例如為氧化矽。In another embodiment, as shown in FIG. 3B, circuit layer 320 further includes feature structure 340 filled in region A. Feature structure 340 surrounds a portion of the perimeter of microstructure 330 and extends through circuit layer 320. In a subsequent step, feature structure 340 will be removed to form a portion of through space 142 depicted in FIGS. 1A and 1B. In other words, the feature structure 340 is pre-filled in the area A to be subsequently removed. In this embodiment, the circuit layer 320 further includes a first protective layer 326. The first protective layer 326 is located on the outer surface of the circuit layer 320 and covers the inner connection pads 324. The material of the first protective layer 326 may be, for example, ruthenium oxide.

特徵結構340包含介電結構342以及金屬結構344。介電結構342貫穿電路層320,並接觸下方的基材310。介電結構342可例如為氧化矽或氮化矽,或由氧化矽及氮化矽堆疊而構成。金屬結構344也同樣貫穿電路層320,並且環繞介電結構342。換言之,金屬結構344形成在特徵結構340的外緣。更詳細而言,金屬結構344可包含344a及344b兩部分。金屬結構的344a部分實體連接電路層320與介電結構342;金屬結構的344b部分實體連接微結構330與介電結構342。Feature structure 340 includes a dielectric structure 342 and a metal structure 344. Dielectric structure 342 extends through circuit layer 320 and contacts underlying substrate 310. The dielectric structure 342 can be, for example, tantalum oxide or tantalum nitride, or a stack of tantalum oxide and tantalum nitride. Metal structure 344 also extends through circuit layer 320 and surrounds dielectric structure 342. In other words, the metal structure 344 is formed on the outer edge of the feature 340. In more detail, the metal structure 344 can comprise two portions 344a and 344b. The portion 344a of the metal structure physically connects the circuit layer 320 with the dielectric structure 342; the portion 344b of the metal structure physically connects the microstructure 330 with the dielectric structure 342.

在上述電路層320包含有特徵結構340的實施方式中,形成電路層320的步驟包括形成CMOS或BiCMOS的製程。在CMOS元件的標準製程中,可包括4道的金屬化製程以及2道的多晶矽化製程(2P4M製程),亦可包括5道的金屬化製程以及1道的多晶矽化製程(5M1P製程)。因此,在一實施例中,當形成CMOS元件322時,可藉由適當的光罩設計,同時形成特徵結構340。舉例而言,當形成CMOS元件322中的介電層時,可同時形成特徵結構340的介電結構342。當形成CMOS元件322的導電層時,可同時形成特徵結構340中部分的金屬結構344。當填充金屬於CMOS元件的連接孔(via)時,可同時形成金屬結構344的一部分。因此,能夠在形成CMOS元件322的同時,逐步形成特徵結構340。在一實施例中,填充在CMOS元件通孔的金屬為鎢,CMOS元件322的導電層為鋁。因此,金屬結構344可由鋁層及鎢層堆疊而成。亦即,金屬結構344可為多層結構,且至少由兩種金屬材料所構成。In embodiments in which the circuit layer 320 described above includes features 340, the step of forming the circuit layer 320 includes forming a CMOS or BiCMOS process. In the standard process of CMOS components, it can include four metallization processes and two polysiliconization processes (2P4M process), and can also include five metallization processes and one polysiliconization process (5M1P process). Thus, in an embodiment, when CMOS component 322 is formed, feature 340 can be formed simultaneously by a suitable reticle design. For example, when forming a dielectric layer in CMOS device 322, dielectric structure 342 of feature structure 340 can be formed simultaneously. When the conductive layer of CMOS element 322 is formed, portions of metal structure 344 in feature structure 340 can be formed simultaneously. When the metal is filled in the via of the CMOS device, a portion of the metal structure 344 can be formed simultaneously. Therefore, the feature structure 340 can be formed step by step while forming the CMOS element 322. In one embodiment, the metal filled in the via of the CMOS device is tungsten, and the conductive layer of the CMOS device 322 is aluminum. Therefore, the metal structure 344 can be formed by stacking an aluminum layer and a tungsten layer. That is, the metal structure 344 can be a multi-layer structure and composed of at least two metal materials.

在步驟220中,形成凹槽312貫穿電路層320並深入基材310,如第4圖所示。凹槽312的底部312b低於基材之上表面310a,且凹槽312圍繞微結構330之周邊的一部分。在後續步驟中,凹槽312將形成第1A及1B圖繪示的貫穿空間142的一部分。以下將示例性地敘述兩種形成凹槽312的實施方式。In step 220, a recess 312 is formed through the circuit layer 320 and into the substrate 310, as shown in FIG. The bottom 312b of the recess 312 is lower than the upper surface 310a of the substrate, and the recess 312 surrounds a portion of the perimeter of the microstructure 330. In a subsequent step, the recess 312 will form a portion of the through space 142 depicted in Figures 1A and 1B. Two embodiments of forming the recess 312 will be exemplarily described below.

在一實施方式中,可利用曝光、顯影及反應離子蝕刻(Reactive Ion Etching,RIE)移除電路層320中的介電材料,而在電路層320中形成第4A圖繪示的開口B,並露出開口B中的基材310。接著,在藉由例如深式反應離子蝕刻(Deep Reactive Ion Etching,DRIE)移除露出的基材310的一部分,而形成第4圖繪示的凹槽312。In one embodiment, the dielectric material in the circuit layer 320 can be removed by exposure, development, and reactive ion etching (RIE), and the opening B shown in FIG. 4A is formed in the circuit layer 320, and The substrate 310 in the opening B is exposed. Next, a portion of the exposed substrate 310 is removed by, for example, Deep Reactive Ion Etching (DRIE) to form a recess 312 as shown in FIG.

在電路層320包含有特徵結構340的實施方式中,先形成一光阻層350於電路層320及微結構330上,如第4B圖所示。光阻層350具有開口352,以露出特徵結構340。接著,以諸如反應性離子蝕刻(reactive ion etching,RIE)之乾式蝕刻法移除介電結構342,如第4C圖所示。反應性離子蝕刻僅會蝕刻諸如氧化矽及氮化矽之介電材料,不會蝕刻金屬材料。在進行反應性離子蝕刻的過程中,由於微結構330的側壁以及電路層320的側壁被金屬結構344覆蓋,所以反應性離子蝕刻不會傷害或蝕刻微結構330及電路層320的側壁,而使微結構330及電路層320的側壁得以保持原本的輪廓外觀。隨後,再以濕式蝕刻移除金屬結構344,如第4D圖所示。移除金屬結構344後,在電路層320中形成第4D圖繪示的開口B,並使開口B中的基材310暴露出來。濕式蝕刻採用的蝕刻劑對於金屬材料與氧化物材料(或氮化物)具有高的蝕刻選擇比,例如高於15:1或高於20:1或高於30:1或更高。因此,在移除金屬結構344時,幾乎不會損害微結構330及電路層320原本的側壁輪廓外觀。例如,蝕刻劑中包含硫酸和過氧化氫,硫酸與過氧化氫的重量比為約2:1。當然其他商品化的金屬蝕刻劑也可適用於本發明中。最後,在藉由例如深式反應離子蝕刻(Deep Reactive Ion Etching,DRIE)移除露出的基材310的一部分,而形成第4圖繪示的凹槽312。上述實施方式,可使微結構330的側壁與基材310上表面之間的夾角θ為約85度至約95度。此外,微結構330側壁及電路層320側壁的表面平整,有助於提高微機電裝置的性能以及產品品質穩定性。In an embodiment in which the circuit layer 320 includes the features 340, a photoresist layer 350 is formed over the circuit layer 320 and the microstructures 330, as shown in FIG. 4B. The photoresist layer 350 has an opening 352 to expose the features 340. Next, the dielectric structure 342 is removed by a dry etching method such as reactive ion etching (RIE) as shown in FIG. 4C. Reactive ion etching only etches dielectric materials such as hafnium oxide and tantalum nitride without etching the metal material. During the reactive ion etching process, since the sidewalls of the microstructure 330 and the sidewalls of the circuit layer 320 are covered by the metal structure 344, the reactive ion etching does not damage or etch the sidewalls of the microstructure 330 and the circuit layer 320. The sidewalls of the microstructures 330 and circuit layers 320 maintain their original contoured appearance. Subsequently, the metal structure 344 is removed by wet etching as shown in FIG. 4D. After the metal structure 344 is removed, the opening B shown in FIG. 4D is formed in the circuit layer 320, and the substrate 310 in the opening B is exposed. The etchant employed in the wet etching has a high etching selectivity for the metal material and the oxide material (or nitride), for example, higher than 15:1 or higher than 20:1 or higher than 30:1 or higher. Therefore, when the metal structure 344 is removed, the original sidewall profile appearance of the microstructure 330 and the circuit layer 320 is hardly impaired. For example, the etchant contains sulfuric acid and hydrogen peroxide, and the weight ratio of sulfuric acid to hydrogen peroxide is about 2:1. Of course, other commercially available metal etchants are also suitable for use in the present invention. Finally, a portion of the exposed substrate 310 is removed by, for example, Deep Reactive Ion Etching (DRIE) to form a recess 312 as shown in FIG. In the above embodiment, the angle θ between the sidewall of the microstructure 330 and the upper surface of the substrate 310 may be from about 85 degrees to about 95 degrees. In addition, the surface of the sidewalls of the microstructures 330 and the sidewalls of the circuit layer 320 are flat, which helps to improve the performance of the microelectromechanical device and the stability of the product quality.

在一實施例中,上述凹槽312的底部312b與基材310的上表面310a之間的垂直距離d為約5 μm至約100 μm,如第4圖所示。In one embodiment, the vertical distance d between the bottom 312b of the recess 312 and the upper surface 310a of the substrate 310 is from about 5 μm to about 100 μm, as shown in FIG.

在步驟230中,形成一犧牲層360於電路層320上,如第5圖所示。犧牲層360覆蓋微結構330的上表面332,且填充在凹槽312內。犧牲層360可例如為高分子材料所製成。舉例而言,犧牲層360可為一光阻材料,經圖案化後蓋微結構330並填充在凹槽312中。犧牲層360的材料可例如為酚醛樹脂型光阻、丙烯酸樹脂型光阻或其他有機材料。In step 230, a sacrificial layer 360 is formed over circuit layer 320, as shown in FIG. The sacrificial layer 360 covers the upper surface 332 of the microstructure 330 and is filled within the recess 312. The sacrificial layer 360 can be made, for example, of a polymer material. For example, the sacrificial layer 360 can be a photoresist material that is patterned to cover the microstructures 330 and fill the recesses 312. The material of the sacrificial layer 360 may be, for example, a phenol resin type photoresist, an acrylic type photoresist or other organic material.

在電路層320包含有內連接墊324及第一保護層326的實施方式中,犧牲層360具有一開口362,且開口360大致對準連接墊324,而露出位在內連接墊324上方部分的第一保護層326。在此實施方式中,可接續移出露出的第一保護層部分326,而露出內連接墊324,如第6圖所示。In embodiments in which the circuit layer 320 includes the inner connection pads 324 and the first protective layer 326, the sacrificial layer 360 has an opening 362, and the opening 360 is substantially aligned with the connection pads 324 to expose portions above the inner connection pads 324. The first protective layer 326. In this embodiment, the exposed first protective layer portion 326 can be successively removed to expose the inner connection pads 324 as shown in FIG.

在步驟240中,形成一導電層390於犧牲層360上,使導電層390與第一電極334形成一第一電容結構,如第7圖所示。在一實施例中,先藉由濺鍍製程沈積導電層,接著再進行光阻塗佈、曝光、顯影及蝕刻圖案化導電層,而形成導電層390。隨後,再進行去光阻(photoresist stripping)製程以移除導電層390上的光阻。在本實施例中,犧牲層360為光阻材料,因此在進行去光阻製程時,沒有被導電層390覆蓋的犧牲層360將一併被移除(例如第6圖繪示的犧牲層360a部分及360b部分)。在電路層320包含有內連接墊324的實施方式中,導電層390連接並接觸內連接墊324,讓導電層390可藉由內連接墊324而電性連接主動元件322。因此,可藉由主動元件322量測導電層390與第一電極334間形成的第一電容結構之電容值。導電層390的厚度可例如為約0.5μm至約10 μm。導電層390可例如為金、銀、鋁或銅等金屬材料或多晶矽所製成。In step 240, a conductive layer 390 is formed on the sacrificial layer 360 such that the conductive layer 390 forms a first capacitive structure with the first electrode 334, as shown in FIG. In one embodiment, the conductive layer is formed by depositing a conductive layer by a sputtering process, followed by photoresist coating, exposure, development, and etching of the patterned conductive layer. Subsequently, a photoresist stripping process is performed to remove the photoresist on the conductive layer 390. In this embodiment, the sacrificial layer 360 is a photoresist material, so when the photoresist process is performed, the sacrificial layer 360 not covered by the conductive layer 390 will be removed together (for example, the sacrificial layer 360a shown in FIG. 6 Part and 360b part). In an embodiment in which the circuit layer 320 includes the inner connection pads 324, the conductive layer 390 is connected to and in contact with the inner connection pads 324 such that the conductive layer 390 can be electrically connected to the active elements 322 by the inner connection pads 324. Therefore, the capacitance value of the first capacitor structure formed between the conductive layer 390 and the first electrode 334 can be measured by the active component 322. The thickness of the conductive layer 390 can be, for example, from about 0.5 μm to about 10 μm. The conductive layer 390 can be made of, for example, a metal material such as gold, silver, aluminum, or copper or polycrystalline germanium.

在另一實施方式中,在形成導電層390後,可形成一第二保護層392覆蓋導電層390,如第8圖所示。在一實施例中,第二保護層392位於導電層390以及電路層的上表面。在電路層320包含有第一保護層326的實施例中,第二保護層392形成在導電層390以及第一保護層326上。第二保護層392可例如為氮化矽或氧化矽所製成。第二保護層392的厚度可例如為約0.5 μm至約10 μm。第二保護層392用以保護下方的導電層390,並在後續移除犧牲層360的步驟後,第二保護層392有助於提高導電層390的機械強度。In another embodiment, after the conductive layer 390 is formed, a second protective layer 392 may be formed to cover the conductive layer 390, as shown in FIG. In an embodiment, the second protective layer 392 is located on the conductive layer 390 and the upper surface of the circuit layer. In embodiments where circuit layer 320 includes a first protective layer 326, a second protective layer 392 is formed over conductive layer 390 and first protective layer 326. The second protective layer 392 can be made, for example, of tantalum nitride or hafnium oxide. The thickness of the second protective layer 392 may be, for example, about 0.5 μm to about 10 μm. The second protective layer 392 serves to protect the underlying conductive layer 390, and after the step of subsequently removing the sacrificial layer 360, the second protective layer 392 helps to increase the mechanical strength of the conductive layer 390.

在又一實施方式中,在形成第二保護層392後,配置上蓋體370於電路層320上方,使上蓋體370覆蓋導電層390,如第9圖所示。上蓋體370用以保護最終形成的微機電裝置,上蓋體370可例如為玻璃或矽基板所製成。在一實施例中,上蓋體370可藉由一黏著層372而固定於電路層320上方。In still another embodiment, after the second protective layer 392 is formed, the upper cover 370 is disposed above the circuit layer 320, so that the upper cover 370 covers the conductive layer 390, as shown in FIG. The upper cover 370 is used to protect the finally formed microelectromechanical device, and the upper cover 370 can be made, for example, of a glass or tantalum substrate. In an embodiment, the upper cover 370 can be fixed above the circuit layer 320 by an adhesive layer 372.

在步驟250中,由基材310的下表面310b一側移除基材310的部分,以露出犧牲層360,如第10圖所示。在一實施方式中,可先研磨基材310的下表面310b,使基材310的厚度減少至一定厚度,例如將基材310的厚度研磨至約150μm。隨後,再以DRIE對基材310的下表面進行蝕刻,使基材310的下表面形成一凹陷314。凹陷314的深度足以使犧牲層360暴露出來,如第10圖所示。在其他實施方式中,可直接研磨基材310之下表面直到犧牲層露出為止,而不使用DRIE進行蝕刻。In step 250, portions of the substrate 310 are removed from the side of the lower surface 310b of the substrate 310 to expose the sacrificial layer 360, as shown in FIG. In one embodiment, the lower surface 310b of the substrate 310 may be first ground to reduce the thickness of the substrate 310 to a certain thickness, such as grinding the thickness of the substrate 310 to about 150 [mu]m. Subsequently, the lower surface of the substrate 310 is etched by DRIE to form a recess 314 on the lower surface of the substrate 310. The depth of the recess 314 is sufficient to expose the sacrificial layer 360, as shown in FIG. In other embodiments, the lower surface of the substrate 310 can be directly polished until the sacrificial layer is exposed without etching using DRIE.

習知技術中,在研磨基材的下表面時,常伴隨發生震動,而導致微結構中的細微結構因震動而受損。例如,第1圖繪示的彈性支撐件114或電極116、144的寬度通常僅為約0.1μm至約10μm,很容易因震動而受損。本發明之實施方式中,形成凹槽312後,再於凹槽312內填入犧牲層360,可以有效防止微結構因震動而受損壞。此外,填充在於凹槽312的犧牲層360,也可以避免在進行步驟240時,黏著層372或其他污染物進入凹槽312中。從而,根據本發明之實施方式,可以有效提高微機電裝置的良率。In the prior art, when the lower surface of the substrate is ground, vibration is often accompanied, and the fine structure in the microstructure is damaged by vibration. For example, the elastic support member 114 or the electrodes 116, 144 shown in Fig. 1 are typically only about 0.1 μm to about 10 μm wide and are easily damaged by vibration. In the embodiment of the present invention, after the recess 312 is formed, the sacrificial layer 360 is filled in the recess 312, which can effectively prevent the microstructure from being damaged by vibration. In addition, filling the sacrificial layer 360 in the recess 312 also prevents the adhesive layer 372 or other contaminants from entering the recess 312 when step 240 is performed. Thus, according to an embodiment of the present invention, the yield of the microelectromechanical device can be effectively improved.

在步驟260中,移除犧牲層360以釋放微結構330,如第11圖所示。在一實施方式中,可利用氧電漿移除犧牲層360,而形成一貫穿空間316。微結構330與導電層390之間形成一第一間隙h。在一實施例中,導電層390與微結構330間的間隙寬度h為約0.1 μm至約5μm,更明確而言,約0.1 μm至約2μm。在其他實施方式中,可利用其他化學溶劑來移除犧牲層360。換言之,可根據犧牲層360的材料性質或製程需求來改變或調整移除犧牲層360的方法。本文中,「釋放微結構」係指使微機電裝置產生具有可相對移動的構造或部件。具體而言,移除犧牲層360後,微結構330藉由彈性支撐件(未繪示於第12圖)而懸吊在貫穿空間316中,因此微結構330可相對電路層320而發生位移。In step 260, the sacrificial layer 360 is removed to release the microstructures 330, as shown in FIG. In one embodiment, the sacrificial layer 360 can be removed using oxygen plasma to form a through space 316. A first gap h is formed between the microstructures 330 and the conductive layer 390. In one embodiment, the gap width h between the conductive layer 390 and the microstructures 330 is from about 0.1 μm to about 5 μm, more specifically from about 0.1 μm to about 2 μm. In other embodiments, other chemical solvents may be utilized to remove the sacrificial layer 360. In other words, the method of removing the sacrificial layer 360 can be changed or adjusted depending on the material properties or process requirements of the sacrificial layer 360. As used herein, "releasing microstructure" means causing a microelectromechanical device to produce a structure or component that is relatively movable. Specifically, after the sacrificial layer 360 is removed, the microstructures 330 are suspended in the through space 316 by elastic supports (not shown in FIG. 12 ), and thus the microstructures 330 can be displaced relative to the circuit layers 320 .

在步驟270中,配置下蓋體380於基材310的下方,而形成微機電裝置300,如第12圖所示。下蓋體380以及導電層390形成一封閉空間C圍繞微結構330。微結構330可在封閉空間C中發生相對位移,而使微機電裝置產生預定的功能。上蓋體370及下蓋體380用以保護微結構330。下蓋體380的材料可與上蓋體370相同或不同。在一實施例中,下蓋體380可藉由一黏著層382而固定於基材310的下方。In step 270, the lower cover 380 is disposed below the substrate 310 to form the microelectromechanical device 300, as shown in FIG. The lower cover 380 and the conductive layer 390 form a closed space C surrounding the microstructures 330. The microstructures 330 can be relatively displaced in the enclosed space C to cause the microelectromechanical device to produce a predetermined function. The upper cover 370 and the lower cover 380 are used to protect the microstructures 330. The material of the lower cover 380 may be the same as or different from the upper cover 370. In an embodiment, the lower cover 380 can be fixed under the substrate 310 by an adhesive layer 382.

由上述實施方式可知,形成犧牲層360之後,接著在犧牲層360上方形成導電層390,因此可藉由控制犧牲層360的厚度而控制導電層390與微結構330之間的第一間隙h的寬度。根據本發明之實施方式,導電層390與第一電極334之間的距離可獲得良好控制。換言之,導電層390與第一電極334間的電容值可被精準控制,因此可提高產品穩定性。在另一方面,當導電層390與第一電極334之間的距離縮小,導電層390與第一電極334之間的電容值增加,亦有助於提昇產品的性能。It can be seen from the above embodiment that after the sacrificial layer 360 is formed, the conductive layer 390 is formed over the sacrificial layer 360, so that the first gap h between the conductive layer 390 and the microstructure 330 can be controlled by controlling the thickness of the sacrificial layer 360. width. According to an embodiment of the present invention, the distance between the conductive layer 390 and the first electrode 334 can be well controlled. In other words, the capacitance value between the conductive layer 390 and the first electrode 334 can be precisely controlled, thereby improving product stability. On the other hand, when the distance between the conductive layer 390 and the first electrode 334 is reduced, the capacitance value between the conductive layer 390 and the first electrode 334 is increased, which also contributes to the performance of the product.

藉由根據本發明之另一態樣,係提供一種微機電裝置300,如第12圖所示。微機電裝置300包括基材310、電路層320、微結構330、導電層390、貫穿空間316、下蓋體380以及彈性支撐件(未繪示於第12圖)。電路層320配置在基材310的上表面,且電路層320包含一主動元件322以及一內連接墊324。主動元件322電性連接內連接墊324。貫穿空間316貫穿電路層320及基材310。微結構330容置在貫穿空間316中,且微結構330包含一第一電極334,其電性連接主動元件322。彈性支撐件實體連接電路層320與微結構330,使微結構330懸吊於貫穿空間316中。導電層390覆蓋並密封貫穿空間316的上開口。導電層390與微結構330相對配置,且其間存在一第一間隙h,使導電層390和第一電極334形成一第一電容結構。此外,導電層390電性連接內連接墊324。下蓋體覆蓋貫穿空間316的下開口,因此下蓋體380和導電層390形成一封閉空間C圍繞微結構330。By providing another embodiment of the present invention, a microelectromechanical device 300 is provided, as shown in FIG. The microelectromechanical device 300 includes a substrate 310, a circuit layer 320, a microstructure 330, a conductive layer 390, a through space 316, a lower cover 380, and an elastic support member (not shown in FIG. 12). The circuit layer 320 is disposed on the upper surface of the substrate 310, and the circuit layer 320 includes an active component 322 and an inner connection pad 324. The active component 322 is electrically connected to the inner connection pad 324. The through space 316 extends through the circuit layer 320 and the substrate 310. The microstructures 330 are received in the through space 316, and the microstructures 330 include a first electrode 334 electrically connected to the active component 322. The elastic support physically connects the circuit layer 320 and the microstructures 330 such that the microstructures 330 are suspended in the through space 316. Conductive layer 390 covers and seals the upper opening through space 316. The conductive layer 390 is disposed opposite to the microstructure 330, and a first gap h exists therebetween, so that the conductive layer 390 and the first electrode 334 form a first capacitor structure. In addition, the conductive layer 390 is electrically connected to the inner connection pad 324. The lower cover covers the lower opening of the through space 316, so that the lower cover 380 and the conductive layer 390 form a closed space C surrounding the microstructures 330.

在一實施方式中,微機電裝置300更包括一第二保護層392以及一上蓋體370。第二保護層392覆蓋並接觸導電層390。上蓋體370位於第二保護層392上方,且上蓋體與第二保護層392間存在一第二間隙g。在一實施例中,第一間隙h的寬度為約0.1μm至約10μm。在另一實施例中,第二間隙g為寬度為約5μm至約100μm。In an embodiment, the MEMS device 300 further includes a second protective layer 392 and an upper cover 370. The second protective layer 392 covers and contacts the conductive layer 390. The upper cover 370 is located above the second protective layer 392, and a second gap g exists between the upper cover and the second protective layer 392. In an embodiment, the first gap h has a width of from about 0.1 μm to about 10 μm. In another embodiment, the second gap g is from about 5 [mu]m to about 100 [mu]m wide.

在另一實施方式中,如第1A圖所示,微結構110更包括一第二電極116,且電路層更包括一第三電極144。第二電極116與第三電極144位於貫穿空間中,且第二電極116與第三電極144形成一第二電容結構。In another embodiment, as shown in FIG. 1A, the microstructure 110 further includes a second electrode 116, and the circuit layer further includes a third electrode 144. The second electrode 116 and the third electrode 144 are located in the through space, and the second electrode 116 and the third electrode 144 form a second capacitor structure.

雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100...微機電加速度偵測器100. . . MEMS acceleration detector

110...微結構110. . . microstructure

112...中心部112. . . Central department

114...彈性支撐件114. . . Elastic support

116...第二電極116. . . Second electrode

120...半導體電路120. . . Semiconductor circuit

130...外連接墊130. . . Outer connection pad

140...基材140. . . Substrate

142...貫穿空間142. . . Through space

144...第三電極144. . . Third electrode

200...方法200. . . method

210、220、230、240、250、260、270...步驟210, 220, 230, 240, 250, 260, 270. . . step

300...微機電裝置300. . . Microelectromechanical device

310...基材310. . . Substrate

310a...上表面310a. . . Upper surface

310b...下表面310b. . . lower surface

312...凹槽312. . . Groove

312b...底部312b. . . bottom

314...凹陷314. . . Depression

316...貫穿空間316. . . Through space

320...電路層320. . . Circuit layer

322...主動元件322. . . Active component

324...內連接墊324. . . Inner connection pad

326...第一保護層326. . . First protective layer

330...微結構330. . . microstructure

332...上表面332. . . Upper surface

334...第一電極334. . . First electrode

340...特徵結構340. . . Feature structure

342...介電結構342. . . Dielectric structure

344...金屬結構344. . . Metal structure

350...光阻層350. . . Photoresist layer

352...開口352. . . Opening

360...犧牲層360. . . Sacrificial layer

362...開口362. . . Opening

370...上蓋體370. . . Upper cover

372...黏著層372. . . Adhesive layer

380...下蓋體380. . . Lower cover

382...黏著層382. . . Adhesive layer

390...導電層390. . . Conductive layer

392...第二保護層392. . . Second protective layer

A...區域A. . . region

B...開口B. . . Opening

C...封閉空間C. . . Closed space

d...距離d. . . distance

θ...夾角θ. . . Angle

h...第一間隙h. . . First gap

g...第二間隙g. . . Second gap

第1A圖係繪示本發明一實施方式之微機電裝置的上視示意圖。1A is a top plan view showing a microelectromechanical device according to an embodiment of the present invention.

第1B圖係繪示本發明另一實施方式之微機電裝置的剖面示意圖。1B is a cross-sectional view showing a microelectromechanical device according to another embodiment of the present invention.

第2圖係繪示本發明一實施方式之製造微機電裝置之方法的流程圖。2 is a flow chart showing a method of manufacturing a microelectromechanical device according to an embodiment of the present invention.

第3A至12圖係繪示本發明實施方式之製造微機電裝置方法中各製程階段的剖面示意圖。3A to 12 are schematic cross-sectional views showing respective process stages in the method of fabricating a microelectromechanical device according to an embodiment of the present invention.

200...方法200. . . method

210、220、230、240、250、260、270...步驟210, 220, 230, 240, 250, 260, 270. . . step

Claims (19)

一種製造微機電裝置之方法,包括:(a)形成一電路層於一基材之一上表面,該電路層包含一微結構,其具有一第一電極:(b)形成一凹槽貫穿該電路層並深入該基材,使該凹槽之一底部低於該基材之上表面,其中該凹槽圍繞該微結構之周邊的一部分;(c)形成一犧牲層於該電路層上,其中該犧牲層覆蓋該微結構之一上表面,且填充在該凹槽內;(d)形成一導電層於該犧牲層上,使該導電層與該第一電極形成一第一電容結構;(e)由該基材之下表面一側移除該基材的部分,以露出該犧牲層;(f)移除該犧牲層以釋放該微結構;以及(g)配置一下蓋體於該基材下方,該下蓋體以及該導電層形成一封閉空間圍繞該微結構。 A method of fabricating a microelectromechanical device, comprising: (a) forming a circuit layer on an upper surface of a substrate, the circuit layer comprising a microstructure having a first electrode: (b) forming a recess therethrough a circuit layer and deep into the substrate such that a bottom of the recess is lower than an upper surface of the substrate, wherein the recess surrounds a portion of the periphery of the microstructure; (c) forming a sacrificial layer on the circuit layer, Wherein the sacrificial layer covers an upper surface of the microstructure and is filled in the recess; (d) forming a conductive layer on the sacrificial layer to form a first capacitor structure between the conductive layer and the first electrode; (e) removing a portion of the substrate from a side of the lower surface of the substrate to expose the sacrificial layer; (f) removing the sacrificial layer to release the microstructure; and (g) arranging the cover Below the substrate, the lower cover and the conductive layer form a closed space surrounding the microstructure. 如請求項1所述之方法,其中步驟(a)之該電路層更包括一主動元件、一內連接墊以及一第一保護層,其中該主動元件電性連接該第一電極以及該內連接墊,且該第一保護層位於該電路層之一外表面並覆蓋該內連接墊。 The method of claim 1, wherein the circuit layer of the step (a) further comprises an active component, an inner connecting pad and a first protective layer, wherein the active component is electrically connected to the first electrode and the inner connecting a pad, and the first protective layer is located on an outer surface of the circuit layer and covers the inner connection pad. 如請求項2所述之方法,其中步驟(a)包括:形成一介電結構貫穿該電路層以及形成一金屬結構環 繞該介電結構;且其中步驟(b)包括:依序以乾式蝕刻移除該介電結構以及濕式蝕刻移除該金屬結構,以露出該基材;以及移除該露出基材之一部分,以形成該凹槽。 The method of claim 2, wherein the step (a) comprises: forming a dielectric structure through the circuit layer and forming a metal structure ring Wrap the dielectric structure; and wherein step (b) comprises: sequentially removing the dielectric structure by dry etching and wet etching to remove the metal structure to expose the substrate; and removing a portion of the exposed substrate To form the groove. 如請求項3所述之方法,更包含:形成一開口於該犧牲層上,且該開口對準該內連接墊,以露出位於該內連接墊上方的該第一保護層部分。 The method of claim 3, further comprising: forming an opening on the sacrificial layer, and the opening is aligned with the inner connecting pad to expose the first protective layer portion above the inner connecting pad. 如請求項4所述之方法,更包括:移出該露出之第一保護層部分,以露出該內連接墊。 The method of claim 4, further comprising: removing the exposed first protective layer portion to expose the inner connection pad. 如請求項5所述之方法,其中該導電層接觸該內連接墊。 The method of claim 5, wherein the conductive layer contacts the inner connection pad. 如請求項1所述之方法,其中步驟(b)之該底部與該基材之上表面間之一垂直距離為約5μm至約100μm。 The method of claim 1, wherein a vertical distance between the bottom of the step (b) and the upper surface of the substrate is from about 5 μm to about 100 μm. 如請求項1所述之方法,其中步驟(c)之該犧牲層為一有機光阻材料。 The method of claim 1, wherein the sacrificial layer of the step (c) is an organic photoresist material. 如請求項1所述之方法,其中步驟(e)包含:使用一研磨製程以由該基材之下表面一側移除該基材的部分,進而露出該犧牲層。 The method of claim 1, wherein the step (e) comprises: removing a portion of the substrate from a side of the lower surface of the substrate using a polishing process to expose the sacrificial layer. 如請求項1所述之方法,其中步驟(e)包含:使用一研磨製程以由該基材之下表面一側移除該基材的部分;以及以深式反應離子蝕刻該經研磨之基材,以露出該犧牲層。 The method of claim 1, wherein the step (e) comprises: using a polishing process to remove a portion of the substrate from a side of the lower surface of the substrate; and etching the ground substrate by deep reactive ion etching To expose the sacrificial layer. 如請求項1所述之方法,其中步驟(f)係以一氧電漿移除該犧牲層。 The method of claim 1, wherein the step (f) removes the sacrificial layer with an oxygen plasma. 如請求項1所述之方法,更包括:形成一第二保護層覆蓋該導電層,其中該第二保護層具有一厚度為約0.5μm至約10μm。 The method of claim 1, further comprising: forming a second protective layer covering the conductive layer, wherein the second protective layer has a thickness of about 0.5 μm to about 10 μm. 如請求項1所述之方法,更包括:配置一上蓋體覆蓋該導電層。 The method of claim 1, further comprising: configuring an upper cover to cover the conductive layer. 一種微機電裝置,包括:一基材;一電路層,形成於該基材之一上表面,該電路層包含一主動元件以及一內連接墊電性連接該主動元件; 一貫穿空間,貫穿該電路層及該基材;一微結構,容置於該貫穿空間中,且該微結構包含一第一電極,其電性連接該主動元件;一彈性支撐件,實體連接該電路層與該微結構,使該微結構懸吊於該貫穿空間中;一導電層,覆蓋並密封該貫穿空間之一上開口,且該導電層與該微結構間存在一第一間隙,其中該導電層和該第一電極形成一第一電容結構,且該導電層電性連接該內連接墊;以及一下蓋體,覆蓋該貫穿空間之一下開口,且該下蓋體以及該導電層形成一封閉空間圍繞該微結構。 A microelectromechanical device comprising: a substrate; a circuit layer formed on an upper surface of the substrate, the circuit layer comprising an active component and an inner connecting pad electrically connecting the active component; a penetrating space, through the circuit layer and the substrate; a microstructure, is received in the through space, and the microstructure comprises a first electrode electrically connected to the active component; an elastic support member, a physical connection The circuit layer and the microstructure structure suspend the microstructure in the through space; a conductive layer covers and seals an opening in one of the through spaces, and a first gap exists between the conductive layer and the microstructure The conductive layer and the first electrode form a first capacitor structure, and the conductive layer is electrically connected to the inner connecting pad; and the lower cover covers an opening of the through space, and the lower cover and the conductive layer A closed space is formed around the microstructure. 如請求項14所述之微機電裝置,更包括一第二保護層覆蓋並接觸該導電層。 The MEMS device of claim 14, further comprising a second protective layer covering and contacting the conductive layer. 如請求項14所述之微機電裝置,更包括一上蓋體配置於該導電層上方,且該上蓋體與該導電層間存在一第二間隙。 The MEMS device of claim 14, further comprising an upper cover disposed above the conductive layer, and a second gap between the upper cover and the conductive layer. 如請求項16所述之微機電裝置,其中該第二間隙具有一寬度為約5μm至約100μm。 The MEMS device of claim 16, wherein the second gap has a width of from about 5 μm to about 100 μm. 如請求項14所述之微機電裝置,其中該第一間隙具有一寬度為約0.1μm至約10μm。 The MEMS device of claim 14, wherein the first gap has a width of from about 0.1 μm to about 10 μm. 如請求項14所述之微機電裝置,其中該微結構更包括一第二電極,且該電路層更包括一第三電極,該第二電極與該第三電極位於該貫穿空間中,且形成一第二電容結構。The MEMS device of claim 14, wherein the microstructure further comprises a second electrode, and the circuit layer further comprises a third electrode, the second electrode and the third electrode are located in the through space, and are formed A second capacitor structure.
TW100115989A 2011-05-06 2011-05-06 Micro-electromechanical device and method for manufacturing micro-electromechanical device TWI483892B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW100115989A TWI483892B (en) 2011-05-06 2011-05-06 Micro-electromechanical device and method for manufacturing micro-electromechanical device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW100115989A TWI483892B (en) 2011-05-06 2011-05-06 Micro-electromechanical device and method for manufacturing micro-electromechanical device

Publications (2)

Publication Number Publication Date
TW201245030A TW201245030A (en) 2012-11-16
TWI483892B true TWI483892B (en) 2015-05-11

Family

ID=48094225

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100115989A TWI483892B (en) 2011-05-06 2011-05-06 Micro-electromechanical device and method for manufacturing micro-electromechanical device

Country Status (1)

Country Link
TW (1) TWI483892B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101434375A (en) * 2007-11-16 2009-05-20 微智半导体股份有限公司 Method for manufacturing semiconductor micro electromechanical structure
TW200926310A (en) * 2007-12-04 2009-06-16 Memsmart Semiconductor Corp Method for fabricating a seal chamber microstructure
TW200925101A (en) * 2007-12-14 2009-06-16 Memsmart Semiconductor Corp A micro suspended structure and its manufacturing method
TW200943407A (en) * 2008-04-03 2009-10-16 Memsmart Semiconductor Corp Micro-suspension structure for a compatible semiconductor device and a fabricating method for the same
TW201000391A (en) * 2008-06-18 2010-01-01 Memsmart Semiconductor Corp Micro electromechanical pre treatment manufacturing method and its structure for an integral semiconductor process
TW201002610A (en) * 2008-07-14 2010-01-16 Memsmart Semiconductor Corp Manufacturing method of microstructure for an integral semiconductor process

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101434375A (en) * 2007-11-16 2009-05-20 微智半导体股份有限公司 Method for manufacturing semiconductor micro electromechanical structure
TW200926310A (en) * 2007-12-04 2009-06-16 Memsmart Semiconductor Corp Method for fabricating a seal chamber microstructure
TW200925101A (en) * 2007-12-14 2009-06-16 Memsmart Semiconductor Corp A micro suspended structure and its manufacturing method
TW200943407A (en) * 2008-04-03 2009-10-16 Memsmart Semiconductor Corp Micro-suspension structure for a compatible semiconductor device and a fabricating method for the same
TW201000391A (en) * 2008-06-18 2010-01-01 Memsmart Semiconductor Corp Micro electromechanical pre treatment manufacturing method and its structure for an integral semiconductor process
TW201002610A (en) * 2008-07-14 2010-01-16 Memsmart Semiconductor Corp Manufacturing method of microstructure for an integral semiconductor process

Also Published As

Publication number Publication date
TW201245030A (en) 2012-11-16

Similar Documents

Publication Publication Date Title
US9815685B2 (en) Semiconductor sensing structure and manufacturing method thereof
US9463975B2 (en) MEMS capacitive pressure sensors
US8252695B2 (en) Method for manufacturing a micro-electromechanical structure
US11167979B2 (en) Microelectromechanical systems (MEMS) structure to prevent stiction after a wet cleaning process
US12043537B2 (en) Method of manufacturing a microelectromechanical systems (MEMS) device
TWI733711B (en) Semiconductor structure and manufacturing method thereof
TW202108495A (en) Microphone, microelectromechanical systems device and method for manufacturing thereof
US20150259196A1 (en) Mems device and method of manufacturing the same
US11708262B2 (en) Manufacturing method of semiconductor structure
TWI483892B (en) Micro-electromechanical device and method for manufacturing micro-electromechanical device
CN107764459B (en) Pressure sensor and method for manufacturing the same
TWI829795B (en) Method of manufacturing a semiconductor transducer device with multilayer diaphragm and semiconductor transducer device with multilayer diaphragm
TWI477436B (en) Method for manufacturing a micro-electromechanical device
TWI419263B (en) A micro-electromechanical device and method for manufacturing the same
TWI445132B (en) Method for forming a penetrating space in a circuitry layer and method for manufacturing a micro-electromechanical device
TWI623733B (en) Pressure sensor and manufacture method thereof
TWI458409B (en) Micro-electromechanical device and method manufacturing the same
TWI445131B (en) Method for manufacturing a micro-electromechanical structure
CN102234098A (en) Manufacturing method of micro electromechanical structure

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees