TWI458409B - Micro-electromechanical device and method manufacturing the same - Google Patents

Description

Microelectromechanical device and method of manufacturing same

The present invention relates to a method of fabricating a microelectromechanical device and a microelectromechanical device.

With the advancement of semiconductor process technology, the development of microelectromechanical systems (MEMS) has been promoted. In the manufacturing method of the conventional micromechanical system, the active component process and the microelectromechanical process are performed separately, and after the active component circuit and the microelectromechanical device are respectively completed, the two are integrated on the same substrate to complete the MEMS system. The above manufacturing method is also called "System In Package" (SIP).

Another conventional manufacturing method is to form a microelectromechanical structure after forming semiconductor elements such as a metal oxide semiconductor device (MOS) and a bipolar junction transistor (BJT) in an active device circuit, and then A wafer level MEMS is completed by performing a metallization process of the active device circuit. The wafer is then diced into wafers (Die) and finally wafer packaged.

Regardless of the manufacturing method described above, in the manufacturing process of a microelectromechanical device, a plasma etching method such as reactive ion etching (RIE) is generally employed to form a movable member or portion of the microelectromechanical device. However, the profile of the microelectromechanical device formed in the above manner is not ideal. Therefore, there is a need for a new manufacturing method that will improve the above problems.

It is an object of the present invention to provide a method of fabricating a microelectromechanical device that can form a desired etch profile in a microelectromechanical structure. Another object of the present invention is to provide an improved microelectromechanical device.

One aspect of the present invention provides a method of fabricating a microelectromechanical device. The method comprises the steps of: (a) forming a circuit layer and a microstructure on an upper surface of a substrate, wherein the circuit layer comprises an active component, and the microstructure is electrically connected to the active component; (b) forming a first The recess penetrates the circuit layer and penetrates into the substrate such that one of the bottoms of the first recess is lower than the upper surface of the substrate, wherein the first recess surrounds a portion of the periphery of the microstructure; (c) an upper cover is disposed above the circuit layer And covering the microstructure and the first groove; (d) removing a portion of the substrate located under the first groove and the microstructure from a lower surface side of the substrate to form a second groove, so that the second Forming a substrate residue between the bottom of one of the grooves and the bottom of the first groove; and (e) removing the residual portion of the substrate to release the microstructure.

According to an embodiment of the present invention, after the step (e), the cover body is disposed under the substrate, so that the lower cover body and the upper cover body form a closed space surrounding the microstructure.

According to an embodiment of the invention, the circuit layer of step (a) further comprises a connection pad and a protective layer, wherein the connection pad is electrically connected to the active component, and the protective layer covers the connection pad.

According to an embodiment of the present invention, after step (e), the method further includes removing a portion of the upper cover to expose a portion of the protective layer, and the exposed portion is overlapped with the connection pad; and removing the exposed portion of the protective layer to expose the connection pad.

According to an embodiment of the invention, the active component of step (a) is a complementary metal oxide semiconductor component or a bipolar complementary metal oxide semiconductor component.

According to an embodiment of the invention, wherein the vertical distance between the bottom of the first groove of step (b) and the upper surface is from about 5 μm to about 100 μm.

According to an embodiment of the invention, the cover body in step (c) comprises a positioning mark.

According to an embodiment of the present invention, wherein the step (d) comprises grinding a lower surface of the substrate; forming a patterned photoresist layer on the polished surface of the substrate; and removing the exposed substrate by deep reactive ion etching Part to form a second groove.

According to an embodiment of the invention, the substrate residue of step (d) has a thickness of from about 10 μm to about 150 μm.

In accordance with an embodiment of the present invention, step (e) includes planarly etching the underlying surface of the substrate to remove residual portions of the substrate.

Another aspect of the invention provides a method of making a microelectromechanical device. The method comprises the steps of: forming a circuit layer and a microstructure on an upper surface of a substrate, the circuit layer comprising a feature structure surrounding a portion of the periphery of the microstructure, and the feature structure extending through the circuit layer, wherein the feature structure comprises a dielectric structure and a metal structure; the dielectric structure extends through the circuit layer; the metal structure extends through the circuit layer and surrounds the dielectric structure. The feature structure is removed to expose the upper surface, wherein removing the feature comprises sequentially removing the dielectric structure by dry etching and wet etching to remove the metal structure. A portion of the exposed substrate is removed to form a first recess, wherein the first recess has a bottom that is lower than the upper surface. An upper cover body is disposed above the circuit layer to cover the microstructure and the first recess. Removing a portion of the substrate below the first recess and the microstructure from a lower surface side of the substrate to form a second recess such that one of the bottom of the second recess and the bottom of the first recess A substrate residue is formed between the substrates. The substrate residue is then removed to release the microstructure.

According to still another aspect of the present invention, a microelectromechanical device includes a substrate, a circuit layer, a through space, a movable microstructure, and an elastic support member. The circuit layer is formed on one surface of the substrate, and the circuit layer includes an active component. The through-space penetrates the circuit layer and the substrate to form an upper opening and a lower opening respectively in the circuit layer and the substrate, wherein a cross-sectional area of one of the lower openings is larger than a cross-sectional area of the upper opening. The movable microstructure is accommodated in the through space, and forms a capacitor with the circuit layer, and the movable microstructure is electrically connected to the active component via the capacitor. The resilient support physically connects the movable microstructure to the circuit layer.

According to an embodiment of the invention, the movable microstructure includes at least one first electrode extending into the through space, and the circuit layer includes at least one second electrode extending to the through space, and the first electrode and the second electrode form a capacitance.

Please refer to FIG. 1 , which is a top view of a microelectromechanical device according to an embodiment of the present invention. The microelectromechanical device can be applied to a microelectromechanical inertial sensing device such as an accelerometer or a gyroscope. FIG. 1 illustrates a microelectromechanical acceleration detector, but the manufacturing method disclosed in the present invention is applicable to other microelectromechanical devices, and is not limited to a microelectromechanical acceleration detector.

As shown in FIG. 1 , the MEMS acceleration detector 100 mainly includes a movable microstructure 110 , a semiconductor circuit 120 , a plurality of connection pads 130 , and a circuit layer 140 . The semiconductor circuit 120 is disposed substantially at the periphery of the movable microstructures 110. The connection pads 130 are typically configurable on the periphery of the semiconductor circuit 120.

The microstructure 110 is received in the through space 142 of the circuit layer 140 , and the microstructure includes a central portion 112 , at least one elastic support 114 , and at least one first electrode 116 . The elastic support member 114 connects the central portion 112 with the circuit layer 140 and causes the central portion 112 to assume a movable state. When an external force acts on the center portion 112, the center portion 112 can be displaced; when the external force disappears, the center portion 112 can return to the original position. The width of the elastic support 114 can be, for example, from about 0.5 μm to about 10 μm. The first electrode 116 extends outwardly from the central portion 112 into the through space 142. The width of the first electrode 116 may be, for example, from about 0.1 μm to about 10 μm.

The circuit layer 140 includes a second electrode 144 extending toward the through space 142 and forming a capacitance with the first electrode 116.

The semiconductor circuit 120 is electrically connected to the second electrode 144 and the first electrode 116 to measure the capacitance between the two electrodes 116 and 144 and convert the measured capacitance signal into a voltage or current signal. Semiconductor circuit 120 can include a complementary metal oxide semiconductor device. The semiconductor circuit 120 can be electrically connected to an external circuit (not shown) via the connection pad 130.

In operation, when the MEMS acceleration detector 100 is subjected to an acceleration, the distance between the second electrode 144 and the first electrode 116 changes, and the capacitance value therebetween changes. The semiconductor circuit 120 measures the amount of change in the capacitance value or the capacitance value to estimate the acceleration received by the MEMS acceleration detector 100.

The above described microelectromechanical acceleration detector 100 is merely an illustrative example to facilitate an understanding of the manufacturing methods disclosed herein, and the manufacturing methods disclosed herein may be used to fabricate other microelectromechanical devices. Furthermore, the embodiments disclosed in the following may be combined or substituted with each other in an advantageous manner, and other embodiments may be added to an embodiment without further description or description.

2 is a flow chart of a method 200 of fabricating a microelectromechanical device in accordance with an embodiment of the present invention. 3A to 10 are schematic cross-sectional views showing respective stages of the process in the manufacturing method of the embodiment of the present invention, which is roughly a schematic cross-sectional view of the line segment 3-3' in Fig. 1.

In step 210, circuit layer 320 and microstructures 330 are formed on the upper surface of substrate 310. Substrate 310 can be, for example, a germanium wafer or other substrate suitable for use in fabricating semiconductor components. In one embodiment, as shown in FIG. 3A, circuit layer 320 is formed around microstructures 330. The circuit layer 320 includes an active component 322, a connection pad 324, and a protective layer 326. The microstructures 330 can be electrically connected to the active components 322 via appropriate paths in the circuit layers. The active component 322 can be, for example, a complementary metal oxide semiconductor device (CMOS) or a bipolar complementary metal oxide semiconductor device (BiCMOS). The connection pad 324 is for connecting to an external circuit, and the connection pad 324 is electrically connected to the active element 322. The protective layer 326 covers the connection pads 324, and the material of the protective layer 326 may be, for example, ruthenium oxide. In one embodiment, the step of forming the circuit layer 320 includes forming the first electrode 116 and the second electrode 144, and the first and second electrodes 116, 144 form a capacitor structure, as shown in FIG.

In another embodiment, as shown in FIG. 3B, circuit layer 320 further includes feature structure 340 filled in region A. Feature structure 340 surrounds a portion of the perimeter of microstructure 330 and extends through circuit layer 320. In a subsequent step, feature structure 340 will be removed to form a portion of through space 142 depicted in FIG. In other words, the feature structure 340 is pre-filled in the area A to be subsequently removed.

Feature structure 340 includes a dielectric structure 342 and a metal structure 344. Dielectric structure 342 extends through circuit layer 320 and contacts underlying substrate 310. The dielectric structure 342 can be, for example, tantalum oxide or tantalum nitride, or a stack of tantalum oxide and tantalum nitride. Metal structure 344 also extends through circuit layer 320 and surrounds dielectric structure 342. In other words, the metal structure 344 is formed on the outer edge of the feature 340. In more detail, the metal structure 344 can comprise two portions 344a and 344b. A portion 344a of the metal structure is between the dielectric structure 342 and the active element 322; a portion 344b of the metal structure physically connects the microstructure 330 to the dielectric structure 342.

In embodiments in which the circuit layer 320 described above includes features 340, the step of forming the circuit layer 320 includes the steps of forming a CMOS or BiCMOS process. In the standard process of CMOS components, it can include four metallization processes and two polysiliconization processes (2P4M process), and can also include five metallization processes and one polysiliconization process (5M1P process). Thus, in an embodiment, when CMOS component 322 is formed, feature 340 can be formed simultaneously by a suitable reticle design. For example, when forming a dielectric layer in CMOS device 322, dielectric structure 342 of feature structure 340 can be formed simultaneously. When the metal layer of CMOS element 322 is formed, portions of metal structure 344 in feature structure 340 can be formed simultaneously. When the metal is filled in the via of the CMOS element, another portion of the metal structure 344 can be formed simultaneously. Therefore, the feature structure 340 can be formed step by step while forming the CMOS element 322. In one embodiment, the metal filled in the via of the CMOS device is tungsten, and the metal layer of the CMOS device 322 is aluminum. Therefore, the metal structure 344 may be formed by stacking an aluminum layer 345 and a tungsten layer 346. That is, in the present embodiment, the metal structure 344 is a multilayer structure and is composed of at least two metal materials.

In step 220, a first recess 312 is formed through the circuit layer 320 and deep into the substrate 310, as shown in FIG. The bottom 312b of the first recess 312 is lower than the upper surface 310a of the substrate, and the first recess 312 surrounds a portion of the perimeter of the microstructure 330. In a subsequent step, the first groove 312 will form a through space 142 as shown in FIG. Two embodiments for forming the first groove 312 will be exemplarily described below.

In the embodiment shown in FIG. 3A, a photoresist layer 350 may be formed on the circuit layer 320, and an opening 352 is formed in the photoresist layer 350 by an exposure and development process. Subsequently, the dielectric material in the circuit layer 320 is removed by reactive ion etching (RIE), and the opening B shown in FIG. 4A is formed in the circuit layer 320, and the substrate 310 in the opening B is exposed. . Then, a portion of the exposed substrate 310 is removed by, for example, Deep Reactive Ion Etching (DRIE) to form a first recess 312 as shown in FIG.

In one embodiment, the vertical distance d between the bottom 312b of the first recess 312 and the upper surface 310a of the substrate 310 is from about 5 μm to about 100 μm, as shown in FIG.

In the embodiment illustrated in FIG. 3B, a photoresist layer 350 may be formed on the circuit layer 320. The photoresist layer 350 has an opening 352 to expose the features 340.

Next, the dielectric structure 342 is removed by a dry etching method such as reactive ion etching (RIE) as shown in FIG. 4B. Reactive ion etching only etches dielectric materials such as hafnium oxide and tantalum nitride without etching the metal material. During the reactive ion etching process, since the sidewalls of the microstructure 330 and the sidewalls of the circuit layer 320 are covered by the metal structure 344, the reactive ion etching does not damage or etch the sidewalls of the microstructure 330 and the circuit layer 320, thereby making micro The sidewalls of structure 330 and circuit layer 320 are maintained in their original contoured appearance.

Subsequently, the metal structure 344 is removed by wet etching. After the metal structure 344 is removed, a structure as shown in FIG. 4A is formed in the circuit layer 320. The etchant employed in the wet etching has a high etching selectivity for the metal material and the oxide material (or nitride), for example, higher than 15:1 or higher than 20:1 or higher than 30:1 or higher. Therefore, when the metal structure 344 is removed, the sidewalls around the microstructure 330 and the region A of the circuit layer 320 are hardly damaged. In one embodiment, the etchant may comprise sulfuric acid and hydrogen peroxide in a weight ratio of sulfuric acid to hydrogen peroxide of about 2:1. Of course, other commercially available metal etchants are also suitable for use in the present invention.

Then, a portion of the exposed substrate 310 is removed by, for example, Deep Reactive Ion Etching (DRIE) to form a first recess 312 as shown in FIG. In the above embodiment, the angle θ between the sidewall of the microstructure 330 and the upper surface of the substrate 310 may be from about 85 degrees to about 95 degrees. In addition, the sidewalls of the microstructures 330 and the sidewalls of the circuit layer 320 are flat. Therefore, it helps to improve the performance and quality stability of the micro-electromechanical device.

In step 230, the upper cover 370 is disposed above the circuit layer 320 to cover the microstructures 330 and the first recesses 312, as shown in FIG. The upper cover 370 prevents particles or contaminants in the environment from falling into the first recess 312 during subsequent processes, resulting in failure of the final micro-electromechanical device. In addition, the upper cover 370 can protect the finally formed microelectromechanical device from mechanical impact from the outside. The upper cover 370 can be made, for example, of a glass or a ruthenium substrate.

In an embodiment, the upper cover 370 may optionally include a positioning mark 374 for providing the positioning or alignment required for subsequent processes. The present embodiment can be realized by the following steps. First, the upper cover 370 is provided, and a set of positioning grooves 371 are formed on the surface 370a of the upper cover 370 as shown in Fig. 5A. In one embodiment, the positioning groove 371 is formed by laser cutting, the positioning groove 371 does not penetrate the upper cover 370, and the positioning groove 371 has a depth of about 5 μm to about 300 μm. Subsequently, an adhesive layer 372 is formed on the surface 370a as shown in Fig. 5B. The order in which the adhesive layer 372 and the positioning groove 371 are formed is not limited. For example, the adhesive layer 372 may be formed first, and then the positioning groove 371 may be formed. Next, the upper cover 370 on which the positioning groove 371 and the adhesive layer 372 are formed is adhered to the circuit layer 320 as shown in FIG. 5C. At this time, the surface 370a on which the positioning groove 371 and the adhesive layer 372 are formed is located on the side close to the circuit layer 320. Then, a portion of the upper cover 370 is removed from the opposite side surface 370b of the surface 370a to expose the positioning groove 371 to form the positioning mark 374. For example, the positioning groove 371 can be exposed by grinding the surface 370b of the upper cover 370.

In the above embodiment in which the positioning mark 374 is formed, the formed positioning groove 371 can also directly penetrate the upper cover 370, so that the image positioning device can observe the outline of the positioning groove 371 from one side of the surface 370b. In other words, the positioning groove 371 is a positioning mark.

In step 240, a portion of the substrate under the first recess 312 and the microstructure 330 is removed from one side of the lower surface 310b of the substrate 310 to form a second recess 314 for the second recess. A base residue 316 is formed between the bottom 314b of the groove 314 and the bottom 312b of the first groove 312. In other words, in this step, the formed second groove 314 does not communicate with the first groove 312. At this time, the microstructures 330 are connected to the surrounding circuit layer 320 by the substrate residual portion 316.

In one embodiment, the substrate 310 is a wafer that can be first subjected to a polishing process to reduce the thickness of the substrate 310, as shown in FIG. 6A. Generally, the thickness of the wafer is about 720 μm, and the thickness can be reduced to about 200 μm by a grinding process. Any conventional suitable grinding process can be applied to the present invention.

Then, a patterned photoresist layer 318 is formed on the grounded lower surface 310b as shown in FIG. 6B. The photoresist layer 318 exposes the substrate 310 under the first recess 312 and the microstructures 330. In this step, the area of the substrate portion exposing the photoresist layer 318 may be larger than the bottom areas of the first recess 312 and the microstructures 330. In one embodiment, the patterned photoresist layer 318 is positioned by the alignment marks 374 of the upper cover 370, so that the relative position of the formed photoresist pattern to the substrate 310 can be more precisely controlled.

Next, the exposed portion of the substrate 310 is removed by deep reactive ion etching to form the second recess 314 and the substrate residue 316 as shown in FIG. 6C. In one embodiment, the second recess 314 formed by the deep reactive ion etching has a depth of from about 10 μm to about 150 μm. In another embodiment, the substrate residue 316 has a thickness H of from about 10 μm to about 150 μm. After the second recess 314 and the substrate residual portion 316 are formed, the photoresist layer 318 is removed to form the structure shown in FIG.

The above-described embodiment in which the second recess 314 and the substrate residual portion 316 are formed is merely illustrative, and the present invention is not limited thereto. Other process steps or methods which may have the same or similar structure may also be suitable for use in the present invention. For example, the above polishing process may be omitted. It is possible that the photoresist layer 318 described above is replaced with, for example, a hard mask or a suitable mask. The above deep reactive ion etching method may be replaced by other etching methods.

The step of forming the second recess 314 and the substrate residue 316 described above is highly beneficial for maintaining or maintaining the sidewall profile of the microstructure 330. For example, if the second recess 314 is formed by etching by deep reactive ion etching, the heat is accumulated near the etching site due to the characteristics of the deep reactive ion etching method, which leads to a deep reaction. The ion etch is transformed into a near isotropic etch in this localized region. Therefore, a good etching profile cannot be obtained. Therefore, if the second recess 314 is in communication with the first recess 312 during this etching step, the sidewall profile of the microstructure 330 will be poor. Therefore, according to the embodiment of the present invention, in the step of forming the second recess 314, the substrate residual portion 316 is formed between the bottom portion 314b of the second recess 314 and the bottom portion 312b of the first recess 312, thereby avoiding the above problem.

In addition, when the second recess 314 is formed, the first recess 312 is sealed by the upper cover 370 and the adhesive layer 372 to be in a sealed state. Therefore, when the step of removing the photoresist layer 318 is performed, the stripper used does not penetrate into the first recess 312. On the other hand, if the second recess 314 is in communication with the first recess 312 when the second recess 314 is formed, the photoresist will inevitably enter the first recess 312 when the photoresist layer 318 is removed. However, the voids or widths within the first recess 312 are typically small, such as from about 2 μm to about 30 μm. Therefore, the above steps of forming the second recess 314 and the substrate residual portion 316 also contribute to improvement in product reliability.

In step 250, the substrate residue 316 is removed to release the microstructures 330, as shown in FIG. As used herein, "releasing microstructure" means causing a microelectromechanical device to produce a structure or component that is relatively movable. Specifically, after the substrate residue 316 is removed, the microstructures 330 can be displaced relative to the circuit layer 320 at its periphery. In detail, after the substrate remaining portion 316 is removed, the second groove 314 communicates with the first groove to form a through space 142 as shown in FIG. At this time, the microstructures 330 are "suspended" in the through space 142 by the elastic support members 114 shown in FIG. In one embodiment, the substrate residue 316 can be removed by a full-surface etching of the lower surface 310b of the substrate 310. By "whole-sided etching", it is meant that all of the lower surface of the substrate is etched instead of etching a specific portion of the substrate. Therefore, when performing a full-surface etching, no photoresist is used. For example, full-surface etching can be performed by RIE, DRIE, or other suitable means.

After step 250, the following steps may be performed non-essentially.

In step 260, the cover 380 is disposed under the substrate 310 such that the lower cover 380 and the upper cover 370 form a closed space C surrounding the microstructure 330, as shown in FIG. The microstructures 330 can be moved in the enclosed space C to cause the microelectromechanical device to produce a predetermined function. The upper cover 370 and the lower cover 380 serve to protect the microstructures 330 while preventing contaminants from entering the enclosed space C. The material of the lower cover 380 may be the same as or different from the upper cover 370. In an embodiment, the lower cover 380 can be fixed under the substrate 310 by an adhesive layer 382.

In step 270, a portion of the upper cover 370 is removed to expose a portion of the protective layer 326, as shown in FIG. The exposed portion of the protective layer 326 overlaps the connection pads 324. In one embodiment, as shown in FIG. 9A, a patterned photoresist layer 376 is formed on the outer surface of the upper cover 370, and then the exposed upper cover is removed by, for example, deep reactive ion etching. 370, while the underlying protective layer 326 is exposed. Alternatively, this step can be accomplished by laser cutting or mechanical cutting.

In step 280, portions of the exposed protective layer 326 are removed to expose the underlying connection pads 324, and then the photoresist layer 376 is removed, as shown in FIG. For example, the exposed portion of the protective layer 326 can be removed by the RIE process, and the connection pads 324 under the protective layer 326 can be exposed. The exposed connection pads 324 can serve as a connection point for the microelectromechanical device to external circuitry. The photoresist layer 376 is then removed using a photoresist removal process.

According to another aspect of the present invention, a microelectromechanical device is provided as shown in Figures 1 and 10. The microelectromechanical device 300 includes a substrate 310, a circuit layer 320, a through space 142, a movable microstructure 330, and an elastic support 114 (shown in FIG. 1). Circuit layer 320 is formed on the surface of substrate 310, which includes an active component 322. The through space 142 extends through the circuit layer 320 and the substrate 310 to form an upper opening 391 and a lower opening 392 in the circuit layer 320 and the substrate 310, respectively. The cross-sectional area at the entrance of the lower opening is larger than the cross-sectional area at the entrance of the upper opening. The microstructures 330 are housed in the through space 142. A capacitor structure can be formed between the microstructures 330 and the circuit layer 320. The microstructures 330 can be electrically connected to the active components 322 via a capacitive structure. The resilient support 114 physically connects the microstructure 330 to the circuit layer 320.

In one embodiment, the microstructures 330 include at least one first electrode 116 (shown in FIG. 1 ), and the circuit layer 320 includes at least one second electrode 144 . The first electrode 116 and the second electrode 144 extend into the through space 142 to form the above-described capacitor structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100. . . MEMS acceleration detector

110. . . microstructure

112. . . Central department

114. . . Elastic support

116. . . First electrode

120. . . Semiconductor circuit

130. . . Connection pad

140. . . Substrate

142. . . Through space

144. . . Second electrode

200. . . method

210, 220, 230, 240, 250, 260, 270, 280. . . step

300. . . Microelectromechanical device

310. . . Substrate

310a. . . Upper surface

310b. . . lower surface

312. . . First groove

312b. . . bottom

314. . . Second groove

314b. . . bottom

316. . . Residual substrate

318. . . Photoresist layer

320. . . Circuit layer

322. . . Active component

324. . . Connection pad

326. . . The protective layer

330. . . microstructure

340. . . Feature structure

342. . . Dielectric structure

344, 344a, 344b. . . Metal structure

350. . . Photoresist layer

352. . . Opening

370. . . Upper cover

370a, 370b. . . surface

372. . . Adhesive layer

374. . . Positioning mark

376. . . Photoresist layer

380. . . Lower cover

382. . . Adhesive layer

391. . . Upper opening

392. . . Lower opening

A. . . region

B. . . Opening

C. . . Closed space

d. . . distance

H. . . thickness

θ. . . Angle

1 is a top view of a microelectromechanical device according to an embodiment of the present invention.

2 is a flow chart showing a method of manufacturing a microelectromechanical device according to an embodiment of the present invention.

3A to 10 are schematic cross-sectional views showing respective process stages in the method of fabricating a microelectromechanical device of the present invention.

200. . . method

210, 220, 230, 240, 250, 260, 270, 280. . . step

Claims (11)

A method of fabricating a microelectromechanical device, comprising: (a) forming a circuit layer and a microstructure on an upper surface of a substrate, wherein the circuit layer comprises an active component, and the microstructure is electrically connected to the active component; (b) forming a first recess penetrating the circuit layer and deep into the substrate such that a bottom of the first recess is lower than an upper surface of the substrate, wherein the first recess surrounds the periphery of the microstructure a portion (c) configured with an upper cover over the circuit layer to cover the microstructure and the first recess; (d) from a lower surface side of the substrate, removed in the first recess and the micro a portion of the substrate under the structure to form a second recess such that a bottom portion of the second recess forms a substrate residue with the bottom portion of the first recess; and (e) removing the substrate A residual portion of the substrate to release the microstructure. The method of claim 1, further comprising after the step (e); disposing the cover body under the substrate, so that the lower cover body and the upper cover body form a closed space surrounding the microstructure. The method of claim 1, wherein the circuit layer of the step (a) further comprises a connection pad and a protective layer, wherein the connection pad is electrically connected to the active component, and the protective layer covers the connection pad. The method of claim 3, after the step (e), further comprising: removing a portion of the upper cover to expose a portion of the protective layer, and the exposed portion is overlapped with the connection pad; and removing the protection The exposed portion of the layer exposes the connection pad. The method of claim 1, wherein the active component of step (a) is a complementary metal oxide semiconductor device or a bipolar complementary metal oxide semiconductor device. The method of claim 1, wherein a vertical distance between a bottom of the first groove of the step (b) and the upper surface is from about 5 μm to about 100 μm. The method of claim 1, wherein the upper cover of step (c) comprises a positioning mark. The method of claim 1, wherein the step (d) comprises: grinding a lower surface of the substrate; forming a patterned photoresist layer on the polished surface of the substrate; and moving by deep reactive ion etching A portion of the substrate is exposed to form the second recess. The method of claim 1, wherein the substrate residue of the step (d) has a thickness of from about 10 μm to about 150 μm. The method of claim 1, wherein the step (e) comprises: etching the lower surface of the substrate in a planar manner to remove the substrate residue. A method of fabricating a microelectromechanical device, comprising: forming a circuit layer and a microstructure on an upper surface of a substrate, the circuit layer including a feature structure surrounding a portion of a periphery of the microstructure, and the feature structure a circuit layer, wherein the feature structure comprises: a dielectric structure extending through the circuit layer; and a metal structure extending through the circuit layer and surrounding the dielectric structure; removing the feature structure to expose the upper surface, wherein removing The feature includes sequentially removing the dielectric structure by dry etching and removing the metal structure by wet etching; removing a portion of the exposed substrate to form a first recess, wherein the first recess Having a bottom portion lower than the upper surface; an upper cover body disposed above the circuit layer to cover the microstructure and the first recess; and a lower surface side of the substrate, removed in the first recess and the a portion of the substrate under the microstructure to form a second recess such that a bottom portion of the second recess forms a substrate residue with the bottom of the first recess; and the base is removed Residue, Release of the microstructure.