200926310 九、發明說明： 【發明所屬之技術領域】 本發明係提供—種料 禋铽機電結構製造方法，特別是指一種 新的密封腔微型結 棲全 灰乂方法’其能有效避免不當侵蝕，而B 曝絡機率低，更能與一 且 本。 奴知體電路封裝整合、減少最後封裝成 ❹ ❹ 【先前技術】 現今半導體微機電系統包含各種不_半導體微 構，例如：不可動的探針、流道、孔穴結構，或是―: 彈簧、連桿、齒於f圆雕、$ —」動的 _ 、 时（J歧運動或是撓性形變）等結構。 將上述不同的結構和相關的積體電路相互整合，即可 各種不同的半導體廡爾上 夜 勒。故如域㈣造方法提昇微機械結構 各種不_功能，是桃轉體微機電緖_難標，也是 未來進步研究晶片時的嚴峻挑戰；若能研發改進習知的技 術，未來的發展性實無法預估。 目前製作微機電感·及致動m經常需要在石夕基底 上製作懸浮式結構。前述製程必須_ 了先進的半導體技術， 例如.利用乾侧、濕綱、氣體爛來進行犧牲層 (saCHfieial layer)去除’並且在元仙部形趟浮的微機 6 200926310 黾系統CMEMS : Micro-Electro-Mechanical Systems)，利用此 微機電系統可以產生高靈敏度動作，並且應用在廣泛的產品設 計上。 習用技術如美國專利6，458，615B1，前述案件是於一石夕 基底上表面形成至少一内具微機電結構的絕緣層，並且接著從 上表面逐層蝕刻，並且經過微機電結構側緣後，等向性200926310 IX. Description of the invention: [Technical field to which the invention pertains] The present invention provides a method for manufacturing an electromechanical structure of a seed material, and in particular to a new method for micro-habiting all-ash sputum in a sealed chamber, which can effectively prevent undue erosion. The B exposure rate is low, and it can be more consistent with one. Numerous body circuit package integration, reducing the final package into ❹ ❹ [Prior Art] Today's semiconductor MEMS include a variety of semiconductor micro-structures, such as: non-movable probes, runners, hole structures, or -: springs, The connecting rod, the tooth is in the shape of the f-carving, the _, the movement (the J-shaped motion or the flexible deformation) of the $-" movement. By integrating the above different structures and related integrated circuits, a variety of different semiconductors can be used. Therefore, as the domain (four) method to improve the micro-mechanical structure of various non-functions, is the peach-turn micro-mechanical _ difficult to mark, but also a serious challenge in the future research and development of wafers; if the development of improved technology, future development Unpredictable. At present, it is often necessary to make a floating structure on the Shishi substrate by making the microcomputer inductance and the actuation m. The above process must be advanced semiconductor technology, for example, using the dry side, the wet class, the gas to kill the sacrificial layer (saCHfieial layer) to remove 'and the floating plane in the Yuanxian part of the computer 6 200926310 黾 system CMEMS : Micro-Electro -Mechanical Systems), which utilizes this MEMS system to produce highly sensitive motions and is used in a wide range of product designs. Conventional technology, such as U.S. Patent No. 6,458,615 B1, the disclosure of which is to form at least one insulating layer having a microelectromechanical structure on the upper surface of a substrate, and then etched layer by layer from the upper surface and after passing through the side edges of the microelectromechanical structure. Isotropic
CisotTQPicetching)矽基底乾蝕刻，達成微機電結構之懸浮； 前述第一種習用技術雖然能夠製作懸浮微機電結構，但是 卻會產生下列幾項缺陷： 其—，其採用非等向性化學儀刻（anis〇tr〇pic d叮 —1Cal e她ing)方式，利·學反應的方式移除絕緣層， 但疋由於經過微機電結構側緣後，仍要再進行等向性化學姓刻 將石夕基底大量侧，故此種技術會發生嚴細賴現象(她『 rnt、： cut)； 微機電結構受 t，繼物輸巾，觸辑—開始就曝 路在衣程之中’長時間多層製程之後，經常會有： 到污染、損傷，造成良率過低； =、’此㈣雜術在_作社成之後，該微機電結構 广:ΓΓ運作，但疋部又要以特殊機具將_機電結構表面封 衣阻、％空氣中的微粒，但是由於該微機電結構必須確保懸浮狀 7 200926310 200926310 整合 雜且高成本，且無法與一般積體電路Ic的封裝 别賴術的發展十分迅速，為了改進其諸多問題，美國專 ^ ^ 812 〇 :道雜層由上、下方分別包覆微機電懸浮部 ^ 繼—細輪軸微機電懸浮 =後^於鶴構上抓，並且㈣孔來蹄蓋覆 摘-逼犧牲層飯刻，並在該蓋覆結構外又 層而形成-密封腔，達成微機電驗部位 二= 術雖然能大幅降低微機Hi H、，子此種技 耳顺機包外路機率，但是，其問題在於： 該二道犧牲層的製作方式必須由上 懸浮部位，二層 、 方”別L錢機電 Ο 且搭配微機麵外兩道光罩製作十分費卫費時，而 顺逸予部位的對準技術須十分精準， 用技術仍然過於麻煩複雜。 之習 — 〜 前述密封腔微機電箩你 缺HfeLi 、 所务生的問題在習用技術内h 也是目前半導體微型結 二 不斷哥得突破的隨點。 衣業界 有鑑於斯，本案菸 微機電產品設計與半詳思細索，並積多年從事各種 •'研九生產的經驗，開發出—種能有欵 8 200926310 避免u機电結構曝露、提昇電路整合性、減少無效過渡結構及 減少封I成本的密封腔微型結構製造方法。 【發明内容】 本發明之首要目的在於提供一種密封腔微型結構製造方 法’可降低微機電結渺卜露解，且減少封裝成本。 本發明為達成前述目的，其係於一矽基底上表面形成至少 Ο 區域内具彳政機電結構的絕緣層，該區域包含具備間隔區的至 )微機电結構，經過蝕刻後以犧牲層充填於前述間隔區與表 面’亚在犧牲層上相應該傳導結構製作穿孔後，在前述穿孔内 及表面沈積—罩蓋層，藉此，產生降碰機電結構外露機率的 效果； 將犧牲層_去除後，翻料蓋層的孔隙將微機電結構 下方的砍基底爛，達成微機電結構之懸浮，最後再以一密封 ❹ 料覆於該罩蓋層外’且將罩蓋層的孔騎塞密封； 藉此，不但可以有效避免微機電結構曝露，更能直接利用 石夕基底的侧讓微機電結構達成懸浮，進而減少以往製作多道 犧牲層的成本與麻須手續。 本4x月目的之—在於提供一種密封腔微型結構製造方 法，其充份運用罩蓋層來形成功能元件。 本發明為達成前述目的，此密封腔微型結構製造方法係於 200926310 Ο :錄底上麵㈣1物彳物結翻絕緣層，該 Ζ包含彼此之間具備間隔區的至少—微機電結構及至少一 傳^结構，經舰刻後以犧牲層充填於前述間隔區盘傳導结構 表面，並在犧牲層上相應該傳導結構製作穿錢，在前述穿孔 =及表面沈積-罩蓋層，該罩為導電材料製作所成，且該 罩盍層電性通連於該傳導結構，在將犧牲層綱去除、石夕基底 餘刻後’最後再以-㈣層罩覆於該罩蓋層外； 、藉此，能直接利用罩蓋層與微機電結構的電導通整合設計 為電路之—部份’有效增加該罩蓋層在製程後的魏，同樣亦 可減少封裝成本。 〜重要的是，由於絕緣層上表面的阻絕層可以直接作為微機 構餘刻過程的_保護，翻财基底舰娜微機電結 ，達成懸浮，進喊少以往製作乡道齡層的成本與麻煩手 只本發明確能夠突破以往技術的細，開創出前所未見的技 &值得一提的是，本發明之蝕刻技術可各自依需求選擇採用 見的離子钱刻（Reactive Ion Etching，以下簡稱rie)或龄 、深'舌性離子蝕刻（Deep Reactive Ion Etching,以下簡 _RIE); 10 200926310 ’乾柄縣絲子侧謝歧近 z 的非等向性廣## 相晏文到重規 保護層’來ΓΓΓΓ 臟體綱的過財所形成的 禾防止側壁被蝕刻，以達到預設之高深 刻的結構形狀’不會_晶格面的影響且沒有 此麵 性^此可以_出任意形狀的孔洞或凸塊，·科 延遲⑽1⑹的特性，還可以在基材表面製造多重高度/CisotTQPicetching) dry etching of the substrate to achieve suspension of the microelectromechanical structure; although the first conventional technology described above can produce a suspended microelectromechanical structure, it has the following defects: - it uses anisotropic chemical etching ( Anis〇tr〇pic d叮—1Cal e she ing) way, the way of learning and removing the insulation layer, but after passing through the side edge of the microelectromechanical structure, it is still necessary to carry out the isotropic chemical There are a large number of sides of the substrate, so this technology will occur closely (she rnt,: cut); micro-electromechanical structure is subject to t, the infusion of the towel, the touch-up - began to be exposed in the process of 'long-term multi-layer process, Often there will be: pollution, damage, resulting in low yield; =, 'this (four) after the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Surface sealing resistance, % airborne particles, but because the micro-electromechanical structure must ensure the suspension 7 200926310 200926310 integration and high cost, and can not be developed with the general integrated circuit Ic package development very quickly, In order to improve its many problems, the United States specializes in ^ ^ 812 〇: the dope layer is covered by the upper and lower parts of the micro-electromechanical suspension part ^ followed by the fine wheel axis micro-electromechanical suspension = after ^ on the crane structure, and (four) hole hoof cover Picking-forced sacrificial layer rice carving, and forming a sealed cavity outside the covering structure to achieve a micro-electromechanical inspection site 2 = although the computer can greatly reduce the Hi H, the sub-skills of the technology However, the problem lies in: The production method of the two sacrificial layers must be made up of the upper suspension part, the second layer, the square, and the two masks made up of the micro-machine surface are very time-consuming and time-consuming. The alignment technology must be very precise, and the technology is still too cumbersome and complicated. The habits - ~ The aforementioned sealed cavity micro-electromechanical 箩 you lack HfeLi, the problem of the problem is in the conventional technology h is also the current semiconductor micro-junction In the clothing industry, in view of this, the design of the smoke micro-electromechanical products in this case is half-detailed, and has accumulated many years of experience in the production of various researches, and has developed a kind of energy. 8 200926310 Avoiding the electromechanical structure of u SUMMARY OF THE INVENTION The primary object of the present invention is to provide a method for manufacturing a sealed cavity microstructure, which can reduce the microelectromechanical junction. The invention aims to achieve the foregoing object, which is to form an insulating layer having a chemistries and electromechanical structures in at least a region of the upper surface of a substrate, the region comprising a microelectromechanical structure having a spacer. After being etched, the sacrificial layer is filled in the spacer region and the surface is formed on the sacrificial layer, and then the conductive structure is formed into a perforation, and a cap layer is deposited in the through hole and on the surface, thereby generating an exposure probability of the buckling electromechanical structure. Effect; after the sacrificial layer is removed, the pores of the flip cover layer rot the chopped substrate under the microelectromechanical structure to achieve suspension of the microelectromechanical structure, and finally cover the cover layer with a sealing material 'and the cover The hole of the cap layer is sealed by the plug; thereby, the MEMS structure can be effectively prevented from being exposed, and the side of the Shi Xi base can be directly used to make the microcomputer Reached suspension structure, thereby reducing the production cost of the conventional multi-channel sacrificial layer and the procedures to be hemp. The purpose of this 4x month is to provide a method of manufacturing a sealed cavity microstructure that fully utilizes a cap layer to form functional elements. In order to achieve the foregoing object, the method for manufacturing a sealed cavity microstructure is based on 200926310 Ο: (4) a material smashing insulation layer, the Ζ comprising at least a microelectromechanical structure having a spacer between each other and at least one Passing the structure, after the ship is engraved, filling the surface of the disk-conducting structure with the sacrificial layer, and making the money on the sacrificial layer corresponding to the conductive structure, in the above-mentioned perforation= and surface deposition-cover layer, the cover is electrically conductive The material is fabricated, and the cover layer is electrically connected to the conductive structure, and after the sacrificial layer is removed and the stone base is left, the layer is finally covered by the layer of (4); The direct integration of the electrical conduction between the cap layer and the MEMS structure as part of the circuit can effectively increase the cover layer after the process, and also reduce the packaging cost. ~ The important thing is that because the barrier layer on the upper surface of the insulating layer can be directly used as the _ protection of the micro-mechanical process, the flip-flop base ship Na-micro-electromechanical knot, achieves suspension, and shouts less cost and trouble in making the township age layer. Only the invention can break through the fineness of the prior art, and create a technique that has never been seen before. It is worth mentioning that the etching technique of the present invention can be selected according to the needs of the Reic Ion Etching (hereinafter referred to as Reactive Ion Etching). Rie) or age, deep 'tonic ion etching (Deep Reactive Ion Etching, _ _ RIE); 10 200926310 'dry handle county silk side Xie Qi near z non-isotropic wide ## 相晏文至重规保护The layer 'to ΓΓΓΓ 脏 脏 脏 的 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止 防止Holes or bumps, the characteristics of the delay (10) 1 (6), can also create multiple heights on the surface of the substrate /
此外，前述該罩蓋層可以依需求採用由I呂、銻、聲、鋼 鈦、鶴及金組成的物質群中選擇的一種導電材料，此導體以 蓋層細输物y，且可—併完朗裝㈣。 有關本案發明為達成上述目的、所採用之高度技術思想、 手段’兹卿—較封實關並齡㈣如後，相作In addition, the cover layer may be a conductive material selected from the group consisting of Ilu, 锑, 声, steel, titanium, crane, and gold, and the conductor is a cover layer of the fine material y, and may Finished (4). The high-tech ideas and means used in the invention of the present invention to achieve the above objectives are as follows:
本案發明之目的、特徵及其他優點，當可由之得-深入而旦體 之瞭解。 【實施方式】 相參閱第1至11圖之實關，本發明密封腔微型結構製造 方法之詳細說明如下； 士第1圖所不’首先於一石夕基底1〇上表面形成内具區域幻 的絕緣層20 ’域21包含數組層疊之微機電結構211及環繞 11 200926310 其週側的至少一傳導結構212，前述各組微機電結構211之間、 各微機電結構211與該傳導結構212間皆具備間隔區213，該區 域21被絕緣層20包覆； 如第2、3圖所示，將絕緣層2〇進行離子蝕刻（RIE)，該絕 緣層20經過RIE钱刻後，該區域21之微機電結構211及環繞其週 侧的傳導結構212露出，且前述各組微機電結構211之間、各微 機電結構211與該傳導結構212間的間隔區213也被姓刻成中空 ❹ 狀態； 如第4、5圖所示’接著在絕緣層20上方披覆一層犧牲層 30，該犧牲層30充填於前述間隔區213，且該犧牲層3〇覆蓋該 區域21之微機電結構211及傳導結構212的表面； 如第6、7圖所示，在該犧牲層30上製作多數穿孔31，且 前述穿孔31排列製作於該傳導結構212之上方，而穿孔31到 達該區域21之傳導結構212表面，且排列成圍繞該區域21之 ❺ 微機電結構211; 如第8圖所示，在前述犧牲層30表面上沈積一罩蓋層4〇, 且罩蓋層40的覆蓋範圍含蓋多數穿孔31，並且罩蓋層4〇充填 進入前述穿孔31内； 如第9圖所示，接著再將犧牲層完全蝕刻去除，位於前述 絕緣層20之間隔區213内與罩蓋層40下方的犧牲層3〇則透 過罩蓋層40未充填的空間達成完全飯刻去除的效果； 12 200926310 如弟10圖所示’再利用罩蓋層40的孔隙（去除犧牲層後 所生之孔隙）、中空的絕緣層20之間隔區213，可以將區域21 之微機電結構211下方的矽基底10蝕刻出一空間丨丨，利用此 空間11達成微機電結構211之懸浮； 隶後，如弟11圖所不，袁後再沈積一密封層50在★亥罩罢 層40外，且將罩蓋層40的孔隙完全密封。The objects, features, and other advantages of the present invention can be obtained from an in-depth understanding. [Embodiment] Referring to the actual figures of Figures 1 to 11, the detailed description of the manufacturing method of the sealed cavity microstructure of the present invention is as follows; the first figure of Figure 1 does not first form an area with an illusion on the upper surface of a stone substrate. The insulating layer 20' field 21 includes an array of stacked microelectromechanical structures 211 and at least one conductive structure 212 surrounding the periphery of the 11 200926310, between the respective sets of microelectromechanical structures 211, between the microelectromechanical structures 211 and the conductive structures 212. A spacer 213 is provided, and the region 21 is covered by the insulating layer 20; as shown in FIGS. 2 and 3, the insulating layer 2 is ion-etched (RIE), and the insulating layer 20 is etched by RIE, and the region 21 is The microelectromechanical structure 211 and the conductive structure 212 around the circumference thereof are exposed, and the spacers 213 between the microelectromechanical structures 211 and the microelectromechanical structures 211 and the conductive structures 212 are also engraved into a hollow state; As shown in FIGS. 4 and 5, a sacrificial layer 30 is then overlaid over the insulating layer 20, the sacrificial layer 30 is filled in the spacer 213, and the sacrificial layer 3 covers the microelectromechanical structure 211 of the region 21 and conducts The surface of structure 212; As shown in FIGS. 6 and 7, a plurality of perforations 31 are formed in the sacrificial layer 30, and the perforations 31 are arranged above the conductive structure 212, and the through holes 31 reach the surface of the conductive structure 212 of the region 21, and are arranged to surround the Between the regions 21, the microelectromechanical structure 211; as shown in Fig. 8, a cap layer 4 is deposited on the surface of the sacrificial layer 30, and the coverage of the cap layer 40 covers a plurality of perforations 31, and the cap layer 4 The crucible is filled into the through hole 31; as shown in FIG. 9, the sacrificial layer is completely etched away, and the sacrificial layer 3 located in the space 213 of the insulating layer 20 and under the cap layer 40 passes through the cap layer. 40 unfilled space achieves the effect of complete meal removal; 12 200926310 As shown in Figure 10, 'reuse the pores of the cap layer 40 (the pores created after the sacrificial layer is removed), the space 213 of the hollow insulating layer 20 The germanium substrate 10 under the microelectromechanical structure 211 of the region 21 can be etched into a space 丨丨, and the space 11 can be used to achieve the suspension of the microelectromechanical structure 211; afterwards, if the image is not shown in the middle 11, the seal is deposited after the Yuan Layer 50 is outside the layer of 40 The porosity of the cover layer 40 is completely sealed.
藉前述密封腔微型結構製造方法；其產生的效果在於： 1.其降低微機電結構曝露、降低損傷機率，由於本發明犧 牲層30¼刻去除及區域21之微機電結構211懸浮爛時，皆 文到罩蓋層40的保護，可以保持良好、避免曝露，有效避免 區域21之微機電結構211曝露在外、降低受到損傷的機率。 + 2.因絕緣層20上的罩蓋層4〇可以接作為密封層5〇封 裝的保護，且該傳導結構212的暴露表面可供打金線導通電路 7，故本發明能夠直接去除以往複雜、高成本的後製封裝作 3.最重要的是， 結構211達成懸浮， 煩手續。 本發明再彻魏底10 __微機電 進而減少以往製作多道犧牲層的成本與麻 本發明另一關鍵第4 功效在於：由於該犧牲層30 上的穿 13 2 卿 26310 孔31到達該區域2 層40採用由鋁、鎳哿導=構212表面，若是本發明之罩蓋 擇的一種導電材料時，觸射選 傳導結構妣導通，並且可罩;f4G可以與該區域幻之 做為雜谢了錢料㈣t)通相—部份（例如： 為二::接利用罩蓋層4〇與區域21的電導通整合設計 Ο =罩蓋層4Q在製程後的持續運作 功月匕，同樣亦可減少封裝成本。 本發明另—實施例，請參閱第12至20圖之實施例，以下 實_皆直接說明該罩蓋層採用導電材料的實施方式，但僅為 重要只把之^用模式’並非限定本實施之技術範圍；本發明密 封腔被型結構製造方法之詳細說明如下； 如第12圖所示，首先於一矽基底1〇上表面沈積内具區域21 〇 的絕緣層20，該區域21包含數組層疊之微機電結構211及環繞 其週側的至少一傳導結構212，前述各組微機電結構2H之間、 各微機電結構211與該傳導結構212間皆具備間隔區213，該區 域21被絕緣層20包覆； 如第13圖所示，將絕緣層20進行離子蝕刻（RIE)，該絕緣 層20經過RIE蝕刻後，該區域21之微機電結構2Π及環繞其週側 的傳導結構212露出，且前述各組微機電結構211之間、各微機 14 200926310 * 電結構211與该傳導結構212間的間隔區213也被姓刻成中介狀The foregoing sealing cavity micro-structure manufacturing method has the following effects: 1. It reduces the exposure of the micro-electromechanical structure and reduces the probability of damage, because the sacrificial layer 301⁄4 of the present invention is removed and the micro-electromechanical structure 211 of the region 21 is suspended, The protection to the cap layer 40 can be kept good and avoid exposure, and the microelectromechanical structure 211 of the region 21 is effectively prevented from being exposed and the probability of being damaged is reduced. + 2. Since the cap layer 4 on the insulating layer 20 can be protected as a sealing layer 5 〇 package, and the exposed surface of the conductive structure 212 can be used for the gold wire conducting circuit 7, the present invention can directly remove the complicated The high-cost post-production package is 3. The most important thing is that the structure 211 is suspended and troublesome. The invention further reduces the cost of fabricating multiple sacrificial layers in the past and another key fourth effect of the invention is that the hole 13 2 through the sacrificial layer 30 reaches the region The 2 layer 40 is made of aluminum and nickel, and the surface of the structure is 212. If it is a conductive material selected by the cover of the present invention, the contact-selective conductive structure is conductive and can be covered; the f4G can be mixed with the region. Thanks for the money (4) t) through the phase - part (for example: two:: use the cover layer 4 〇 and the electrical conductivity of the area 21 integrated design Ο = cover layer 4Q after the process of continuous operation, the same The invention can also reduce the cost of the package. For the other embodiments, please refer to the embodiments of FIGS. 12 to 20, and the following embodiments directly illustrate the implementation of the cover layer using a conductive material, but only for the important ones. The mode 'is not limited to the technical scope of the present embodiment; the detailed description of the method for manufacturing the sealed cavity by the structure of the present invention is as follows; as shown in FIG. 12, the insulating layer 20 having the region 21 〇 is first deposited on the upper surface of a substrate 1 , the area 21 contains the array of micro The electrical structure 211 and the at least one conductive structure 212 surrounding the circumferential side thereof, and the spacers 213 are disposed between the microelectromechanical structures 2H and the microelectromechanical structures 211 and the conductive structures 212. The regions 21 are covered by the insulating layer 20. As shown in FIG. 13, the insulating layer 20 is ion-etched (RIE), and after the RIE etching of the insulating layer 20, the microelectromechanical structure 2 of the region 21 and the conductive structure 212 surrounding the peripheral side thereof are exposed, and the foregoing Between each group of microelectromechanical structures 211, each microcomputer 14 200926310 * The spacing 213 between the electrical structure 211 and the conductive structure 212 is also mediated by the surname
At . 悲， 如第14圖所示，接著利用深活性離子蝕刻（j^IE)延著哼 絕緣層20之間隔區213進行石夕基底1〇的餘刻，並且钱刻出預役 深度的中空蝕槽12 ’各中空蝕槽12的深度一致； 如第15圖所示，在絕緣層20上方披覆一層犧牲層3〇，該犧 牲層30充填於前述間隔區213及中空蝕槽12内，且該犧牲層3〇 Ο 覆蓋該區域21之微機電結構2 Π及傳導結構212的表面； 如第16圖所示，於石夕基底10之下背面進行钱刻，且於石夕 基底10定向形成通連該中空蝕槽12的空間101; 如第17圖所示，在該犧牲層3〇上製作多數穿孔31，且前 述穿孔31排列製作於該傳導結構212之上方’而穿孔31到達 邊區域21之傳導結構212表面，且排列圍繞該區域21之微機 電結構211 ; © 如第18圖所示，在前述犧牲層30表面上沈積一罩蓋層 40，該罩蓋層40採用導電材料，且罩蓋層4〇的覆蓋範圍含蓋 多數穿孔31’並且罩蓋層4〇充填進人前述穿孔&内後接觸該 傳導結構212表面； 如第19騎示，接著再將犧牲層完全侧去除，位於前 述絕緣層20之間隔區213内的犧牲層3〇、罩蓋層4〇下方的犧 牲層30及縣底1〇之中空㈣12 _犧牲層％，皆透過罩 15 200926310 ， 蓋層40未充填的空間達成完全餘刻去除的效果，並且中空I虫 槽12與該矽基底10之空間101相連通，而該微機電結構211 一側尚留有預設厚度的懸空矽基底10，可供使用者需求調控微 機電結構211的物理特性； 如第20圖所示，最後再沈積一密封層50在該罩蓋層40 外，且將罩蓋層40的孔隙完全密封，此時，利用罩蓋層40的 孔隙、中空的絕緣層2〇之間隔區213 '矽基底1〇之中空蝕槽 © 12與矽基底10下方的空間1〇1，可以達成微機電結構211之 懸浮。 藉前述實施例提供的一種密封腔微型結構製造方法；其產 生的效果在於： 1. 其降低微機電結構曝露 '降低損傷機率。 2. 去除以往複雜、高成本的後製封裝作業。 3·減少以往製作多道犧牲層的成本與麻煩手續，且該傳導 結構可供打金線導通電路。 4.直接利用罩蓋層4G整合設計為電路之一部份，有效增 加該罩蓋層功能，並減少封裝成本。 全士 〃月匕夠1^思5周控微機電結構211白勺厚重，利用該微機電 結構211 —側尚留有預設厚度的懸空秒基底10,可供使用者依 知需求調控微機電結構211在爵時的重量、扭力科物理特 16 200926310 y 性。 本發明又一實施例，請參閱第21至29圖之實施例，本實 施例特別適用罩蓋層採用導電材料的實施；本發明密封腔微型 結構製造方法之詳細說明如下； 如第21圖所示’首先於一矽基底10上表面沈積區域的絕 緣層20，該區域21包含數組層疊之微機電結構〖η及環繞其週 〇 侧的若干彼此獨立之傳導結構212，前述各組微機電結構211之 間、各微機電結構211與該傳導結構212間皆具備間隔區213， 該區域21被絕緣層20包覆； 如第22、23圖所示，將絕緣層2〇進行離子蝕刻（RIE)，該 絶緣層20經過RIE钱刻後，該區域21之微機電結構21丨及環繞其 週側若干獨纹料結顧，硕述各組_電結構211 之間、各微機電結構211與各傳導結構212間的間隔區213也被 〇 蝕刻成中空狀態； 如第24圖所示，在絕緣層20上方披覆一層犧牲層3〇，該犧 牲層30充填於前述間隔區213内，且該犧牲覆蓋該區域21 之微機電結構211及傳導結構212的表面； 如第25圖所示，於石夕基底10之下背面進行飯刻，且於石夕 基底10定向形成到達絕緣層20、通連該間隔區213的空間⑻； 如第26圖所示，在該犧牲層30上製作多數穿孔31，且前 17 200926310 述穿孔31射獅於各個料結構犯之上方㈣孔31到 達該區域2丨之各個傳導結構212表面，且排列圍繞該 之微機電結構211; 如弟27圖所示，在前述犧牲層3〇表面上沈積—罩 40，該罩蓋層40採用導雷奸 » ^ ^ ^ 4¾•材枓，且罩盍層40的覆蓋範圍含苗 多數穿孔31，並且罩蓋屌4Π古+古、仓λ义、+.咖 息 蓋層40充填進入刖述穿孔31内後接觸夂 個傳導結構212表面； 如第28目所示，接著再將犧牲層完全餘刻去除，位於^ 述絕緣層20之間隔區213内的犧牲層3〇及罩蓋層4g下方^ 犧牲層30皆透過罩蓋層40未充填的空間達成完錄刻去除的 效果，並且與該矽基底10之空間101相連通； 如第29圖所*，最後再沈積一密封層5〇在該罩蓋層如 外，且將罩蓋層40的孔隙完全密封，此時，利用罩蓋層4〇的 孔隙、中空的絕緣層20之間隔區213與矽基底1〇下方的空間 ιοί ’可以達成微機電結構2π之懸浮。 藉如述再一貫施例提供的一種密封腔微型結構製造方 法’其產生的效果在於： 1. 其降低微機電結構曝露、降低損傷機率。 2. 去除以往複雜、高成本的後製封裝作業。 3. 減少以往製作多道犧牲層的成本與麻煩手續。 18 200926310 4.直接利鮮蓋層整合設計為電路之—部份，並減少 封裝成本。 5·能夠隨意調控懸浮結構的厚重。 不僅„轉$結構212的暴露表面可供打金線導通電路之 用再利用計彼此獨立之傳導結構212來連接罩蓋層4〇,各 個傳導結構212可以分別設定不同的電路功能，也可以利用若 Θ的傳‘結構212來連接不同的微機電結構211，進行更 © 複雜的電路設計變化。 本發明另一實施例請參閱第3〇至37圖之實施例，本實施 例4寸別適用罩盍層採用導電材料的實施；本發明密封腔微型結 構製造方法之詳細說明如下； 如第30圖所示，首先於一矽基底1〇上表面沈積内具區域21 的絕緣層20，該區域21包含數組層疊之微機電結構211及環繞 © 其週側的若干傳導結構212，前述傳導結構212由内而外包含彼 此獨立之内迴路2121、外迴路2122，前述各組微機電結構211 之間、各微機電結構211外側具備間隔區213，更在該傳導結構 212的内迴路2121、外迴路2122之間設有間隔區213，該區域21 被絕緣層20包覆； 如第31圖所示，將絕緣層20進行離子蝕刻（rie)，該絕緣 層20經過RIE姓刻後，該區域21之微機電結構211及環繞其週側 19 200926310 若干獨立之傳導結構212 (内迴路2121、外迴路2122)露出， 且前述各組微機電結構211之間、各微機電結構211的間隔區 213，以及傳導結構212的内迴路2121與外迴路2122的間隔區 213也被蝕刻成中空狀態； 如第32圖所示，在絕緣層20上方披覆一層犧牲層30，該犧 牲層30充填於前述間隔區213内，且該犧牲層30覆蓋該區域21 之微機電結構211及傳導結構212 (内迴路2121、外迴路2122) 〇 的表面； 如第33圖所示，於矽基底1〇之下背面進行蝕刻，且於矽 基底10定向形成空間lOi，該空間1〇1到達絕緣層2〇，並且 以空間101通連相應微機電結構21!的間隔區; 如第34圖所示，在該犧牲層3〇上製作多數穿孔31，且前 达牙孔31排列製作於各個傳導結構212的内迴路212丨之上 方，而牙孔31到達該區域21之内迴路2121表面，且排列圍 〇 繞該區域21之微機電結構211 ; 如第35圖所示’在前述犧牲層30表面上沈積-罩蓋層At the same time, as shown in Fig. 14, the deep reactive ion etching (j^IE) is followed by the spacer 213 of the tantalum insulating layer 20 to carry out the remaining moment of the Shixi substrate, and the money is carved into the pre-depth of depth. The hollow etching grooves 12' have the same depth of the hollow etching grooves 12; as shown in Fig. 15, a sacrificial layer 3 is coated over the insulating layer 20, and the sacrificial layer 30 is filled in the space 213 and the hollow etching groove 12 And the sacrificial layer 3 覆盖 covers the surface of the microelectromechanical structure 2 Π and the conductive structure 212 of the region 21; as shown in FIG. 16 , the money is engraved on the back surface of the Shi Xi substrate 10, and the Shi Xi substrate 10 Oriented to form a space 101 connecting the hollow etching groove 12; as shown in Fig. 17, a plurality of perforations 31 are formed on the sacrificial layer 3, and the perforations 31 are arranged above the conducting structure 212 and the perforations 31 are reached. The surface of the conductive structure 212 of the edge region 21, and the microelectromechanical structure 211 surrounding the region 21; © As shown in FIG. 18, a cap layer 40 is deposited on the surface of the sacrificial layer 30, and the cap layer 40 is electrically conductive. Material, and the coverage of the cover layer 4〇 covers the majority of the perforations 31' and the cover The layer 4 is filled into the aforementioned perforation & and then contacts the surface of the conductive structure 212; as shown in the 19th riding, the sacrificial layer is completely removed, and the sacrificial layer 3 is located in the spacer 213 of the insulating layer 20, The sacrificial layer 30 under the cover layer 4 and the hollow (four) 12 _ sacrificial layer % of the bottom of the cover layer are all passed through the cover 15 200926310, and the unfilled space of the cover layer 40 achieves the effect of complete removal of the cover, and the hollow I worm groove 12 The space 101 of the crucible substrate 10 is in communication with the floating electroplated substrate 10 of a predetermined thickness on the side of the microelectromechanical structure 211, so that the user can adjust the physical characteristics of the microelectromechanical structure 211; Finally, a sealing layer 50 is deposited on the outside of the cap layer 40, and the pores of the cap layer 40 are completely sealed. At this time, the pores of the cap layer 40 and the spacer layer 213 of the hollow insulating layer 2 are utilized. The suspension of the microelectromechanical structure 211 can be achieved by the hollow etching groove 12 of the substrate 1 and the space 1〇1 below the crucible substrate 10. The method for manufacturing a sealed cavity microstructure provided by the foregoing embodiments has the following effects: 1. It reduces the exposure of the microelectromechanical structure to reduce the probability of damage. 2. Remove the complex and costly post-packaging operations of the past. 3. Reduce the cost and troublesome procedures for making multiple sacrificial layers in the past, and the conductive structure is available for the gold wire conduction circuit. 4. Directly using the cover layer 4G to integrate design into a part of the circuit, effectively increasing the function of the cover layer and reducing packaging costs. The full moon and the moon are enough for 1^5 to control the micro-electromechanical structure 211. The micro-electromechanical structure 211-side has a preset thickness of the suspended second base 10, which can be used by the user to adjust the MEMS. Structure 211 in the weight of the time, the torsion of the physical special 16 200926310 y. For another embodiment of the present invention, please refer to the embodiments of FIGS. 21-29. This embodiment is particularly applicable to the implementation of the cover layer using a conductive material; the detailed description of the method for manufacturing the sealed cavity microstructure of the present invention is as follows; The insulating layer 20 is first deposited on the upper surface of the substrate 10, and the region 21 comprises an array of laminated microelectromechanical structures [n] and a plurality of mutually independent conductive structures 212 surrounding the circumferential side thereof, the aforementioned groups of microelectromechanical structures. Between 211, each microelectromechanical structure 211 and the conductive structure 212 are provided with a spacer 213, which is covered by the insulating layer 20; as shown in Figures 22 and 23, the insulating layer 2 is ion-etched (RIE) After the insulating layer 20 is etched by RIE, the microelectromechanical structure 21 of the region 21 and a plurality of monoliths around the circumference thereof are taken into consideration, and each group _ electrical structure 211 and each microelectromechanical structure 211 are The spacer 213 between the conductive structures 212 is also etched into a hollow state; as shown in FIG. 24, a sacrificial layer 3 is overlying the insulating layer 20, and the sacrificial layer 30 is filled in the spacer 213, and The sacrifice covers the area 21 The surface of the micro-electromechanical structure 211 and the conductive structure 212; as shown in FIG. 25, the back surface of the Shixia substrate 10 is subjected to a meal, and the Shishi substrate 10 is oriented to form an insulating layer 20 and communicate with the spacer 213. Space (8); as shown in Fig. 26, a plurality of perforations 31 are formed on the sacrificial layer 30, and the first 17 200926310 perforations 31 shoot the lions above the individual material structures. (4) The holes 31 reach the respective conductive structures 212 of the region 2 a surface, and arranged around the microelectromechanical structure 211; as shown in FIG. 27, a cover 40 is deposited on the surface of the sacrificial layer 3, and the cover layer 40 is made of a smear, ^^^^43⁄4• The coverage of the cover layer 40 includes a plurality of perforations 31, and the cover 屌4Π古+古, 仓λ义,+.Café cover layer 40 is filled into the surface of the perforation 31 to contact the surface of the conductive structure 212; As shown in the 28th, the sacrificial layer is completely removed, and the sacrificial layer 3〇 in the spacer region 213 of the insulating layer 20 and the sacrificial layer 30 under the cap layer 4g pass through the cap layer 40. The filling space achieves the effect of recording removal, and the space 101 with the crucible base 10 Connected; as shown in Fig. 29, finally depositing a sealing layer 5 on the cover layer, and completely sealing the pores of the cover layer 40. At this time, the pores of the cover layer 4 are hollow, The space 213 of the insulating layer 20 and the space 〇ο ' below the 矽 substrate 1〇 can achieve a suspension of the microelectromechanical structure 2π. A sealing cavity microstructure manufacturing method provided by a consistent embodiment has the following effects: 1. It reduces the exposure of the microelectromechanical structure and reduces the probability of damage. 2. Remove the complex and costly post-packaging operations of the past. 3. Reduce the cost and hassle of making multiple sacrificial layers in the past. 18 200926310 4. Direct integration of the cover layer is designed as part of the circuit and reduces packaging costs. 5. The thickness of the suspended structure can be arbitrarily regulated. Not only the exposed surface of the structure 212 can be used for the gold wire conduction circuit, but also the conductive structure 212 is connected to each other to connect the cover layer 4, and the respective conductive structures 212 can respectively set different circuit functions, and can also be utilized. If the structure of the structure is connected to the different micro-electromechanical structures 211, more complicated circuit design changes are made. For another embodiment of the present invention, please refer to the embodiments of Figures 3 to 37, and the present embodiment is applicable to 4 inches. The cover layer is implemented by using a conductive material; the detailed description of the method for manufacturing the sealed cavity microstructure of the present invention is as follows; as shown in FIG. 30, the insulating layer 20 having the region 21 is first deposited on the upper surface of a substrate 1 21 includes an array of stacked microelectromechanical structures 211 and a plurality of conductive structures 212 surrounding the periphery thereof. The conductive structures 212 include inner and outer loops 2121 and outer loops 2122, which are independent of each other, between the groups of microelectromechanical structures 211 Each of the microelectromechanical structures 211 has a spacer 213 on the outer side thereof, and a spacer 213 is disposed between the inner loop 2121 and the outer loop 2122 of the conductive structure 212. The region 21 is covered by the insulating layer 20. As shown in FIG. 31, the insulating layer 20 is ion-etched (rie), the insulating layer 20 is etched by the RIE, the microelectromechanical structure 211 of the region 21 and the surrounding side 19 200926310 a number of independent conductive structures 212 (the inner loop 2121, the outer loop 2122) are exposed, and the spacers 213 of the respective microelectromechanical structures 211, the microelectromechanical structures 211, and the inner loops 2121 and the outer loops 2122 of the conductive structures 212 are also Etching into a hollow state; as shown in FIG. 32, a sacrificial layer 30 is overlaid over the insulating layer 20, the sacrificial layer 30 is filled in the spacer 213, and the sacrificial layer 30 covers the microelectromechanical structure 211 of the region 21. And the conductive structure 212 (the inner loop 2121, the outer loop 2122) the surface of the crucible; as shown in Fig. 33, the back surface of the crucible substrate 1 is etched, and the crucible substrate 10 is oriented to form a space lOi, the space 1〇1 Arriving at the insulating layer 2, and connecting the space of the corresponding microelectromechanical structure 21! with the space 101; as shown in Fig. 34, a plurality of perforations 31 are formed on the sacrificial layer 3, and the front teeth 31 are arranged Inner loop 212 of each conductive structure 212丨On the side, and the tooth apertures 31 of the region 21 reaches the inner surface of the loop 2121, and arranged around the circumference of the square region 21 of the micro-electromechanical structure 211; as shown in FIG. 35 'is deposited on the surface of the sacrificial layer 30-- cap layer
設内迴路2121表面； 且罩蓋層40的覆蓋範圍含蓋 進入前述穿孔31内後接觸預 如弟3 6圖所示， 接著再將犧牲層 述絕緣層20之間隔區213内的犧牲層 完全姓刻去除，位於前 30及罩蓋層40下方的 20 200926310 犧牲層30皆透過罩蓋層40未充填的空間達成完全飯刻去除的 效果，並且讓部份間隔區213與該矽基底1〇之空間ι〇ι相 通； # 如第37圖所示，最後再沈積一密封層5〇在該罩蓋層如 外’且將罩蓋層40的孔隙完全密封，此時，利用罩蓋層仙的 孔隙、中空的絕緣層20之間隔區213與石夕基底1〇下方的空間 應’可以達成微機電結構211之懸浮，而傳導結構212的暴 ❹ 斜迴路2122表面可供打金線導通電路之用，並且傳導处構 =的内迴路2121來連接罩蓋層4()，產生密封於内的轨設 §十效果、設定不同的電路功能。 藉則述再貝苑例提供的一種密封腔微型結構製造方 法；其產生的效果在於： 1.其降低微機電結構曝露、降低損傷機率。 ® 往娜、冑縣的後製封裝作業。 3·減少以往製作多道犧牲層的成本與麻煩手續。 4·直接利用罩蓋層4〇整合設計為電路之一部份，且 導結構犯的暴露外迴路2122表面可供打金線導通電路之 1並且傳導結構212的内迴路挪來連接罩蓋層仙，產生 在封於⑽電路設計效果、設定不同的電路功能。 21 200926310 紅上所述，本案之創新設計係一種密封腔微型結構製造 方法，係於矽基底上表面形成具微機電結構的絕緣層，該區 域包含彼此之間具制隔㈣至少電結構及至少-傳 V，’、。構，經過蝕刻後以犧牲層充填於前述間隔區與傳導結構 表面並在犧牲層上相應該傳導結構製作穿孔後，在前述穿 孔内及表面沈積-罩蓋層，將犧牲層_絲後，再將微機 电、、’口構下方的石夕基底餘刻，達$的微機電結構懸浮後密封，‘ ❹ 藉此，有效避免微機電結構曝露，更能直接彻罩蓋層 與傳導結構的導通設計整合為電路之—部份，進喊少最後 封裝成本。 所以本發明之『具有產業之可彻性』應已毋庸置疑， 除此之外，在本案實施例所揭露出的特徵技術，於申請之前 並未曾見於諸刊物或公開使用，不但具有如上所述功效增進 之事實’更具有不可輕忽的附加功效，是故，本發明的^ ❹ 驗』以及『進步性』都已符合專利法規，爰依法提岭明 專利之申請，祈請惠予審查並早曰賜准專利，實感德便。 200926310 【圖式簡單說明】 第1圖至第11圖 第12圖至第 第21圖至第29圖 第30圖至第37圖 本發明實施例之方法步驟示意圖。 本發明於魏底下“㈣製作方法 步驟示意圖。 本發明於矽基底下背面蝕刻製作及傳 導結構變化方法步驟示意圖。 本發明製作傳導結構之外迴路及内迴 路方法步驟示意圖。 【主要元件符號說明】 矽基底10 空間101 空間11 中空蝕槽12 絕緣層20 區域21 微機電結構211 傳導結構212 内迴路2121 外迴路2122 間隔區213 犧牲層30 穿孔31 罩蓋層40 密封層50The surface of the inner loop 2121 is disposed; and the coverage of the cap layer 40 includes the cover entering the through-hole 31, and the contact is as shown in FIG. 36, and then the sacrificial layer in the spacer region 213 of the sacrificial layer insulating layer 20 is completely completed. The surname is removed, and the 20 200926310 sacrificial layer 30 located under the front 30 and the cover layer 40 all achieve the effect of complete meal removal through the unfilled space of the cover layer 40, and the partial spacer 213 and the crucible substrate 1〇 The space ι〇ι通通; # as shown in Fig. 37, finally depositing a sealing layer 5 〇 in the cover layer such as the outer layer 'and completely sealing the pores of the cover layer 40, at this time, using the cover layer The pores, the space 213 of the hollow insulating layer 20 and the space below the 夕 基底 substrate should be able to achieve the suspension of the microelectromechanical structure 211, and the surface of the turbulent circuit 2122 of the conductive structure 212 can be used for the gold wire conducting circuit. The inner circuit 2121 is used to connect the cover layer 4 (), and the inner rail is provided with a tens of effects and different circuit functions are set. A method for manufacturing a sealed cavity microstructure provided by Rebecue is described; the effect is as follows: 1. It reduces the exposure of the microelectromechanical structure and reduces the probability of damage. ® Post-packaging operations in Na, Gifu. 3. Reduce the cost and troublesome procedures for making multiple sacrificial layers in the past. 4. The direct use of the cover layer 4 is integrated into one part of the circuit, and the exposed outer circuit 2122 surface of the conductive structure is available for the gold wire conduction circuit 1 and the inner circuit of the conductive structure 212 is moved to connect the cover layer. Xian, produced in the circuit design (10) circuit effect, set different circuit functions. 21 200926310 Red, the innovative design of this case is a sealed cavity micro-structure manufacturing method, which is formed on the upper surface of the crucible substrate to form an insulating layer with micro-electromechanical structure, the region containing the separation between each other (4) at least electrical structure and at least - Pass V, ',. After etching, the sacrificial layer is filled with the sacrificial layer and the surface of the conductive structure, and after the perforation is formed on the sacrificial layer corresponding to the conductive structure, the cap layer is deposited in the perforation and the surface, and the sacrificial layer is post-wired. The micro-electromechanical, and the lithological substrate under the 'mouth structure' are engraved, and the micro-electromechanical structure up to $ is suspended and sealed, ' ❹ , thereby effectively avoiding the exposure of the micro-electromechanical structure, and directly closing the cover layer and the conductive structure. The design is integrated into the part of the circuit, and the final package cost is less. Therefore, the "intelligence of the industry" of the present invention should be undoubted. In addition, the feature technology disclosed in the embodiments of the present invention has not been seen in publications or publicly used before the application, not only as described above. The fact that the effect is improved is more indispensable. Therefore, the invention and the "progressiveness" of the present invention have been in compliance with the patent regulations, and the application for the patent of the Lingming has been submitted according to law. I am willing to grant a patent, and I feel really good. 200926310 [Simple description of the drawings] Fig. 1 to Fig. 11 Fig. 12 to Fig. 21 to Fig. 29 Fig. 30 to Fig. 37 are schematic diagrams showing the steps of the method of the embodiment of the present invention. The present invention is a schematic diagram of the steps of the method for the production process of the invention. The schematic diagram of the steps of the method for the etching of the underside of the substrate and the method for changing the structure of the conductive structure of the present invention. The steps of the method for fabricating the outer loop and the inner loop of the conductive structure according to the present invention.矽Substrate 10 Space 101 Space 11 Hollow etched trench 12 Insulating layer 20 Region 21 Microelectromechanical structure 211 Conducting structure 212 Inner loop 2121 Outer loop 2122 Spacer 213 Sacrificial layer 30 Perforation 31 Cover layer 40 Sealing layer 50