1356038 九、發明說明： 【發明所屬之技術領域】 微結構及金屬不當侵蝕破壞 本發明係關於-種微結構製造方法，特別是指一種入 新的可整合半導體製程之微結構製造方法，其能有效料 【先前技術】 按，現今羊導體微機電系統包含各種不同的半導體微 型結構’例如：不可動的探針、流道、孔穴結構，或是_ 些可動的彈簧、連桿、#輪㈤料動或是触彻等結 構。 將上述不同的結構和相關的半導體電路相互整合 可構成各種不同的半導體岸用· 糾製造方法提昇微機械 結構各種不同的功能，是未來车 x ^ 來+導體微機電糸統的關鍵指 I也疋未來進-步研究晶片時的嚴峻挑戰；若能研發改 進習知的技術’未來的發展性實無法預估。 目前製作微機電感㈣及致動H线皆需要在石夕基 層上製作出懸浮式結構；前述製程必須採用了先進的半導 體技術’例如：渴巍约丨. "、、^幻、乾蝕刻和犧牲層（sacrificial layer)去除等微機電專用作業。 濕I虫刻疋-種快迷有效银刻，而且不致餘刻其它材料 5 1,356038 的『蝕刻劑』（etchant)，因此，通常濕蝕刻對不同材料 會具有相當高的『選擇性』（selectivity)。然而，除了 結晶方向可能影響姓刻速率外，由於化學反應並不會對特 定方向有任何的偏好，因此濕敍刻本質上乃是一種『等向 性触刻』（isotropic etching)。等向性蝕刻意味著，濕 餘刻不但會在縱向進行钱刻，而且也會有橫向的钱刻效 果。橫向姓刻會導致所謂1P彳目丨 例蝕』（undercut)的現象發生； 相反的’在乾姓刻（電嗜 兒水蝕刻）中，電漿是一種部分解 離的氣體，乾蝕刻最大優 慢點即疋『非等向性蝕刻』 (anisotropic etching)。姊、 “、、'而，乾蝕刻的選擇性卻比渴 ㈣來得低（因為祕刻的麵刻機制基本上是-種物理交' 互作用；因此離子的撞擊尤 旦可以移除被餘刻的薄膜，也 同時會移除遮罩）。 # ' € 習用係於一石夕基層上矣 〜面形成至少一内 構的絕緣層，該微機電結檨4人 電路，前述習用結構進一二至二微結構與數個金屬 刀析，仍存在下列問題： 問題一：習用絕緣層上設有金屬連接； 層與金屬電路電性連結，卷"。亥金屬連接 護的t屬連接:將因受侵〜結構遭受破壞，故如何: 效保護該金4連接制㈣w當如係為目前極= 6 1356038 ··' 決之重點所在。 問題二：習用微結構進行蝕刻時，蝕刻液將直接侵蝕 不受保護的微結構而使結構遭受破壞’故如何有效保護該 微結構避免遭受不當侵蝕係為目前極欲解決之重點所在。 問題三：習用微機電結構必須採用光罩（mask)，方能 進行精密餘刻技術，但隨著微機電技術的設計愈來愈精 ' 細，造成光罩之製造愈來愈不容易，如此不但增加生產成 # 本，故如何採用替代性光罩即可進行精密蝕刻係為目前極 欲解決之重點所在。 而為了能夠有效解決前述相關議題，本發明創作人基 於過去在微機電（Microelectric Machanic System, MEMS) 領域所累積的研發技術與經驗，於數次試驗及多方嘗試 後，終於發展出一種可整合半導體製程之微結構製造方 法。 【發明内容】 本發明可整合半導體製程之微結構製造方法，其目的 之一在於有效避免與外部連接的金屬連接層遭受不當蝕 刻。 為達成上述目的，本發明可整合半導體製程之微結構 製造方法係於一矽基層上表面形成絕緣層，該絕緣層包含 7 1356038 至少一微結構與數個金屬電路，該絕緣層成型一與金屬電 路及外部導體電性連結的金屬連接層，該金屬連接層係外 露於該絕緣層表面上受一保護層覆蓋進行蝕刻。 藉由前述進一步分析將可獲得下述功效：該金屬連接 層受該保護層保護進行银刻，讓#刻液無法直接侵钱該金 屬連接層，避免該金屬連接層遭受破壞，最後再藉由#刻 保護層使外部導體透過與該金屬連接層電性連結後，令該 • 金屬電路透過打線與外部接合進行訊號傳輸。 本發明可整合半導體製程之微結構製造方法，其目的 之二在於有效避免微結構暴露遭受不當侵蝕。 為達成上述目的，本發明可整合半導體製程之微結構 製造方法係於一矽基層上表面形成絕緣層，該絕緣層包含 至少一微結構與數個金屬電路，該微結構與該金屬電路受 • 該絕緣層包覆進行蝕刻。 藉由前述進一步分析將可獲得下述功效：該微結構受 該絕緣層保護進行蝕刻，無論是採用由上而下蝕刻或由下 而上蝕刻，蝕刻液皆無法直接侵蝕該微結構，避免該微結 構之金屬暴露遭受破壞並產生污染機台腔體的金屬顆粒。 本發明可整合半導體製程之微結構製造方法，其目的 8 1356038 之三在於大幅簡化遮蔽所需的精密度需求進而降低整體 成本。 為達成上述目的，本發明可整合半導體製程之微結構 製造方法係於一石夕基層上表面形成絕緣層，該絕緣層包含 至少一微結構與數個金屬電路，該絕緣層上成型一保護層 進行絕緣層及矽基層之蝕刻空間成型。 藉由前述進一步分析將可獲得下述功效：該保護層及 # 保護蓋遮蔽取代精密光罩效果進行蝕刻，使該微結構達到 懸浮，以及金屬連接層上的保護層被移除，進而減輕使用 光罩耗費的成本；且該保護蓋進行切割時，該金屬連接層 將受該保護層保護免於割傷破損，另該保護蓋的設置將對 該矽基層與該絕緣層進行支撐對抗應力，進而避免受力破 碎提昇製程良率。 有關本發明為達成上述目的，所採用之技術、手段及 • 其他功效，茲列舉實施例並配合圖式詳細說明如後，相信 本發明之目的、特徵及其他優點，當可由之得一深入而具 體之瞭解。 【實施方式】 本發明實施例請參閱第1圖至第13圖所示，本發明可 整合半導體製程之微結構製造方法詳細說明如下： 9 Ϊ356038 請參閱第1圖所示，首先於-石夕基層1〇上表面u成型 —絕緣層20’該絕緣層20可為二氧化矽，該絕緣層2〇具有 至少一微結構（Micr〇structure) 21、複數個金屬電路U 及複數個互補式金屬氧化半導體（c〇mplementary1356038 IX. Description of the Invention: [Technical Field of the Invention] Microstructure and Metal Improper Erosion Damage The present invention relates to a method for fabricating a microstructure, and more particularly to a method for fabricating a microstructure into a new integrated semiconductor process. Effective material [Prior Art] According to the present, the sheep conductor MEMS consists of various semiconductor micro-structures such as: immovable probes, runners, hole structures, or _ some movable springs, connecting rods, #轮(五) Feeding or touching structures. Integrating the above different structures and related semiconductor circuits into each other can constitute various semiconductor shores. The manufacturing method improves the various functions of the micro-mechanical structure, and is the key point of the future car x ^ + + conductor MEMS In the future, we will continue to study the challenges of wafers; if we can develop and improve our know-how, the future development cannot be predicted. At present, the fabrication of the microcomputer inductor (4) and the actuation of the H-line all require the suspension structure to be fabricated on the Shixi base layer; the above process must use advanced semiconductor technology 'for example: thirst 丨. ",, 幻, dry etching And micro-electromechanical special operations such as sacrificial layer removal. Wet I insects are engraved and effective, and they do not leave the etchant of other materials 5 1,356038. Therefore, wet etching usually has a relatively high selectivity for different materials. Selectivity). However, in addition to the fact that the direction of crystallinity may affect the rate of surnames, wet characterization is essentially an isotropic etching because the chemical reaction does not have any preference for a particular direction. Isotropic etching means that the wet moment will not only be burned in the vertical direction, but also have a horizontal effect. The horizontal surname engraving leads to the phenomenon of the so-called 1P under 蚀 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 相反 相反 相反 相反 相反 相反 相反 相反 相反 相反 相反 相反 相反 相反 相反 相反 相反 相反 相反 相反 相反The point is "anisotropic etching".姊, ",, ', the selectivity of dry etching is lower than that of thirst (four) (because the secret engraving mechanism is basically a kind of physical interaction ' interaction; therefore the impact of ions can be removed by Yu Dan The film will also remove the mask.) # ' € The utility system is based on the upper layer of the 石 夕 layer to form at least one internal insulation layer, the MEMS is a four-person circuit, and the aforementioned conventional structure is one to two. The two micro-structures and several metal-knifes still have the following problems: Problem 1: The conventional insulation layer is provided with a metal connection; the layer is electrically connected with the metal circuit, and the volume is connected with the "metal connection": Invaded ~ structure is damaged, so how to: protect the gold 4 connection system (four) w when the current pole = 6 1356038 · · ' The focus of the decision. Problem 2: the conventional micro-structure etching, the etching solution will directly erode The unprotected microstructure causes the structure to be damaged. Therefore, how to effectively protect the microstructure from undue erosion is the focus of the current problem. Problem 3: The conventional micro-electromechanical structure must use a mask. Enter Precision engraving technology, but with the design of MEMS technology becoming more and more refined, the manufacture of reticle is becoming more and more difficult, so not only increase the production into #本, so how to use alternative reticle to carry out precision The etching system is currently the focus of the solution. In order to effectively solve the above-mentioned related issues, the creators of the present invention have based on the research and development techniques and experience accumulated in the field of Microelectric Machanic System (MEMS) in several experiments and After many attempts, a micro-structure manufacturing method capable of integrating semiconductor processes has finally been developed. SUMMARY OF THE INVENTION The present invention can integrate a semiconductor manufacturing method for manufacturing a microstructure, and one of its purposes is to effectively avoid improper handling of a metal connection layer connected to the outside. In order to achieve the above object, the microstructure manufacturing method of the integrated semiconductor process of the present invention is to form an insulating layer on the upper surface of a base layer, the insulating layer comprising 7 1356038 at least one microstructure and a plurality of metal circuits, the insulating layer forming a a metal connection layer electrically connected to the metal circuit and the outer conductor, the metal connection The bonding layer is exposed on the surface of the insulating layer and covered by a protective layer for etching. By further analysis as described above, the following effects can be obtained: the metal connecting layer is protected by the protective layer for silver engraving, so that the #刻液 cannot directly invade The metal connection layer is prevented from being damaged by the metal connection layer. Finally, the external conductor is electrically connected to the metal connection layer by the #刻保护层, and then the metal circuit is transmitted through the wire bonding and external bonding. The invention can integrate the microstructure manufacturing method of the semiconductor process, and the second purpose thereof is to effectively prevent the microstructure from being exposed to improper erosion. To achieve the above object, the micro-structure manufacturing method capable of integrating the semiconductor process of the invention is formed on the upper surface of a substrate. An insulating layer comprising at least one microstructure and a plurality of metal circuits, the microstructure and the metal circuit being covered by the insulating layer for etching. By the foregoing further analysis, the following effects can be obtained: the microstructure is etched by the protection of the insulating layer, and the etching solution can not directly erode the microstructure, whether it is etched from top to bottom or from bottom to top, avoiding the The metal exposure of the microstructure is destroyed and produces metal particles that contaminate the chamber cavity. The present invention can integrate a microfabric fabrication method for a semiconductor process, and its purpose is to substantially simplify the precision requirements required for shading and thereby reduce the overall cost. In order to achieve the above object, the microstructure manufacturing method of the integrated semiconductor process of the present invention is to form an insulating layer on an upper surface of a base layer, the insulating layer comprising at least one microstructure and a plurality of metal circuits, and a protective layer is formed on the insulating layer. The etching space of the insulating layer and the ruthenium base layer is formed. By the above further analysis, the following effects can be obtained: the protective layer and the #protective cover shield are etched instead of the precision mask effect, the microstructure is suspended, and the protective layer on the metal connection layer is removed, thereby reducing the use The cost of the reticle; and when the protective cover is cut, the metal connecting layer is protected from the damage by the protective layer, and the protective cover is disposed to support the 矽 base layer and the insulating layer against stress, In turn, the force is broken to improve the process yield. The present invention has been described with reference to the embodiments and the detailed description of the embodiments of the present invention. Specific understanding. [Embodiment] Please refer to FIG. 1 to FIG. 13 for the embodiment of the present invention. The detailed description of the manufacturing method for the microstructure of the integrated semiconductor process of the present invention is as follows: 9 Ϊ356038 Please refer to FIG. 1 , first in the -Shi Xi Base layer 1 〇 upper surface u-forming insulating layer 20 ′, the insulating layer 20 may be cerium oxide, the insulating layer 2 〇 having at least one microstructure (Micr〇 structure) 21 , a plurality of metal circuits U and a plurality of complementary metals Oxidized semiconductor
Meta卜Oxide-Semiconductor，CMOS)電路層 23，該微結 構21、5亥金屬電路22及該互補式金屬氧化半導體電路層 分別受該絕緣層2〇包覆； 該微結構21周側設有該金屬堆疊層24，該金屬堆疊層 24係由鋁鋼合金、鎢或鈦等金屬交互堆疊而成，該金屬堆 疊層24外露是用來蝕刻所需空間，該金屬堆疊層24採用能 被银刻液侵蝕的材質’前述該微結構21受該絕緣層20包覆 下並未與該金屬堆疊層24接觸； 該絕緣層2 0表面成型一與該金屬電路2 2電性連結的 金屬連接層30，該金屬連接層30外露係可用來與外部導體 電性連結’讓該金屬電路22與外部導體進行訊號連結； 言亥絕緣層2 0在標準半導體製程的最後於表面沉積一 為鈍化材質的第一保護層40,該第一保護層40係採用電漿 輔助化學氣相沉積（Plasma-Enhanced CVD，PECVD)、常壓 化學氣相沉積（Atmospheric Pressure CVD，APCVD)或低 壓化學氣相沉積（Low-Pressure CVD，LPCVD)等技術進行 '儿積’ 5亥弟一保護層40係由一氮化物（nitride)層及一氧 1356038 化物（oxide)層所組成，接著利用曝光、顯影及蝕刻等技 術使得特定區域外露而不受該第一保護層40覆蓋，前述特 定區域包含該金屬堆疊層24表面、該金屬連接層30表面及 包覆該微結構21之絕緣層20的表面； 請參閱第2圖所示，該絕緣層20於表面沉積一為氧化 材質的第二保護層5 0 ’該第二保護層5 0係採用電聚輔助化 籲 學氣相沉積（Plasma-Enhanced CVD，PECVD)、常壓化學氣 相沉積（Atmospheric Pressure CVD，APCVD)或低壓化學 氣相沉積（Low-Pressure CVD，LPCVD)等技術進行沉積， 使外露於該絕緣層20表面的該金屬堆疊層24、該金屬連接 層30及該第一保護層40分別受該第二保護層50覆蓋； 請參閱第3圖所示，對該金屬堆疊層24表面的第二保 * 護層50及包覆該微結構21之絕緣層2〇表面的第二保護層 50進行鍅刻去除； 請參閱第4圖所示，對該金屬堆疊層24蝕刻（係採用濕 蝕刻或乾蝕刻），去除該金屬堆疊層24進而形成貫通該絕 緣層20的蝕刻空間2〇1，且於蝕刻過程中，仍被該第二保 護層50覆蓋的部份，將受該第二保護層5〇作為蝕刻光罩保 1356038 護避免遭受侵蝕，以及受該絕緣層20包覆的該微結構21 也將避免遭受侵蝕； 請參閱第5圖所示，利用該絕緣層20對該矽基層10的 高蝕刻選擇比，對相對該絕緣層20之蝕刻空間201的矽基 層10正面進行蝕刻（係採用深活性離子蝕刻Deep Reactive Ion Etching, DR IE)，去除局部石夕基層10，進而 • 形成尚未貫通該矽基層10的蝕刻空間101，且於蝕刻過程 中，仍被該第二保護層50覆蓋的部份，將受該第二保護層 50作為蝕刻光罩保護避免遭受侵蝕，以及受該絕緣層20 包覆的該微結構21也將避免遭受侵蝕； 請參閱第6圖所示，該第二保護層50上設置一為玻璃 或為矽晶圓的保護蓋60，該保護蓋60與該第二保護層50 • 之間透過一黏著層70結合，且該保護蓋60與該第二保護層 50彼此相距一特定距離，該保護蓋60於表面設置一層環氧 化物（epoxy)，該保護蓋60透過該環氧化物彈性緩衝封裝 壓力避免損壞，該矽基層10與該絕緣層20受該保護蓋60 支撐下，使該矽基層10與該絕緣層20於運送時將避免受力 破裂碎掉，因製程所需該矽基層10必須磨薄到300um以 下，磨薄將會因應力產生翹曲，如不使用該保護蓋60作為 12 1356038 支撐將容易破裂碎掉，一旦損毀將宣告製程失敗，造成製 程良率因此降低； 請參閱第7圖所示，對相對該絕緣層20之蝕刻空間201 的矽基層10由背面進行蝕刻（係採用深活性離子蝕刻或溼 蝕刻），去除局部矽基層10，使該蝕刻空間101貫通該矽基 層10，讓該矽基層10的蝕刻空間101與該絕緣層20的蝕刻 • 空間201相互連貫通，令該微結構21形成懸浮狀態；前述 該微結構21受該絕緣層20包覆下，除了作為深活性離子蝕 刻光罩，更可避免該微結構21内部的金屬電路22裸露蝕刻 濺出污染機台腔體的金屬顆粒； 請參閱第8圖所示，切割該保護蓋60，使該金屬連接 層30上的第二保護層50不受該保護蓋60遮蔽，該保護蓋60 • 作為蝕刻光罩對特定區域進行蝕刻去除； 請參閱第9圖所示，該保護蓋60於切割時，該金屬連 接層30於該第二保護層50保護下，將避免該金屬連接層30 遭受割傷，對該金屬連接層30上的第二保護層50進行蝕 刻，讓該金屬連接層30外露於該絕緣層20表面，且於蝕刻 過程中，該微結構21受該絕緣層20及該保護蓋60保護避免 13 1356038 -身爲，以及該絕緣層透過表面特定區域的第—保護 層40進行蝕亥彳’利用氧化1層與1彳匕層的#刻選擇比’讓特 定區成透過該第一保護層4〇保護避免遭受侵蝕，使外部導 體透過與該金屬連接層30電性連結後，令該金屬電路22 透過打線與外部接合進行傳輸訊號。 下列第10圖至第13圖係為第6圖至第9圖之另一實施 • 態樣： 請參閱第10圖所示’採用等向性乾蝕刻或溼蝕刻沿著 該矽基層10晶格面蝕刻分離矽基層10形成蝕刻空間1〇1， 令該微結構21形成懸浮狀態，或是，採用深活性離子钱刻 不長側壁保護的參數，對該矽基層10的蝕刻空間1〇1進行 姓刻分離矽基層10形成蝕刻空間1〇1，令該微結構2丨形成 懸浮狀態，前述該微結構21受該絕緣層2〇包覆下，除了作 _ 為蝕刻光罩，更可避免該微結構2丨内部的金屬電路22裸露 钕刻滅出污染機台腔體的金屬顆粒； 5月麥閱第11圖所示，該第二保護層5〇上設置一為玻螭 或為矽阳圓的保護蓋60，該保護蓋60與該第二保護層5〇 之間透過—點著層70結合，且該保護蓋60與該第二保護層 5〇彼此相距一特定距離，該保護蓋60於表面設置一層環氧 14 二保護蓋6°透w氧化物彈性緩衝封裝 支標下、切基層職該絕緣㈣受該保護蓋6 〇 破裂碎掉，71基#層1G與該絕緣層2G於運送時將避免受力 下，磨薄將:因7所需該_0必須磨薄^ 支樓將容易護蓋60作為 裎良率因轉低；敗’⑽ 清參閱第12圖所示，切割該保護蓋60，使該金屬連接 層30上的第二保護層5〇不受該保護蓋60遮蔽，該保護蓋6〇 作為钱刻光罩對特定區域進行蝕刻去除； 請參閱第13圖所示，該保護蓋60於切割時，該金屬連 接層30於該第二保護層50保護下，將避免該金屬連接層3〇 遭受割傷’對該金屬連接層30上的第二保護層50進行钱 刻’讓該金屬連接層30外露於該絕緣層20表面，且於蝕刻 過程中’該微結構21受該絕緣層20及該保護蓋60保護避免 遭受侵蝕，以及該絕緣層20透過表面特定區域的第一保護 層40進行蝕刻，利用氧化層與氮化層的蝕刻選擇比，讓特 定區域透過該第一保護層40保護避免遭受侵钱，使外部導 體透過與該金屬連接層30電性連結後，令該金屬電路22 15 1356038 透過打線與外部接合進行傳輸訊號。 综上所述，本發明『產業之可利用性』已顯而易見， 且本案實施例所揭露出的特徵技術，並未見於各刊物及傳 媒’亦未曾被公開使用’更具有不可輕忽義加功效，故 本1月的新1貞性』以及『進步性』都已符合專利法規，a Meta-Oxide-Semiconductor (CMOS) circuit layer 23, the microstructure 21, the 5th metal circuit 22, and the complementary metal oxide semiconductor circuit layer are respectively covered by the insulating layer 2; the microstructure 21 is provided on the peripheral side thereof a metal stack layer 24, which is formed by alternately stacking metals such as aluminum steel alloy, tungsten or titanium. The metal stack layer 24 is exposed for etching. The metal stack layer 24 can be silver-etched. The material of the liquid etching is not covered by the insulating layer 20 and is not in contact with the metal stacking layer 24; the surface of the insulating layer 20 is formed with a metal connecting layer 30 electrically connected to the metal circuit 22 The metal connection layer 30 is exposed to be electrically connected to the external conductor. The signal is connected to the external conductor. The insulating layer 20 is deposited on the surface of the standard semiconductor process as a passivation material. a protective layer 40, the first protective layer 40 is plasma-assisted chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD) or low pressure chemical vapor deposition (Low-Pressure CVD, LPCVD) and other technologies for the 'Children' 5 Shield-protective layer 40 consists of a nitride layer and an oxide 1356038 oxide layer, followed by exposure, development and etching. The technique exposes a specific region that is not covered by the first protective layer 40, and the specific region includes the surface of the metal stacked layer 24, the surface of the metal connecting layer 30, and the surface of the insulating layer 20 covering the microstructure 21. As shown in FIG. 2, the insulating layer 20 is deposited on the surface with a second protective layer 50 of an oxidized material. The second protective layer 50 is electrically-assisted by vapor deposition (Plasma-Enhanced CVD, PECVD). Deposited by techniques such as Atmospheric Pressure CVD (APCVD) or Low-Pressure CVD (LPCVD) to expose the metal stack layer 24 on the surface of the insulating layer 20, The metal connection layer 30 and the first protection layer 40 are respectively covered by the second protection layer 50. Referring to FIG. 3, the second protection layer 50 on the surface of the metal stack layer 24 and the microstructure are covered. 21 insulation layer 2 surface The second protective layer 50 is etched away; as shown in FIG. 4, the metal stacked layer 24 is etched (by wet etching or dry etching), and the metal stacked layer 24 is removed to form an etch through the insulating layer 20. The space is 2〇1, and during the etching process, the portion still covered by the second protective layer 50 will be protected by the second protective layer 5 as an etch mask to protect against erosion, and the insulating layer 20 The coated microstructure 21 will also be protected from erosion; see Figure 5 for a high etch selectivity of the ruthenium substrate 10 using the insulating layer 20, and a ruthenium layer for the etched space 201 of the insulating layer 20. 10 etching is performed on the front side (Deep Reactive Ion Etching, DR IE) to remove the local base layer 10, thereby forming an etching space 101 that has not penetrated the base layer 10, and is still in the etching process. The portion covered by the second protective layer 50 will be protected by the second protective layer 50 as an etch mask to avoid erosion, and the microstructure 21 covered by the insulating layer 20 will also be protected from erosion; Figure A protective cover 60 is formed on the second protective layer 50 as a glass or a germanium wafer. The protective cover 60 is bonded to the second protective layer 50 through an adhesive layer 70, and the protective cover 60 is The second protective layer 50 is spaced apart from each other by a specific distance. The protective cover 60 is provided with an epoxy layer on the surface. The protective cover 60 is protected from damage through the epoxy elastic buffering package pressure. The germanium base layer 10 is insulated from the insulating layer. The layer 20 is supported by the protective cover 60, so that the base layer 10 and the insulating layer 20 are prevented from being broken by force during transportation, and the base layer 10 must be thinned to 300 um or less as required for the process. If the stress is warped, if the protective cover 60 is not used as the support of 12 1356038, it will be easily broken and broken. Once the damage will be declared, the process will fail, resulting in a decrease in the process yield. See Figure 7 for the opposite insulation layer. The ruthenium base layer 10 of the etched space 201 of 20 is etched from the back surface (by deep reactive ion etching or wet etching), and the local ruthenium base layer 10 is removed, so that the etched space 101 penetrates the ruthenium base layer 10, and the etched space of the ruthenium base layer 10 is allowed. 1 The etching and space 201 of the insulating layer 20 are connected to each other to make the microstructure 21 form a suspended state; the microstructure 21 is covered by the insulating layer 20, and can be avoided as a deep active ion etching mask. The metal circuit 22 inside the microstructure 21 is exposed and etched to splash metal particles contaminating the chamber cavity; as shown in FIG. 8, the protective cover 60 is cut so that the second protective layer 50 on the metal connection layer 30 is not Covered by the protective cover 60, the protective cover 60 • etches and removes a specific area as an etch mask; as shown in FIG. 9 , the metal cover layer 30 is on the second protective layer when the protective cover 60 is cut. Under the protection of 50, the metal connecting layer 30 is prevented from being cut, and the second protective layer 50 on the metal connecting layer 30 is etched to expose the metal connecting layer 30 to the surface of the insulating layer 20, and during the etching process. The microstructure 21 is protected by the insulating layer 20 and the protective cover 60 to avoid the first protective layer 40 of the specific surface of the insulating layer, and the first layer and the first layer of the insulating layer are etched. Layer #刻选择比Let a specific region through the first protective layer to protect against erosion 4〇, passes through the external conductor is connected to the metal layer 30 is electrically connected, enabling the metal circuit 22 for signal transmission through a wire bonded to the outside. Figures 10 through 13 below are another embodiment of Figures 6 through 9. • See Figure 10 for an isotropic dry etch or wet etch along the 矽 base layer 10 lattice The etch-etching separation of the ruthenium base layer 10 forms an etched space 〇1, so that the microstructure 21 is in a suspended state, or the etched space 1〇1 of the ruthenium base layer 10 is performed by using a parameter of deep active ions and no side wall protection. The surname is separated from the base layer 10 to form an etching space 1〇1, so that the microstructure 2丨 is in a suspended state, and the microstructure 21 is covered by the insulating layer 2, except that it is an etching mask, which can avoid the The metal circuit 22 inside the microstructure 2 is exposed to smear out the metal particles of the contaminated machine cavity; as shown in Fig. 11 of May, the second protective layer 5 is provided with a glass or a sun. a protective cover 60 is disposed between the protective cover 60 and the second protective layer 5, and the protective cover 60 and the second protective layer 5 are separated from each other by a specific distance. The protective cover 60 on the surface of a layer of epoxy 14 two protective cover 6 ° transparent w oxide elastic buffer package under the subscript The base layer of the insulation (4) is broken by the protective cover 6 〇, 71 base #层1G and the insulation layer 2G will be protected from the force when transported, the thinning will be: because the 7 required _0 must be thin ^ The support will easily cover the cover 60 as the turn-off rate is lowered; as shown in Fig. 12, the protective cover 60 is cut so that the second protective layer 5 on the metal connection layer 30 is not protected. The cover 60 is shielded, and the protective cover 6 is used as a money mask to etch and remove a specific area; as shown in FIG. 13 , the metal cover layer 30 is protected by the second protective layer 50 when the protective cover 60 is cut. The metal connection layer 3 is prevented from being cut by the second protective layer 50 on the metal connection layer 30. The metal connection layer 30 is exposed on the surface of the insulation layer 20 during the etching process. The microstructure 21 is protected by the insulating layer 20 and the protective cover 60 from erosion, and the insulating layer 20 is etched through the first protective layer 40 of the specific surface of the surface, using an etching selectivity ratio of the oxide layer to the nitride layer. Allowing a specific area to be protected from invading by the first protective layer 40, so that Portion passes through the guide body is connected to the metal layer 30 is electrically connected, enabling the metal circuit 22151356038 signal transmitted through a wire bonded to the outside. In summary, the "industry availability" of the present invention has been apparent, and the feature technology disclosed in the embodiments of the present invention has not been seen in the publications and the media 'has not been publicly used', and is more indispensable. Therefore, the new one in January and the "progressive" have been in compliance with patent regulations.
驗法提出發料利之申請，祈料予錢並早日賜准專 利’實感德便。 1356038 【圖式簡單說明】 第1圖至第13圖係本發明之微結構製造方法示意圖。 【主要元件符號說明】 《本發明》 矽基層10 蝕刻空間101 上表面11 Φ 絕緣層20 蝕刻空間201 微結構21 金屬電路22 互補式金屬氧化半導體電路層23 金屬堆疊層24 金屬連接層30 第一保護層40 • 第二保護層50 保護蓋60 黏著層70 17The test method proposes the application for the issue of the proceeds, prays for the money and gives the patent as soon as possible. 1356038 [Simple description of the drawings] Figs. 1 to 13 are schematic views showing the manufacturing method of the microstructure of the present invention. [Main component symbol description] "The present invention" 矽 base layer 10 etching space 101 upper surface 11 Φ insulating layer 20 etching space 201 microstructure 21 metal circuit 22 complementary metal oxide semiconductor circuit layer 23 metal stack layer 24 metal connection layer 30 first Protective layer 40 • Second protective layer 50 Protective cover 60 Adhesive layer 70 17