201227873 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種微機電結構的製造方法。 【先前技術】 隨著半導體製程技術的進步’已推動微機電系統 (MEMS)的蓬勃發展。在傳統微機械系統的製造方法中，主 動元件製程與微機電製程是分開進行，在分別完成主動元 _件電路與微機電結構後，再將兩者整合在同一基材上而完 成微機電糸統。上述的製造方法又稱為r System In Package」 (SIP)。 另一種習知的製程方式是在形成主動元件電路中諸如 金屬氧化物半導體元件(MOS)及雙載子接面電晶體(BJT)等 半導體元件後，進行形成微機電結構的製程，然後再進行 主動元件電路的金屬化製程而完成晶圓層級(wafer level) 的微機電系統。隨後將晶圓切割成晶片（Die)，最後再進行 _晶片的封裝。在微機電結構的製造過程中，通常採用諸如 反應性離子蝕刻（RIE)之電漿蝕刻方式來形成微機電結構 中可移動的構件或部分。但是，以上述方式所形成的微機 電結構的輪廓(profile)並不理想，且使用反應性離子蝕刻所 需的設備昂貴。此外，在形成微機電結構之後，進行晶片 封裝之前’環境中的微粒或污染物可能掉落至微機電結構 中’而使微機電結構無法運作。因此，目前亟需一種新的 微機電結構之製造方法，期能改善上述問題。 201227873 【發明内容】 本發明之一目的係提供一種微機電結構的製造方法， 俾能在微機電結構中形成三個維度的電容。 本發明之另一目的係提供一種微機電結構的製造方 法，俾能降低微機電結構的製造成本，且形成良好的微機 電結構輪廓。 本發明之再一目的係提供一種微機電結構的製造方 法，俾能在晶圓層級完成封裝。 根據本發明之實施方式，上述製造方法包括以下步 驟：（a)形成一電路層於一第一基板之一上表面，該電路層 包括一微結構、一釋放特徵結構以及一連接墊，其中該釋 放特徵結構圍繞該微結構之周邊的一部分並貫穿該電路 層，且該釋放特徵結構係由一金屬材料所製成，該連接墊 位於該電路層之一外表面；（b)形成一抗蝕刻層於該電路層 上，其中該釋放特徵結構露出於該抗蝕刻層；（c)藉由濕蝕 刻製程移除該釋放特徵結構，以露出該第一基板；（d)使 用一非等向性蝕刻步驟以蝕刻露出之該第一基板；（e)配置 一第二基板於該電路層上方，其中該第二基板之一下表面 具有一第一金屬層以及一第二金屬層電性連接該第一金屬 層，且該第一及第二金屬層分別大致對準該微結構以及該 連接墊；（f)形成一孔洞貫穿該第一基板，其中該孔洞大致 位於該連接墊下方；（g)填充一高分子材料於該孔洞中；（h) 移除位於該微結構下方之該第一基材的部分，以釋放該微 結構；⑴配置一第三基板於該第一基板之該下表面；⑴由 該第三基板之一側形成一連接孔，其中該連接孔貫穿該第 201227873 三基板、該高分子材料以及該連接墊，而露出該第二金屬 層以及該連接墊；以及(k)形成一導電層於該連接孔中，以 電性連接該露出的連接墊與該露出的第二金屬層。 根據本發明一實施方式，上述步驟（a)之形成該電路層 包括形成一互補式金屬氧化物半導體結構，其電性連接該 微結構以及該連接墊。在一實施例中，該釋放特徵結構係 在形成該互補式金屬氧化物半導體結構時形成。 根據本發明一實施方式，上述步驟(b)之該抗蝕刻層包 含一氧化石夕層以及一氮化石夕層。 根據本發明一實施方式，上述步驟(c)包括應用一包含 硫酸以及過氧化氫之蝕刻劑。 根據本發明一實施方式，上述步驟（d)之該非等向性蝕 刻包括一反應離子蝕刻步驟以及一深式反應離子蝕刻步 驟。 根據本發明一實施方式，上述步驟(d)包括形成一凹陷 部於該第一基板，該凹陷部之深度為約5 /im至約60 // m ° 根據本發明一實施方式，上述步驟（e)之該第一金屬層 與該微結構間之一間距為約1 至約50 //m。 根據本發明一實施方式，在步驟(e)之後，且在步驟(f) 之前，更包括：研磨該第一基板的下表面，以減少該第一 基板的厚度。 【實施方式】 請參照第 1圖，其為本發明一實施方式之微機電結構 6 201227873 的上視示意圖。微機電結構可應用在例如加速度偵測器 (accelerometer)或陀螺儀（gyroscope)等之微機電慣性感測 襄置。第1圖係繪示一微機電加速度偵測器，但本發明以 下所揭露的製造方法可適用在其他的微機電裝置中’並不 限於微機電加速度偵測器。 如第1圖所示，微機電加速度偵測器100主要包括可 動的微結構11〇、半導體電路12〇以及複數個連接墊130 以及電路層140。半導體電路120大致配置在可動的微結 • 構110之外圍。連接墊130通常可配置在半導體電路120 的外圍。 微結構110容置在電路層140的凹槽142中，且微結 構包括中心部112、至少一彈性支撐件114以及至少一凸出 物116 °彈性支撐件114連接中心部112與電路層140,且 使中心部H2呈現可移動狀態。凸出物116由中心部112 向外延伸，且與基材延伸出的另一凸出物144形成一電容。 半導體電路120電性連接凸出物144及凸出物116， % =量測兩凸出物116、144之間的電容值，並將所量測的電 谷訊號轉變為一電壓訊號。半導體電路12〇可包括一互補 式金屬氧化物半導體裝置。半導體電路12〇可經由連接墊 130而電性連接一外部電路(未繪示）。 在操作時’當微機電加速度偵測器1〇〇受到一加速度 夺凸出物144與凸出物116之間的距離改變，使其間的 電容值發生變化。半導體電路120量測上述電容值或電容 值的變化量，而得以估算微機電加速度偵測器i⑻所受到 的加速度。 201227873 上述微機電加速度偵測器100僅為示範性例子，以易 於暸解本發明的内容以及下文將揭露的製造方法，本發明 並不限於製造微機電加速度偵測器。此外，上述各元件以 及各元件之間的連接關係及相對關係，僅為說明之目的， 不應被解釋為本發明的限制。 第2圖係繪示本發明一實施方式之微機電結構之製造 方法的流程圖。第3A圖至3H圖係繪示本發明一實施方式 之製造方法中’各製程階段的剖面示意圖。第3A圖至3H 圖大致為第1圖中的線段3-3，的剖面示意圖。以下將以第 1圖中微機電結構為例，詳細揭露本發明一實施方式之微 機電結構的製造方法。本發明以下所揭露的各實施例，在 有益的情形下可相互組合或取代，也可在一實施例中附加 其他的實施例，而無須進一步的記載或說明。 進行步驟201，形成電路層320於第一基板310上， 如第3A圖所示。電路層32〇包括微結構322、釋放特徵結 構324、連接墊326以及介電材料層328。連接墊326位於201227873 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of fabricating a microelectromechanical structure. [Prior Art] With the advancement of semiconductor process technology, the development of microelectromechanical systems (MEMS) has been promoted. In the manufacturing method of the traditional micro-mechanical system, the active component process and the micro-electromechanical process are performed separately. After the active element-piece circuit and the micro-electromechanical structure are respectively completed, the two are integrated on the same substrate to complete the micro-electromechanical process. System. The above manufacturing method is also called r System In Package" (SIP). Another conventional process is to form a process of forming a microelectromechanical structure after forming semiconductor elements such as a metal oxide semiconductor device (MOS) and a bipolar junction transistor (BJT) in an active device circuit, and then performing the process. The metallization process of the active component circuit completes the wafer level MEMS. The wafer is then diced into wafers (Die) and finally _ wafer packaged. In the fabrication of microelectromechanical structures, plasma etching methods such as reactive ion etching (RIE) are typically employed to form movable components or portions of the microelectromechanical structure. However, the profile of the microcomputer structure formed in the above manner is not ideal, and the equipment required for using reactive ion etching is expensive. In addition, after the formation of the microelectromechanical structure, particles or contaminants in the environment may fall into the microelectromechanical structure before wafer encapsulation, rendering the microelectromechanical structure inoperable. Therefore, there is a need for a new manufacturing method for MEMS structures that can improve the above problems. 201227873 SUMMARY OF THE INVENTION One object of the present invention is to provide a method of fabricating a microelectromechanical structure that can form three dimensions of capacitance in a microelectromechanical structure. Another object of the present invention is to provide a method of fabricating a microelectromechanical structure which can reduce the manufacturing cost of the microelectromechanical structure and form a good outline of the microelectromechanical structure. It is still another object of the present invention to provide a method of fabricating a microelectromechanical structure that can be packaged at the wafer level. According to an embodiment of the present invention, the manufacturing method includes the following steps: (a) forming a circuit layer on an upper surface of a first substrate, the circuit layer including a microstructure, a release feature, and a connection pad, wherein The release feature surrounds a portion of the periphery of the microstructure and extends through the circuit layer, and the release feature is made of a metal material, the connection pad is located on an outer surface of the circuit layer; (b) forming an anti-etching Laying on the circuit layer, wherein the release feature is exposed to the anti-etching layer; (c) removing the release feature by a wet etching process to expose the first substrate; (d) using an anisotropic An etching step of etching the exposed first substrate; (e) arranging a second substrate over the circuit layer, wherein a lower surface of the second substrate has a first metal layer and a second metal layer electrically connected to the first substrate a metal layer, wherein the first and second metal layers are respectively substantially aligned with the microstructure and the connection pad; (f) forming a hole through the first substrate, wherein the hole is substantially located at the connection (a) filling a polymer material in the hole; (h) removing a portion of the first substrate under the microstructure to release the microstructure; (1) arranging a third substrate at the first a lower surface of the substrate; (1) forming a connection hole from one side of the third substrate, wherein the connection hole penetrates the third substrate of the 201227873, the polymer material and the connection pad to expose the second metal layer and the Connecting a pad; and (k) forming a conductive layer in the connection hole to electrically connect the exposed connection pad and the exposed second metal layer. According to an embodiment of the invention, forming the circuit layer in the step (a) comprises forming a complementary metal oxide semiconductor structure electrically connected to the microstructure and the connection pad. In one embodiment, the release features are formed when the complementary metal oxide semiconductor structure is formed. According to an embodiment of the invention, the anti-etching layer of the step (b) comprises a layer of a oxidized stone layer and a layer of a layer of nitride. According to an embodiment of the invention, the above step (c) comprises applying an etchant comprising sulfuric acid and hydrogen peroxide. According to an embodiment of the invention, the anisotropic etching of the step (d) includes a reactive ion etching step and a deep reactive ion etching step. According to an embodiment of the present invention, the step (d) includes forming a recess in the first substrate, the recess having a depth of about 5 /im to about 60 // m °. According to an embodiment of the present invention, the step ( e) The distance between the first metal layer and the microstructure is from about 1 to about 50 //m. According to an embodiment of the invention, after the step (e) and before the step (f), the method further comprises: grinding the lower surface of the first substrate to reduce the thickness of the first substrate. [Embodiment] Please refer to Fig. 1, which is a top view of a microelectromechanical structure 6 201227873 according to an embodiment of the present invention. The microelectromechanical structure can be applied to a microelectromechanical inertial sensing device such as an accelerometer or a gyroscope. Fig. 1 is a diagram showing a microelectromechanical acceleration detector, but the manufacturing method disclosed in the present invention is applicable to other microelectromechanical devices, and is not limited to a microelectromechanical acceleration detector. As shown in FIG. 1, the microelectromechanical acceleration detector 100 mainly includes a movable microstructure 11A, a semiconductor circuit 12A, and a plurality of connection pads 130 and a circuit layer 140. The semiconductor circuit 120 is disposed substantially at the periphery of the movable micro-junction 110. The connection pads 130 are typically configurable on the periphery of the semiconductor circuit 120. The microstructures 110 are received in the recesses 142 of the circuit layer 140, and the microstructures include a central portion 112, at least one elastic support member 114, and at least one protrusion 116° elastic support member 114 connecting the central portion 112 and the circuit layer 140. And the center portion H2 is made movable. The projection 116 extends outwardly from the central portion 112 and forms a capacitance with another projection 144 extending from the substrate. The semiconductor circuit 120 is electrically connected to the protrusion 144 and the protrusion 116. The value of the capacitance between the two protrusions 116 and 144 is measured, and the measured voltage signal is converted into a voltage signal. The semiconductor circuit 12A can include a complementary metal oxide semiconductor device. The semiconductor circuit 12A can be electrically connected to an external circuit (not shown) via the connection pad 130. In operation, when the MEMS acceleration detector 1 is subjected to an acceleration, the distance between the protrusion 144 and the protrusion 116 changes, and the capacitance value therebetween changes. The semiconductor circuit 120 measures the amount of change in the capacitance value or the capacitance value described above, and estimates the acceleration received by the MEMS acceleration detector i (8). 201227873 The above-described microelectromechanical acceleration detector 100 is merely an illustrative example, to facilitate understanding of the present invention and the manufacturing method disclosed hereinafter, and the present invention is not limited to the fabrication of a microelectromechanical acceleration detector. In addition, the above-mentioned components and the connection relationships and relative relationships between the components are for illustrative purposes only and should not be construed as limiting the invention. Fig. 2 is a flow chart showing a method of manufacturing a microelectromechanical structure according to an embodiment of the present invention. 3A to 3H are cross-sectional views showing the respective manufacturing stages in the manufacturing method of an embodiment of the present invention. 3A to 3H are schematic cross-sectional views of line segment 3-3 in Fig. 1. Hereinafter, a method of manufacturing a microelectromechanical structure according to an embodiment of the present invention will be described in detail by taking a microelectromechanical structure in Fig. 1 as an example. The embodiments of the invention disclosed herein may be combined or substituted in the advantageous embodiments, and other embodiments may be added to an embodiment without further description or description. Step 201 is performed to form a circuit layer 320 on the first substrate 310 as shown in FIG. 3A. Circuit layer 32A includes microstructures 322, release features 324, connection pads 326, and dielectric material layer 328. Connection pad 326 is located
電路層320的外表面。釋放特徵結構324圍繞微結構322 一部分，且貫穿電路層32〇。釋放特徵結構 疋由金屬材料所製成，其在後續的製程中，將形 中的凹槽142的一部分。在一實施例t，第一基=第1圖 例如為矽晶圓，連接墊320為金屬所製成。土 可 在一實施例中，形成電路層320的步驟包含 補式金屬氧化物半導體(CM0S)結構33〇。在習二^成—互 結構330的標準製程中，可包括4道的金屬化 道的多晶矽化製程(4M2P製程），亦可包括5道二以及2 的金屬化製 201227873 ::及2的多晶矽化製程(5M1P製程)。因此，在-實施 ，同吐成CM〇S結構330的過程中，藉由適當設計的 你丨~ Μ 5、^成釋放特徵結構324。以上僅以CMOS為舉 類:結構發明，其他例如_〇S結構或 心本發明。此外，本發明亦不限於彻p 2 lp製程，其他的製程方式亦可適用於本發明。 預1 =成CM〇S結構的通孔時’可同時移除介電層中 放特徵結構324位置的介電材料。職，在形成 、，構的金屬層時，刊時填充金屬材料至上述預設 放❹^此’可以在形成復08結構330日寺，逐步形成釋 =、、·。構324。在另一實施例中，形成金屬氧化物半導 壯、、’。構330的金屬層係為鋁，而填充在金屬氧化物半導體 A^33G中通孔的金屬為鶴。因此，可形成由㉟及鶴所構 釋放特徵結構324。在又一實施例中，CM〇s結構33〇 二接連接塾326以及微結構322，連接塾326為金屬 /在一實施例中’在形成CMOS結構330的過程中，同 時形成微結構322。請同時參照第1圖，微結構322可包 括中心部112、彈性支撐件114、以及凸出物116。於形成 CMOS結構33〇的過程中可以同時形成中心部U2、彈性 支撐件114、以及凸出物116。換言之，微結構322是由與 CM〇S結構330相同的材料(例如鋁及/或鎢）所堆疊而成， 因此’中心部112、凸出物116及彈性支撐件114中具有金 屬層的結構。此外，由電路層140延伸出的凸出物144以 及其他微機電結構中的金屬連接線也可以在形成CM〇s結 201227873 f 330的過程中同時被形成。凸出物⑷中的金屬層電性 f接半導體電路120。凸出物U6中的金屬層可經由中心 :12广的金屬層電性連接至彈性支撐件114内的金屬 :然後在連接至半導體電路12()。因此，在凸出物⑷ 與凸出物m之間形成電容。在另—實施例中，如第3A圖 微結構322包括與金屬氧化物半導體結構33〇相同 ' ”電材料323(例如氧化矽及/或氮化矽），且介電材料323 ，在微結構322的外侧表面。介電材料323的厚度可為約 卢1 "m至約3 例如為約！ “m、2 "爪或3㈣。 在另一實施例中，微結構322電性連接連接墊326。 在步驟202中，形成抗蝕刻層34〇於電路層32〇上， =3A圖所示。釋放特徵結構似露出於抗㈣層· ’ 二’抗㈣層34G不覆蓋釋放特徵結構324,以便進 二：步驟。在一實施例中，抗蝕刻層可為例如氧化矽層 姓二化^層’或抗姓刻層可為包含氧化石夕及氮化石夕的多層 i術：層可利用習知的化學氣相沈積技術或其他的 d 實施例中’抗敍刻層340可覆蓋連接墊 ，如第3A圖所示。 324，以^ 藉由濕㈣製程移除釋放特徵結構 徵社構310 ’如第3B圖所示。移除釋放特 324後，微結構322可與電路層320的其他部分之The outer surface of circuit layer 320. The release feature 324 surrounds a portion of the microstructure 322 and extends through the circuit layer 32A. The release feature is made of a metallic material that will form a portion of the recess 142 in a subsequent process. In an embodiment t, the first base = Fig. 1 is, for example, a germanium wafer, and the connection pad 320 is made of metal. Soil In one embodiment, the step of forming circuit layer 320 includes a complementary metal oxide semiconductor (CMOS) structure 33A. In the standard process of Xi 2 - Interstructure 330, it can include 4 channels of metallization polysiliconization process (4M2P process), and can also include 5 channels 2 and 2 metallization 201227873:: and 2 polysilicon Process (5M1P process). Therefore, in the process of performing the same process as the CM〇S structure 330, the feature structure 324 is released by appropriately designing the 丨~Μ5. The above is only in the CMOS category: structural inventions, others such as the _〇S structure or the present invention. Furthermore, the present invention is not limited to the full p 2 lp process, and other process modes are also applicable to the present invention. Pre 1 = a through hole in the CM 〇 S structure' can simultaneously remove the dielectric material in the dielectric layer at the location of the feature 324. In the formation, the metal layer of the structure, the time to fill the metal material to the above-mentioned preset ❹ ^ this can be formed in the complex 08 structure 330 temple, gradually formed release =,, ·. Structure 324. In another embodiment, the metal oxide is semiconducting, '. The metal layer of the structure 330 is aluminum, and the metal filled in the through holes of the metal oxide semiconductor A^33G is a crane. Thus, the feature 324 can be formed by 35 and the crane. In yet another embodiment, the CM 〇 s structure 33 〇 connects the 塾 326 and the microstructure 322, and the connection 塾 326 is metal / in an embodiment </ RTI> in the process of forming the CMOS structure 330, while forming the microstructure 322. Referring also to Figure 1, the microstructure 322 can include a central portion 112, an elastic support member 114, and a projection 116. The central portion U2, the elastic support member 114, and the projections 116 may be simultaneously formed in the process of forming the CMOS structure 33A. In other words, the microstructures 322 are stacked from the same material as the CM〇S structure 330 (for example, aluminum and/or tungsten), so that the central portion 112, the protrusions 116, and the elastic support member 114 have a metal layer structure. . In addition, the protrusions 144 extending from the circuit layer 140 and the metal lines in other microelectromechanical structures can also be formed simultaneously during the formation of the CM 〇s junction 201227873 f 330. The metal layer in the protrusion (4) is electrically connected to the semiconductor circuit 120. The metal layer in the protrusion U6 can be electrically connected to the metal in the elastic support 114 via a central: 12 wide metal layer: then connected to the semiconductor circuit 12(). Therefore, a capacitance is formed between the protrusion (4) and the protrusion m. In another embodiment, the microstructure 322 as in FIG. 3A includes the same ' ” electrical material 323 as the metal oxide semiconductor structure 33 ( (eg, yttrium oxide and/or tantalum nitride), and the dielectric material 323 is in the microstructure. The outer surface of the 322. The thickness of the dielectric material 323 may range from about 1 lux to about 3, for example, about "m, 2 " claws or 3 (four). In another embodiment, the microstructures 322 are electrically connected to the connection pads 326. In step 202, an anti-etching layer 34 is formed on the circuit layer 32A, as shown in the =3A diagram. The release feature appears to be exposed to the anti-(four) layer. The 'two' anti-(four) layer 34G does not cover the release feature 324 for the second step. In an embodiment, the anti-etching layer may be, for example, a ruthenium oxide layer, or an anti-surname layer, which may be a multi-layered process comprising an oxidized stone and a nitrite: the layer may utilize a conventional chemical vapor phase. The deposition technique or other d embodiment can be used to cover the connection pads as shown in Figure 3A. 324, by removing the release feature by the wet (four) process, the structure 310' is as shown in FIG. 3B. After the release feature 324 is removed, the microstructure 322 can be associated with other portions of the circuit layer 320.
mU隙"。在一實施例中’間隙廿之寬度為約U 所採，例如可為2㈣或3心。在步驟2〇3中， *高於二材:與氧化物材料(或氮化物)具 ㈣刻選擇比，例如尚於15: i或高於2〇: i，例如 201227873 成更同因此，在移除釋放 可以得到較佳的側壁輪廓 恨口構324子 324 在實施例中，釋放特徵結構 製程ί =抗峨340為氧化㈣。_刻 Μ使用-包含硫酸以及過氧化氫之 :例中’硫酸與過氧化氣的重量比為約2:ι丄= 324的金屬材料時，可以得到滿意的侧壁輪廓。 二：例I，移除釋放特徵結構324後，可形成如第1 圖繪不的凹槽142的一部分。 .在習知的技術中’通常採用反應性離子蝕亥― ⑽etchlng，RIE)移除電路層中的介電材料（諸如氧化 以形成第1圖繪示的凹槽142。但是使用反應^ J，所形成的蝕刻側壁輪廓並不理想。而且， ，離子蝕刻所需得設備昂貴。但是若採用一般的濕蝕刻J 程，直接蝕刻電路層中的介電材料，因濕蝕刻本質上為 向性蝕刻，报難得到理想的蝕刻側壁輪廓。因此，根據 發明一實施例，係在所欲移除的區域中預先填入金屬^ 料姓形成釋放特徵結構324。然後再利用濕蝕刻將釋效= 徵結構324移除。藉由使用具有高蝕刻選擇比的蝕刻劑、 可以達到更佳的蝕刻側壁輪廓（相較於反應離子蝕刻）。 者’釋放特徵結構324可在形成電路層320的同時形成再 無須額外製程。所以，本發明具有低製程成本的優點’， 能達到更佳的蝕刻輪廓。 且 在步驟204中，非等向性蝕刻露出的第一基板31〇， 如第3C圖所示。在一實施例中，非等向性蝕刻包括—深式 反應離子餘刻（Deep Ion reactive Etching, DRIE)步驟。在另 201227873 一實施例中，非等向性蝕刻第一基板31〇的步驟包括形成 一凹陷部314於第一基板31〇中，且凹陷部314之深度為 約5 "m至約60 ym，例如為約2〇 "m、3〇 #m、4〇 " m或50以m。在又一實施例中，凹陷部314可形成如第j 圖繪示之凹槽142的一部分。在非等向性蝕刻過程中，抗 蝕刻層340(例如氧化矽或氮化矽等）可保護其下的金屬層 (例如連接墊326及電路層320中的金屬層），避免在非等 向性蝕刻過程中破壞金屬層應有的電性。 在步驟203所述移除釋放特徵結構324後，在某些情 况下’所露出的第一基板310的上表面（即間隙d的位置) 可忐形成氧化物，例如氧化矽。因此，在進行步驟2〇4之 刖，可非必要性地進行一 RIE製程，以移除間隙d内第一 基板310表面上的氧化物。隨後，再進行步驟2〇4以蝕刻 第一基板310。 在步驟205中，配置第二基板350於電路層320上方， 如第313圖所不。第二基板350的下表面351具有第一金 屬層354以及第二金屬層356，且第-金屬層354以及第 金屬s 356電性連接。第一金屬層以及第二金屬層 356刀別大致對準微結構322以及連接墊326。在一實施例 中L第一金屬層354與第二金屬層356為同一層的金屬層， 換言之’第一金屬層354與第二金屬層356係同時形成。 在其他實施例中’第—金屬層354可與第二金屬層3%為 不相同的金屬層’亦即第-金屬層354 與第二金屬層356 並非同時形成。第一金屬層354與微結構322之間的垂直 間距為約1 _至約5〇 /im，例如可為約1G #m、20 //mU gap ". In one embodiment, the width of the gap 为 is about U, for example, 2 (four) or 3 hearts. In step 2〇3, * is higher than the two materials: with the oxide material (or nitride) with a (four) selection ratio, such as still 15: i or higher than 2〇: i, such as 201227873, so Removal of the release results in a preferred sidewall profile hatch 324 sub-324. In an embodiment, the release feature process ί = anti-峨 340 is oxidized (d). _ Μ Use - Contains sulfuric acid and hydrogen peroxide: In the case where the weight ratio of sulfuric acid to peroxygen gas is about 2: ι = 324, a satisfactory sidewall profile can be obtained. Two: Example I, after removing the release feature 324, a portion of the recess 142 as depicted in FIG. 1 can be formed. In the prior art, the dielectric material in the circuit layer (such as oxidation is formed to form the recess 142 shown in Fig. 1) is usually removed by reactive ion etching (RIE), but the reaction is used. The resulting etched sidewall profile is not ideal. Moreover, the equipment required for ion etching is expensive. However, if a general wet etch process is used, the dielectric material in the circuit layer is directly etched, which is essentially etched by wet etching. It is difficult to obtain an ideal etched sidewall profile. Therefore, according to an embodiment of the invention, the metal feature is pre-filled in the region to be removed to form a release feature 324. The wet etching is then used to release the effect = sign Structure 324 is removed. By using an etchant having a high etch selectivity, a better etched sidewall profile can be achieved (compared to reactive ion etch). The 'release feature 324 can be formed while forming circuit layer 320. No additional process is required. Therefore, the present invention has the advantage of low process cost', and a better etching profile can be achieved. And in step 204, the first substrate 31 is exposed by anisotropic etching. As shown in Fig. 3C. In one embodiment, the anisotropic etch includes a Deep Ion reactive Etching (DRIE) step. In another embodiment of 201227873, anisotropic etching The step of the first substrate 31〇 includes forming a recess 314 in the first substrate 31〇, and the depth of the recess 314 is about 5 "m to about 60 ym, for example, about 2 〇"m, 3〇# m, 4 〇 " m or 50 in m. In still another embodiment, the recess 314 may form a portion of the recess 142 as depicted in Figure j. During the anisotropic etching process, the anti-etching layer 340 (such as tantalum oxide or tantalum nitride, etc.) can protect the underlying metal layer (such as the connection pad 326 and the metal layer in the circuit layer 320) to avoid damaging the electrical properties of the metal layer during the anisotropic etching process. After the release feature 324 is removed as described in step 203, in some cases the exposed upper surface of the first substrate 310 (i.e., the location of the gap d) may form an oxide, such as hafnium oxide. After step 2〇4, an RIE process may be performed non-essentially to remove the first gap in the gap d The oxide on the surface of the substrate 310. Subsequently, step 2〇4 is performed to etch the first substrate 310. In step 205, the second substrate 350 is disposed over the circuit layer 320, as shown in Fig. 313. The second substrate 350 The lower surface 351 has a first metal layer 354 and a second metal layer 356, and the first metal layer 354 and the metal s 356 are electrically connected. The first metal layer and the second metal layer 356 are substantially aligned with the microstructure 322. And the connection pad 326. In one embodiment, the first metal layer 354 and the second metal layer 356 are the same metal layer. In other words, the first metal layer 354 and the second metal layer 356 are simultaneously formed. In other embodiments, the metal layer 354 may be different from the second metal layer 3%, that is, the first metal layer 354 and the second metal layer 356 are not formed at the same time. The vertical spacing between the first metal layer 354 and the microstructure 322 is from about 1 _ to about 5 〇 /im, for example, about 1G #m, 20 //
12 201227873 m、30 或40//m。因此，第一金屬層354與微結構322 中的金屬層可形成電容結構。 承上所述，第二基板350作為第一及第二金屬層354、 356的載板’並用以保護微結構322及避免環境中的微粒 掉落至凹陷部314。在一實施例中，第二基板350可例如 為玻璃基板或一矽基材，玻璃基板或矽基材的厚度為約5〇12 201227873 m, 30 or 40//m. Thus, the first metal layer 354 and the metal layer in the microstructure 322 can form a capacitive structure. As described above, the second substrate 350 acts as a carrier plate for the first and second metal layers 354, 356 and serves to protect the microstructures 322 and to prevent particles in the environment from falling to the recesses 314. In one embodiment, the second substrate 350 can be, for example, a glass substrate or a substrate having a thickness of about 5 Å.
A m 至約 900 " m，例如為 1〇〇 以 m、200、300 " m 或 400以m。在另一實施例中，第二基板mo與抗蝕刻層34〇 之間可配置黏著層352，用以固定第二基板350。 在步驟205之後，可非必要性地進行步驟206。在步 驟206中，研磨第一基板310的下表面316，以減少第— 基板310的厚度，如第3E圖所示。具體而言，第一基板 研磨後的厚度可為約50微米至微米300微米。 在步驟207中，形成一孔洞510貫穿第一基板31〇， 如第3F圖所示。孔洞510大致位於連接墊326下方，藉此 將位於連接墊326下方的電路層320露出。形成孔洞"51〇 的方法可為乾蝕刻法、濕蝕刻法、機械鑽孔或雷射鑽孔。 在一實施例中，孔洞510具有一傾斜的側壁512。側壁 與電路層320的下表面514形成一大於90度的夾角β，2 如可為約100度、110度、120度、140度或150度。^ 在步驟208中，填充一高分子材料520於孔洞5l〇中 如第3G圖示。在一實施例中，高分子材料52〇可為缳’ 樹脂(epoxy)。在另一實施例中，所填充的高分子材料1氣 表面大致與第一基板310的下表面316齊平。 〇 在步驟209中，移除位於微結構322下方的第 13 201227873 的-部分，以釋敌微結構322,如第3H圖所示 結：」是指讓微結構能夠相對於其他構件而發生 相對移動。在一實施例中，藉由臟製程移除位於凹陷 部314及微結構功下方的第一基板3U)的—部分於= 結構322能相對於第一基板31〇、介電材料328二第= 板350產生位移。在另一實施例中，微結構切藉由如第 1圖所不之彈性支撐件1H而連接於電路層咖的盆他部 分。因此’當微結構322受外力時，可產生微小的相對位 移。A m to about 900 " m, for example, 1 〇〇 in m, 200, 300 " m or 400 in m. In another embodiment, an adhesive layer 352 may be disposed between the second substrate mo and the anti-etching layer 34A for fixing the second substrate 350. After step 205, step 206 may be performed non-essentially. In step 206, the lower surface 316 of the first substrate 310 is ground to reduce the thickness of the first substrate 310, as shown in Fig. 3E. Specifically, the thickness of the first substrate after grinding may be from about 50 microns to 300 microns. In step 207, a hole 510 is formed through the first substrate 31, as shown in FIG. 3F. The hole 510 is located substantially below the connection pad 326, thereby exposing the circuit layer 320 under the connection pad 326. The method of forming the hole "51〇 can be dry etching, wet etching, mechanical drilling or laser drilling. In an embodiment, the aperture 510 has a sloped sidewall 512. The sidewalls form an included angle β greater than 90 degrees with the lower surface 514 of the circuit layer 320, such as may be about 100 degrees, 110 degrees, 120 degrees, 140 degrees, or 150 degrees. ^ In step 208, a polymer material 520 is filled in the hole 5l, as shown in Fig. 3G. In one embodiment, the polymeric material 52A may be an oxime' epoxy. In another embodiment, the filled polymeric material 1 gas surface is substantially flush with the lower surface 316 of the first substrate 310.步骤 In step 209, the portion of the 13th 201227873 located below the microstructure 322 is removed to release the enemy microstructure 322, as shown in FIG. 3H:" means that the microstructure can be relatively relative to other components. mobile. In one embodiment, the portion of the first substrate 3U that is located under the recess 314 and under the microstructure function is removed by a dirty process. The structure 322 can be opposite to the first substrate 31 and the dielectric material 328. Plate 350 produces displacement. In another embodiment, the microstructure cut is attached to the pot portion of the circuit layer by an elastic support 1H as shown in Fig. 1. Therefore, when the microstructure 322 is subjected to an external force, a slight relative displacement can be generated.
在步驟210中，配置第三基板53〇於第一基板3丨〇的 下方，如第31圖所示。在一實施例中，第三基板53〇可與 第二基板350為相同材料，例如為矽基材或玻璃基板。第 一基板350及第二基板530形成一包圍微結構322的封閉 空間。因此，第二基板350及第三基板530可保護微結構 322免於受損及防止微粒進入，而確保微結構322正常運 作。 在步驟211中，由第三基板530之一側形成連接孔 540 ’如第3J圖所示。連接孔540大致位於填充高分子材 料520之處，且貫穿第三基板530、高分子材料520、電路 層320、連接墊326以及抗蝕刻層340，而露出第二金屬層 356以及連接墊326。形成連接孔540的方法可為機械鑽孔 或雷射鑽孔等。 步驟212中，形成導電層550於連接孔540中，而形 成微機電結構500，如第3K圖所示。導電層550將連接墊 326與第二金屬層356相連接。因此，可經由導電層550 14 201227873 傳輸電子訊號進入連接墊326以及第二金屬層356。在一 實施方式中，電子訊號可以經由第二金屬層356傳遞至第 一金屬層354。另一方面，電子訊號也可以經由連接墊326 傳遞微結構322及/或電路層320中的CMOS結構330。因 此，可以在微結構322與第一金屬層354之間形成一垂直 方向的電容。同時，可利用第1圖所繪示之實施方式，在 凸出物144與凸出物116之間形成另一電容。因此，根據 本發明之一實施方式，此微機電結構500能夠量測三個維 度的加速度變化。完成步驟212，即完成晶圓層級的微機 電結構封裝。 上述導電層550可利用一般習知的濺鍍製程形成，導 電層550的材料可例如為銅、錫、鋁、銀或鎢。在一實施 例中’導電層550由連接孔540延伸至第三基板530的下 表面532，且可非必要性地形成連接凸塊560於導電層550 上，如第3L圖所示。連接凸塊56〇用以提供微機電結構 500與外部電路之連接。連接凸塊560可使用任何習知的 方法形成，例如網印製程或佈植錫球方式等。 一雖然本發明已以實施方式揭露如上，然其並非用以限 =本發明’任何熟習此技藝者’在不脫離本發明之精神和 範圍内’當可作各種之更動與潤飾，因此本發明之保護範 園當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖係繪示本發明一實施例之微機電結構的上視 圖0 15 201227873 第2圖係繪示本發明一實施方式之微機電結構之製造 方法的流程圖。 第3A圖至3L圖係繪示本發明一實施方式之製造方法 中各製程階段的剖面示意圖。 【主要元件符號說明】 100微機電加速度偵測器 110微結構 112中心部 114彈性支撐件 116凸出物 120半導體電路 130連接墊 140基材 142凹槽 144凸出物 201,202, 203, 204, 205, 206 步驟 207, 208, 209,210, 211，212 步驟 300微機電結構 310第一基板 312上表面 314凹陷部 316下表面 320電路層 16 201227873 322微結構 323介電材料 324釋放特徵結構 326連接墊 328介電材料層 330互補式金屬氧化物半導體結構 340抗钱刻層 350第二基板 351下表面 352黏著層 354第一金屬層 356第二金屬層 500微機電結構 510孔洞 512側壁 514下表面 520高分子材料 530第三基板 532下表面 540連接孔 550導電層 560連接凸塊 d間隙 Θ夾角In step 210, the third substrate 53 is disposed below the first substrate 3'', as shown in FIG. In one embodiment, the third substrate 53A may be the same material as the second substrate 350, such as a tantalum substrate or a glass substrate. The first substrate 350 and the second substrate 530 form an enclosed space surrounding the microstructures 322. Therefore, the second substrate 350 and the third substrate 530 can protect the microstructure 322 from damage and prevent the entry of particles, and ensure that the microstructure 322 operates normally. In step 211, a connection hole 540' is formed from one side of the third substrate 530 as shown in Fig. 3J. The connection hole 540 is located substantially at the place where the polymer material 520 is filled, and penetrates the third substrate 530, the polymer material 520, the circuit layer 320, the connection pad 326, and the anti-etching layer 340 to expose the second metal layer 356 and the connection pad 326. The method of forming the connection hole 540 may be mechanical drilling or laser drilling or the like. In step 212, a conductive layer 550 is formed in the connection hole 540 to form a microelectromechanical structure 500, as shown in Fig. 3K. Conductive layer 550 connects connection pads 326 to second metal layer 356. Therefore, the electronic signal can be transmitted to the connection pad 326 and the second metal layer 356 via the conductive layer 550 14 201227873. In one embodiment, the electronic signal can be transferred to the first metal layer 354 via the second metal layer 356. Alternatively, the electronic signal can also pass the microstructure 322 and/or the CMOS structure 330 in the circuit layer 320 via the connection pads 326. Therefore, a vertical capacitance can be formed between the microstructure 322 and the first metal layer 354. At the same time, another embodiment can be used to form another capacitance between the protrusions 144 and the protrusions 116 using the embodiment illustrated in FIG. Thus, in accordance with an embodiment of the present invention, the microelectromechanical structure 500 is capable of measuring acceleration changes in three dimensions. Upon completion of step 212, the wafer level micro-computer electrical structure package is completed. The conductive layer 550 may be formed by a conventional sputtering process, and the material of the conductive layer 550 may be, for example, copper, tin, aluminum, silver or tungsten. In one embodiment, the conductive layer 550 extends from the connection hole 540 to the lower surface 532 of the third substrate 530, and the connection bump 560 may be formed non-essentially on the conductive layer 550 as shown in Fig. 3L. Connection bumps 56 are used to provide connection of the microelectromechanical structure 500 to external circuitry. The connection bumps 560 can be formed using any conventional method, such as a screen printing process or a solder ball method. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention to the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The protection of Fan Park shall be subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top view of a microelectromechanical structure according to an embodiment of the present invention. FIG. 15 15 201227873 FIG. 2 is a flow chart showing a method of fabricating a microelectromechanical structure according to an embodiment of the present invention. 3A to 3L are schematic cross-sectional views showing respective process stages in the manufacturing method of an embodiment of the present invention. [Main component symbol description] 100 MEMS acceleration detector 110 microstructure 112 center portion 114 elastic support member 116 protrusion 120 semiconductor circuit 130 connection pad 140 substrate 142 groove 144 protrusions 201, 202, 203, 204, 205 206 Steps 207, 208, 209, 210, 211, 212 Step 300 Microelectromechanical structure 310 First substrate 312 Upper surface 314 Depression 316 Lower surface 320 Circuit layer 16 201227873 322 Microstructure 323 Dielectric material 324 Release feature 326 Connection pad 328 Dielectric material layer 330 complementary metal oxide semiconductor structure 340 anti-etched layer 350 second substrate 351 lower surface 352 adhesive layer 354 first metal layer 356 second metal layer 500 microelectromechanical structure 510 hole 512 side wall 514 lower surface 520 high Molecular material 530 third substrate 532 lower surface 540 connection hole 550 conductive layer 560 connection bump d gap Θ angle