TWI476891B - Technique for interconnecting integrated circuits - Google Patents

Description

Technology for interconnecting integrated circuits

This application relates to integrated circuits, and more particularly to interconnected integrated circuits.

This application was filed in the United States as a patent application No. 12/267,725 on November 10, 2008.

There are many reasons for interconnecting more than one integrated circuit die to form a single packaged device. One use adds memory for a given package. Another use system combination is typically used together, but it is difficult to utilize two dies that are manufactured for one of the two effective processing procedures. An example is for one of the logic circuits of a mobile phone and an RF circuit. Sometimes there are interconnection problems or interference problems that must be solved. In summary, there are sometimes problems that need to be addressed due to the specific combination of grains being implemented. Regardless of the reason for the combination of multiple crystal grains, there is a problem caused in order to overcome the fact that there is a need for one of the multiple crystal grains. The ability to combine multiple functionalities on a single die is still limited, so the problems associated with multiple grains continue to exist.

Therefore, there is a need for an improved technique for interconnecting multiple dies.

The invention is illustrated by way of example and not by the accompanying drawings, For the sake of simplicity and clarity, the elements in the drawings are illustrated and are not necessarily drawn to scale.

In one aspect, two integrated circuit dies (each of which has a processing core and an on-board memory) are interconnected and packaged together to form a multi-chip module. The first die is considered to be predominant and the second die is considered to be secondary. They are connected together via an intermediate substrate. The first and second dies may be of the same design and thus have the same resources (such as peripherals and memory) and preferably have a common system interconnection protocol. The core of the second die is deactivated or placed in a reduced power mode during most of the operation as needed. The first die includes a minimum circuit for interconnecting to the second die. The second die has at least some desired interface circuitry and an address translator. The result is that the memory and other resources are generally on the first die, and the core of the first die can be in transactions with the memory and other resources of the second integrated circuit. This is especially beneficial when used as a prototype. After testing with the prototype, we finally felt that the various features we wanted could easily be included in one of the individual grains used in mass production. Therefore, if the design of the mass production device can be completed after the prototype test is completed, the feature optimization for mass production will be more suitable and timely. This is good for early software development and product prototype building. This can be better understood with reference to the drawings and the description below.

Illustrated in FIG. 1 is a package device 10 that includes an integrated circuit die 12, an integrated circuit die 14 and an intermediate substrate 16. The integrated circuit 12 includes a system interconnect 18, a core 20, a DMA 22, a main control circuit 24, a configuration register 26, a peripheral device 28, a non-volatile memory (NVM) 30, and a A static random access memory (SRAM) 32, a slave circuit 34, a decoder 36, an external terminal 38, an external terminal 40, an external terminal 42, and an external terminal 44. The integrated circuit 14 includes a system interconnection 46, a core 48, a DMA 50, a main control circuit 52, a decoder 54, a configuration register 56, a peripheral device 58, an NVM 60, and an SRAM 62. A slave circuit 64, an external terminal 66, an external terminal 68, an external terminal 70 and an external terminal 72. In this example, the integrated circuit dies 12 and 14 are of the same design. Although system interconnects 18 and 46 are identical, it is preferred that system interconnects 18 and 46 have the same protocol. An example of such a system interconnect is a crossbar system interconnect. This system is a good example because it is relatively simple to add resources to the crossbar system. Cores 20 and 48 function as processing units and are each connected to system interconnects 18 and 46. In this example, the die 12 is a master die-like primary die and the die 14 is a slave-like secondary die. Peripheral devices 28 and 58 can be a wide variety of functional circuits. An example is an analog to digital converter. The external terminals are for direct external connection to the die, and the external terminals are part of the die.

With respect to die 12, system interconnect 18 is coupled to core 20 at one of system interconnects 21 of system interconnect 18, and interconnected to DMA 22 at one of system interconnects 23, at system interconnect 18 One of the masters 25 is interconnected to the master circuit 24, interconnected to the configuration register 26 at one of the system interconnects 18, and interconnected at one of the system interconnects 18 To the peripheral device 28, to the NVM 30 at one of the system interconnects 18, to the SRAM 32 at one of the system interconnects 18, and to the slave 埠35 at one of the system interconnects 18 Slave circuit 34. Main control circuit 52 is coupled to external terminals 66 and 68 that are not externally connected to die 12 in this example. For clarity of function, the configuration register 26 is shown as being directly connected to the decoder 36, but the configuration register 26 is actually connected to the decoder 36 via the system interconnect 18. The external terminal 42 is connected to the slave circuit 34 and to the intermediate substrate 16. The external terminal 44 is connected to the configuration register 26 and the intermediate substrate 16. A slave circuit 34 is used to connect to the secondary die. The main control circuit 24 is connected to the core 20. The intermediate substrate 16 is used to connect the dies 12 and 14 together in both electrical and structural terms. The resources connected to the upper portion of system interconnect 18 are connected to the master and the resources on the lower portion of system interconnect 18 are connected to the slave. Thus, core 20, DMA 22, and master control circuit 24 are communicatively coupled to system interconnect 18 at the master control port. Peripheral device 28, NVM 30, SRAM 32, slave circuitry 34, and configuration register 26 are communicatively coupled to system interconnect 18 at the slave. It is well known in the art to have a microcontroller divided into system interconnects having slaves and masters.

With respect to die 14, system interconnect 46 is coupled to core 48, DMA 50, master circuit 52, decoder 54, configuration register 56, peripheral device 58, NVM 60, SRAM 62, slave circuit 64. Main control circuit 52 is connected to external terminals 66 and 68. The external terminals 66 and 68 are connected to the intermediate substrate 16. For clarity of function, the decoder 54 is shown as being directly connected to the configuration register 56, but the decoder 54 is actually connected to the configuration register 56 via the system interconnect 46. The configuration register 56 is connected to the external terminal 70. The slave circuit 64 is connected to the external terminal 72. External terminals 70 and 72 are not connected to circuitry external to die 14. The slave circuit 34 and the configuration register 26 connected to the master circuit 52 via the intermediate substrate 16 establish the die 12 as primary and establish the die 14 as secondary. Core 48, DMA 50, master control circuitry 52 are communicatively coupled to system interconnect 18 at the master control port. Peripheral device 58, NVM 60, SRAM 62, slave circuit 64, and configuration register 56 are communicatively coupled to system interconnect 18 at the slave.

In operation, core 20 has access to resources connected to system interconnect 18 and peripheral devices 58, NVM 60, and SRAM 62 that are accessible to system interconnect 46. The decoder 36 decodes the system interconnect to load the control information that the external terminal 44 provides the primary information of the die 12 into the configuration register. The control information is received by the external terminal 68 via the intermediate substrate 16 and is thus received by the master control circuit 52 as a configuration signal C. The master control circuit 52 is for receiving a transaction request from the primary die that is the master. The slave circuit 34 controls the transaction T with the master circuit 52 via the intermediate substrate 16 and the external terminal 66. For example, if core 20 chooses to access SRAM 62, the transaction is communicated to slave circuit 34 via system interconnect 18. The slave circuit communicates the transaction T to the master control circuit 52. The master control circuit 52 then performs the transaction with respect to the SRAM 62 via the system interconnect 46. The transaction master control circuit 52 communicates back to the slave circuit 34 and uses the system interconnect 18 to communicate from the slave circuit 34 to the core 20. This is further explained with reference to FIG. 2.

One portion of the device 10 is shown in more detail in FIG. 2 and also shown in FIG. 1 are system interconnect 18, slave circuit 34, configuration register 26, intermediate substrate 16, main control circuit 52, system interconnect 46, core 48 and external terminal 42, 44, 66 and 68. Slave circuit 34 includes slave logic 74 and a communication handshake circuit 76. Slave logic 74 is coupled to system interconnect 18 via a first interface and to communication handshake circuit 76 via a second interface. The main control circuit 52 includes a communication handshake circuit 78, an address translation circuit 80, and a master control logic 82. The communication handshake circuit 78 is coupled to the external terminal 66 via a first interface and to the address translation circuit 80 via a second interface. The master logic 82 is coupled to the address translation circuitry 80 via a first interface and to the system interconnect via a second interface. The address translation circuitry and core 48 are coupled to the configuration register 26 via external terminals 68 and 44. Dependent logic 74 interfaces with system interconnect 18 to know what transactions are to be performed with die 14, and to couple necessary information (such as address and data) while a transaction is being executed. The communication handshake circuit 76 communicates with the communication handshake circuit 78 such that the signals between them are timely and synchronized.

The core 20 has accessed the resources connected to the system interconnect 46, and thus the core 20 has doubled the resources for its processing. In the case of adding memory (such as NVM 60 and SRAM 62), integrated circuit 12 must also be able to increase the corresponding bit compared to the address space required to use only the memory connected to system interconnect 18. Address space. This is rarely a problem because the amount of memory on a microcontroller's onboard system is much less than the addressability of the core. Core 20 is expected to have an addressing capability of at least 32 bits and possibly 64 bits or even 128 bits. Even with a low addressability of only 32 bits, the number of address addresses that can be addressed exceeds four billion. If there is a tuple in each address, it will have the ability to address more than four billion gigabytes of memory. However, at the same time, the address space of the memory in the integrated circuit 14 is the same as the address space of the memory in the integrated circuit 12. Thus, in order to process the memory of the integrated circuit 14 as additional memory, when the core 20 is addressing the memory of the integrated circuit 14, there must be an address translation. This is illustrated in Figure 3. Thus the primary memory (the memory of the primary memory system in the primary microcontroller, ie, the integrated circuit 12 in this example) occupies one of the first address ranges within the address mapping, and the secondary The memory (the memory of the secondary memory system in the secondary microcontroller, i.e., the integrated circuit 14 in this example) occupies one of the second address ranges within the address map. As illustrated in Figure 3, this same methodology is equally applicable to the use of such peripheral devices. In the case where one of the resources of the integrated circuit 14 is processed as a copy resource to the resource of the integrated circuit 12, no translation is required.

When a resource (such as SRAM 62) on the secondary die is treated as a copy resource, the resource replaces the same resource SRAM 32 on the primary die. In operation, core 20 will access the address space associated with SRAM 32 across system interconnect 18, however the access will be transferred via slave 1 circuit 34, intermediate substrate 16, master 2 circuit 52, and system interconnect 46. To SRAM 62. In this operation, address translation is not required, but the address decoding logic associated with SRAM 32 is disabled.

For an example of operation, if one address for a write will eventually be communicated to SRAM 62, then communication handshake circuit 78 must be ready to receive the address. Under the control of the configuration register 26, the address translation 80 performs the necessary translation. In this example in which the die 12 and the die 14 are identically designed, the memory space (such as NVM 60 or SRAM 62) of the die 14 that is allocated by the decoder 36 for the memory is different from the memory identified by the die 14. Body space. Therefore, a translation is required. The register 26 is configured to communicate the translations needed. The address translation circuit 80 therefore performs the translations commanded by the configuration register 26. Master logic 82 receives the translated address from address translation circuitry 80 and the master logic 82 negotiates with system interconnect 46 to execute the commanded transaction. Under the command of the configuration register 26, the core 48 is placed in a lower power mode. During startup, core 48 may be active, but after completion of startup, core 48 may drop power to conserve power. In this example, the translation is performed by the secondary die, but the translation may instead be performed by the primary die. As depicted in FIG. 2, address translation circuitry 80 can be moved between slave logic 74 and communication handshake 76.

In the case where die 14 provides information back to die 12, master logic 82 receives information from system interconnect 46 and couples the information to address translation circuitry 80. Under the command of the configuration register 26, the address translation circuit 80 performs any required translations. The communication handshake circuit is coordinated with the handshake circuit 76 to properly communicate the information to the logic 74. Logic 74 then negotiates with the system interconnect to cause the information to reach core 20 via the system interconnect.

This operation allows core 20 to use resources connected to die 14 of system interconnect 46. As such, a variety of experiments can be run to determine the optimal combination of resources for one of the next generation of integrated circuits. Since it is possible and possible to improve the manufacturing capability by running the experiment with the existing integrated circuit, it is desirable to shorten the time to market for an integrated circuit having a new combination of such resources.

Illustrated in FIG. 4 is a device 10 completed in one of the cross-sectional illustrations showing the dies 12 and 14 coupled to one another via an intermediate substrate 16 and using a sealant such as a molding compound such as a phenolic ring. Oxygen resin)) The device 10 is sealed. For ease of understanding, the representative contacts (which may also be referred to as terminals) are shown, but there may be many more contacts for a real device. The die terminal can be, for example, solder, gold or a conductive organic material such as a silver filled epoxy or an epoxy type sphere coated with a conductor. As shown, a heat sink 86 is used to couple heat from the die 12 to a package substrate 84. The intermediate substrate 16 connects the terminals of the dies 12 and 14 to each other and to one of the top surfaces of the package substrate 84. One example of a die-to-die connection is that one of the terminals 104 of the die 12 is connected to one of the terminals 102 of the die 14 via a via 98. Another example is that the terminal 106 of the die 14 is connected to the terminal 108 of the die 12 via a via 100. The through holes 98 and 100 may pass through the plated holes of the intermediate substrate 16. An example of a connection between one of the die 14 and the intermediate substrate 16 is a terminal 110 connected to a pad 118 of the intermediate substrate 16 via a conductive line 120. The die 14 also has a terminal 114 that is connected to one of the intermediate substrate pads of the intermediate substrate 16. In the same manner, the die 12 has connections 112 and 116 that are connected to pads of the intermediate substrate 16. In this example, the pads on the intermediate substrate 16 connected to the pads of the die 12 or die 14 are connected to the package substrate 84 by wire bonds, such as by bond wires 111, which bond the wires 111 to the intermediate substrate A pad 118 of 16 is attached to the solder ball 90. The bonding wires are coupled to the solder balls on the bottom of the package substrate 84 in conjunction with a landing. Other exemplary solder ball solder balls 92, 94, and 96 are shown on the bottom of the package substrate 84 in FIG. The intermediate substrate 16 may be made of tantalum or some other material such as a ceramic such as aluminum nitride. The heat sink 86 can be made of a metal such as copper or another type of material that has good heat transfer. For heat sink 86, the desired target is a coefficient of good heat transfer and matching thermal expansion.

FIG. 5 is a top plan view of the dies 12 and 14 and similar dies 136 and 138 as shown on a wafer 140. The dies 12 and 14 are depicted as having contacts that are configured to be easily attached to the intermediate substrate 16 in a desired manner. In this example, the dies 12 and 14 should be identical but have slightly different functions. The die 12 acts as the primary or master, and the die 14 acts as a secondary or subordinate. Some contacts are used when the particular die is predominant and others are used when the particular die acts as a slave. Illustrated on the die 14 are contacts 102, 106, 110, 114, 120, 122, 124, 126, 154, and 156. Illustrated on the die 12 are contacts 104, 108, 112, 116, 128, 130, 132, 134, 158, and 160. When the secondary die 14 is in contact, the contacts associated with the secondary die 14 include contacts 102, 106, and 154. The unused master contacts 122, 124 and 156 are used. Master control contacts 122, 124, and 156 are each symmetrical with respect to slave contacts 106, 102, and 154 with respect to centerline 142. For example, the distance 146 from the centerline 142 to the contact 124 is the same as the distance 148 from the centerline 142 to the contact 102. The same applies to the die 12, to the contact contacts 108, 104 and 160 associated with the die 12 as a master. The unused slave contact contacts 130, 132 and 158 are associated with the die 12 as a master. The slave contacts 130, 132, and 158 are each symmetrical about the centerline 144 with the master contacts 108, 104, and 160. For example, the distance 150 from the centerline 144 to the contact 104 is the same as the distance 152 from the centerline 144 to the contact 132. This symmetry allows the dies 12 and 14 to be identical, but also aligns the slave contacts with the master contacts and the master contacts are aligned with the slave contacts. This allows the active regions of the dies 12 and 14 to face each other while being aligned with the intermediate substrate such that the slave contacts of one die are electrically connected to the master contacts of the other die. Because the dies are identical and either can be a slave or a master, each of the other contacts also has a corresponding symmetrical contact.

In other applications where the die may be different, the symmetry may not be of interest and the method illustrated in Figure 4 may be used without requiring symmetry.

Illustrated in Figure 6 is a completed device 168 as an alternative to the completed device 10 of Figure 4. Device 168 has dies 12 and 14 that contact an intermediate substrate 170 in a manner similar to how they are in contact with intermediate substrate 16 in FIG. Terminal 114, which is an exemplary terminal, is coupled to one of the contacts of intermediate substrate 170 via a conductor 182. The device 168 is different from the device 10 in that solder balls (such as solder balls 174) are used to contact the package substrate 172 to bring the intermediate substrate 170 into contact with a package substrate 172, and different portions are used as the main die 12 in the die. 14 on. The die 12 exposes the back side opposite the active side such that a heat sink can be applied to the back side. Compared to the secondary integrated circuit, the primary integrated circuit has a greater need for a heat sink. This also depicts solder balls (such as solder balls 176) as external connections to device 168 and the solder balls can be under the die. An exemplary conductor 180 connects the solder balls 174 to the solder balls 176 via the package substrate 172. The encapsulant 178 covers all areas except the back side of the dies 12 and 14 and the intermediate substrate 170. This type of package with a solder ball array is sometimes referred to as a ball grid array (BGA) package. These functional sides of the dies 12 and 14 are opposite the intermediate substrate 170 and do not require wire bonding.

Illustrated in Figure 7 is a device 190 that is completed as one of the alternatives. The dies 12 and 14 are attached to an intermediate substrate, wherein the active sides of the dies 12 and 14 are opposite the intermediate substrate as previously described for devices 10 and 168. In this case, a package substrate 191 has an opening in which a die 14 is resident. The package substrate has selected portions (such as conductive portions 194 and 196) for providing electrical contact outside of the package. The conductive portions 194 and 196 are an integral part of the structure of the package substrate 191. For example, the conductive portions 194 and 196 may be part of a lead frame of copper, generally referred to as a conductor of the alloy 42 or referred to as a quad flat Another leadframe material useful in one leadframe of a leadless (QFN) package. Electrical contacts from the intermediate substrate to the electrically conductive portions are transmitted through terminals (such as terminal 195) similar to the terminals previously described. An exemplary conductor 193 connects the die 12 to the terminal 195 via the intermediate substrate. In this example, the encapsulant 192 extends only to the top of the die 12 such that the backside of the die 12 is exposed and a heat sink can be applied.

Illustrated in FIG. 8 is a completed device 200 that is identical to the completed device 190 except that the die 14 is attached to the top and the die 12 is attached to the bottom and a sealant 202 covers the die 14. In this case, a heat sink needs to be applied to the bottom side of the finished device 200 because the bottom side is where the die 12 is exposed to its back side.

Illustrated in FIG. 9 is a device 210 that is similar to yet another alternative, having a die 12 and 14 attached to an intermediate substrate, as previously described for devices 10, 168, 190 and In the description of 200, the sides of the grains 12 and 14 act on the intermediate substrate. In this case, a solder ball, such as solder ball 212, is used to provide electrical connection to device 210. The die 12 is shown on the bottom so that the back side of the die 12 is exposed there for use in a heat sink. The die 14 has its back side exposed to the top. The dies 12 and 14 can be switched such that the die 12 can have its back side exposed on top of the device 210. Solder balls, such as solder balls 214, are shown attached to device 210, indicating that a BGA can also be fabricated in this manner.

As such, various variations of packaged dies 12 and 14 are available as illustrated in Figures 4-9. This package is particularly useful for the same conditions of the die, but such packages may have applicability outside of this particular case. The two dies can be very different, such as a grain optimized RF performance and a die design as logic. Further, the two crystal grains may be of different sizes.

To date, it has been understood that an information processing system has been provided which includes a first integrated circuit die and a second integrated circuit die. The first integrated circuit die includes: a first system interconnect, the first system interconnect includes a first plurality of masters and a first plurality of slaves, and the first system interconnects are a system interconnection protocol operation; a first processor core communicatively coupled to one of the first plurality of masters; a memory, the memory Communicatively coupled to one of the first plurality of slaves, a first slave circuit, and a first slave circuit communicatively coupled to the first plurality of slaves, the second slave . The second integrated circuit die includes: a second system interconnect, the second system interconnect includes a second plurality of masters and a second plurality of slaves, and the second system interconnect can follow the first a system interconnect protocol operation; a second processor core communicatively coupled to the first plurality of masters of the second plurality of masters; an addressable slave circuit, the Addressing slave circuitry communicatively coupled to one of the second plurality of slaves, the addressable slave circuit having an addressable address range, the addressable address range corresponding to the a first address range within an address map of an integrated circuit die, the addressable address range corresponding to a second bit in one of the address mappings of the second integrated circuit die And a first main control circuit communicatively coupled to one of the second plurality of masters, the second master. The first slave circuit is communicably coupled to the first master circuit for interconnecting via the first system interconnect and the second system via one of the first integrated circuit dies The master provides information during a data access to the addressable slave circuit. A further feature of the system is that at least one of the first slave circuit and the first master circuit includes a address translation circuit for translating an address of the addressable slave circuit from the first address range into The second address range. A further feature of the system is that the first master control circuit includes a translation circuit. The system can further include a memory configured to store configuration information, the configuration information for controlling the system to operate in one of a plurality of modes, wherein in one of the plurality of modes, the first mode, Accessing the data access to the addressable slave circuit by a system interconnect master that addresses the first system interconnect of the first address range, and in a second mode of operation, the addressable slave circuit The data access is achieved by a system interconnect master of the first system interconnect that addresses a third address range of the address mapping of the first integrated circuit die. A further feature of the system is that the addressable slave circuit is a memory circuit. The system may further include a configuration communication path between the first integrated circuit die and the second integrated circuit die, the configured communication path being used in the first integrated circuit die and Operating mode information is provided between the second integrated circuit dies. A further feature of the system is that the addressable slave circuit is a memory circuit. A further feature of the system is that the addressable slave circuit is a peripheral circuit. A further feature of the system is that during at least one mode of operation, the second core is in a low power mode during data access to the addressable slave circuit. The system is further characterized in that the first integrated circuit die is a microcontroller and the second integrated circuit die is a microcontroller. A further feature of the system is that the first integrated circuit further comprises: a second main control circuit communicably coupled to one of the first plurality of masters and the second master An external terminal coupled to the first integrated circuit die, wherein the external terminals are configured in an unavailable state; and a second slave circuit communicatively coupled to the second a second slave of the plurality of slaves and an external terminal coupled to the die of the second integrated circuit, the external terminals of the second integrated circuit die being configured in an unavailable state, wherein the At least one of the second slave circuit and the second master circuit includes a bit address translation circuit for translating the address. The system can further include a memory configured to store configuration information for controlling the system to operate in one of a plurality of modes, wherein in one of the plurality of modes, the first mode The first integrated circuit die operates as a primary integrated circuit die and the second integrated circuit die operates as a primary integrated circuit die, and in one of the plurality of modes, the second mode The second integrated circuit die operates as a main integrated circuit die and the first integrated circuit die operates as a primary integrated circuit die. The system is further characterized in that the first integrated circuit die and the second integrated circuit die are incorporated in an integrated circuit package.

Also described is one method of operating an information processing system. The method includes providing power to a first integrated circuit die, the first integrated circuit die comprising: a first system interconnect, the first system interconnect comprising a first plurality of masters and a first plurality a slave system, the first system interconnect operable in accordance with a first system interconnect protocol; a first processor core communicatively coupled to one of the first plurality of masters a first master circuit; and a first slave circuit communicatively coupled to the first slave of the first plurality of slaves. The method further includes providing power to a second integrated circuit die, the second integrated circuit die comprising: a second system interconnect, the second system interconnect comprising a second plurality of masters and a second a plurality of slaves, the second system interconnect operable in accordance with the first system interconnect protocol; a second processor core communicatively coupled to the second plurality of masters a first master 埠; an addressable slave circuit communicatively coupled to the first slave of the second plurality of slaves, the addressable slave circuit having an addressable address a range, the addressable address range corresponding to a first address range in an address map of the first integrated circuit die, the addressable address range corresponding to the second product a second address range within one of the address mappings of the body circuit die; and a first master control circuit communicatively coupled to one of the second plurality of masters Master control. The method further includes performing a data access to one of the addressable slave circuits via a system interconnect master circuit of the first system interconnect of the first integrated circuit die, the data access via the The first system interconnection, the first slave circuit, the first master circuit, and the second system are interconnected for execution. The method may further include, by the system interconnecting the main control circuit, providing a first address of the data access in the first address range to the first system interconnect, wherein the first slave circuit Receiving the first address from the first system interconnect, translating the first address from the first address range to the second address range to generate a translated address, by the first The master circuit provides the translated address to the second system interconnect and receives the translated address from the second system interconnect by the addressable slave circuit. A further feature of the method is that the translation is performed by the first master circuit. A further feature of the method is that the translation is performed by the first slave circuit. The method can further include performing a data access to one of the addressable slave circuits via a system interconnect master circuit of the first system interconnect of the first integrated circuit die, the data access via the The first system interconnection, the first slave circuit, the first master circuit, and the second system are interconnected, wherein performing a data access further comprises: interconnecting the master circuit by the system, An address is provided on the first system interconnect, the first address is an address within a range of addresses of a second slave circuit, and the second slave circuit is communicatively coupled to the first system Interconnecting one of the first plurality of slaves of the first plurality of slaves; receiving, by the first slave circuit, a data access from the first system interconnect, and wherein the second slave circuit does not receive the data Accessing the data access from the first slave circuit to the first master circuit; providing the data access to the second system interconnect by the first master circuit; The addressable slave circuit receives the interconnection from the second system Data access. The method can further include performing a data access to one of the addressable slave circuits via a system interconnect master circuit of the first system interconnect of the first integrated circuit die, the data access via the Executing, the first slave circuit, the first master circuit, and the second system are interconnected, wherein performing a data access further comprises: interconnecting the master circuit by the system to be a first An address is provided on the first system interconnect, the first address being at an address within a range of one of the second slave circuits, the second slave circuit being communicably coupled to the first system interconnect One of the first plurality of slaves, the second slave; receiving, by the first slave circuit, a data access from the first system interconnect, and wherein the second slave circuit does not receive the data access Providing a data access from the first slave circuit to the first master circuit; providing the data access to the second system interconnect by the first master circuit; and by the addressable The slave circuit receives the data from the second system interconnect Take. The method further includes inhibiting operation of the second processor core during execution of a data access.

Moreover, the terms "front", "rear", "top", "bottom", "above", "below" and the like (if any) are used in the description of the invention and in the scope of the claims. The purpose of the description is not necessarily used to describe a permanent relative position. It is to be understood that the terms so used are interchangeable under appropriate conditions such that the embodiments of the invention described herein, for example, are capable of operation in the

While the invention has been described herein with reference to the specific embodiments thereof, various modifications and changes can be made without departing from the scope of the invention as set forth in the appended claims. For example, the crossbars are indicated as one instance of a system interconnect, but another type of system interconnect can be used. Again, the core of the secondary die is described as powered down. Powering down does not necessarily mean removing all power, but may be a relatively small action, such as simply stopping the core clock or selectively removing power from portions of the core. Other examples of reducing the power consumption of the core can also be used. Accordingly, the specification and drawings are to be regarded as a The solution to any benefit, advantage, or problem described herein with respect to a particular embodiment is not intended to be a critical, required or essential feature or element of any or all of the embodiments.

The term "coupled," as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.

In addition, the terms "a" or "an", as used herein, are defined as one or more than one. In the same way, the use of pre-existing phrases such as "at least one" and "one or more" in such technical solutions should not be construed as implying that the indefinite article "a" or "a" Another technical solution element limits any specific technical solution containing the pre-technical component to the invention containing only the one component, even when the same technical solution includes the pre-speech "one or more" or " The same is true of at least one and indefinite articles such as "one" or "one". This is also the case with the use of definite articles.

Terms such as "first" and "second" may be used to arbitrarily distinguish the elements described by the terms, unless otherwise stated. Therefore, such terms are not necessarily intended to indicate the time or other priority of the elements.

10. . . Package device

12. . . Integrated circuit die

14. . . Integrated circuit die

16. . . Intermediate substrate

18. . . System interconnection

20. . . core

twenty one. . . Master control

twenty two. . . DMA

twenty three. . . Master control

twenty four. . . Main control circuit

25. . . Master control

26. . . Configuration register

27. . . Master control

28. . . Peripherals

29. . . Subordinate

30. . . Non-volatile memory (NVM)

31. . . Subordinate

32. . . Static random access memory (SRAM)

33. . . Subordinate

34. . . Slave circuit

35. . . Subordinate

36. . . decoder

38. . . External terminal

40. . . External terminal

42. . . External terminal

44. . . External terminal

46. . . System interconnection

48. . . core

50. . . DMA

52. . . Main control circuit

54. . . decoder

56. . . Configuration register

58. . . Peripherals

60. . . NVM

62. . . SRAM

64. . . Slave circuit

66. . . External terminal

68. . . External terminal

70. . . External terminal

72. . . External terminal

74. . . Dependent logic

76. . . Communication handshake circuit

78. . . Communication handshake circuit

80. . . Address translation circuit

82. . . Master logic

84. . . Package substrate

86. . . Heat sink

92. . . Solder ball

98. . . Through hole

100. . . Through hole

116. . . connection

118. . . pad

120. . . Conductive wire

136. . . Grain

138. . . Grain

140. . . Wafer

142. . . Center line

144. . . Center line

146. . . distance

148. . . distance

150. . . distance

152. . . distance

168. . . Device

170. . . Intermediate substrate

172. . . Package substrate

174. . . Solder ball

176. . . Solder ball

178. . . Sealants

180. . . conductor

182. . . conductor

190. . . Device

191. . . Package substrate

192. . . Sealants

193. . . conductor

194. . . Conductive part

195. . . Terminal

196. . . Conductive part

200. . . Device

202. . . Sealants

210. . . Device

214. . . Solder ball

102, 106, 110, 114, 120, 122, 124, 126, 154 and 156. . . Contact / terminal

104, 108, 112, 116, 128, 130, 132, 134, 158 and 160. . . Contact / terminal

1 is a block diagram of a multi-die device in accordance with an embodiment;

Figure 2 is a block diagram showing a portion of the apparatus of Figure 1 in more detail;

Figure 3 is an address map relating to the operation of the multi-die device; and

Figure 4 is a cross section of the device according to a first package embodiment;

Figure 5 is a top plan view of two dies that facilitate fabrication of the device of Figure 4;

Figure 6 is a cross section of the apparatus according to a second package embodiment;

Figure 7 is a cross section of the apparatus according to a third package embodiment;

Figure 8 is a cross section of the apparatus according to a fourth package embodiment; and

Figure 9 is a cross section of the apparatus in accordance with a fifth package embodiment.

10. . . Package device

12. . . Integrated circuit die

14. . . Integrated circuit die

16. . . Intermediate substrate

18. . . System interconnection

20. . . core

twenty one. . . Master control

twenty two. . . DMA

twenty three. . . Master control

twenty four. . . Main control circuit

25. . . Master control

26. . . Configuration register

27. . . Master control

28. . . Peripherals

29. . . Subordinate

30. . . Non-volatile memory (NVM)

31. . . Subordinate

32. . . Static random access memory (SRAM)

33. . . Subordinate

34. . . Slave circuit

35. . . Subordinate

36. . . decoder

38. . . External terminal

40. . . External terminal

42. . . External terminal

44. . . External terminal

46. . . System interconnection

48. . . core

50. . . DMA

52. . . Main control circuit

54. . . decoder

56. . . Configuration register

58. . . Peripherals

60. . . NVM

62. . . SRAM

64. . . Slave circuit

66. . . External terminal

68. . . External terminal

70. . . External terminal

72. . . External terminal

Claims (19)

An information processing system includes: a first integrated circuit die, the first integrated circuit die comprising: a first system interconnect, the first system interconnect comprising a first plurality of masters and a plurality of slaves, the first system interconnect operable in accordance with a first system interconnect protocol; a first processor core communicatively coupled to the first plurality of masters a first master; a memory communicatively coupled to the first slave of the first plurality of slaves; and a first slave circuit, the first slave circuit communicatively And a second integrated circuit die coupled to the first plurality of slaves; and the second integrated circuit die comprising: a second system interconnect, the second system interconnect Include a second plurality of masters and a second plurality of slaves, the second system interconnect operable in accordance with the first system interconnect protocol; a second processor core communicatively coupled To the first master of one of the second plurality of masters; one An address slave circuit communicatively coupled to one of the second plurality of slaves, the addressable slave address having an addressable address range, the addressable address range Corresponding to one of the first address ranges in one of the address maps of the first integrated circuit die, the addressable address range corresponding to one of the address mappings in the second integrated circuit die One of the second addresses And a first main control circuit communicatively coupled to the second plurality of masters of the second plurality of masters; wherein the first slave circuit is via the first system An interconnect and the second system interconnect are communicably coupled to the first master control circuit for mastering one of the addressable slave circuits by one of the first integrated circuit die system interconnects Information is provided during data access. The system of claim 1, wherein at least one of the first slave circuit and the first master circuit includes a address translation circuit for using an address of the addressable slave circuit from the first address The range is translated into the second address range. The system of claim 1, wherein the first master circuit comprises a translation circuit. The system of claim 1, further comprising: a memory configured to store configuration information, wherein the configuration information is used to control the system to operate in one of a plurality of modes, wherein: And in one of the plurality of modes, in the first mode, the data access to the addressable slave circuit is achieved by a system interconnect master that addresses the first system interconnect of the first address range; In the second mode of operation, the data access to the addressable slave circuit is interconnected by one of the first system interconnects addressing the third address range of the address map of the first integrated circuit die The master reached. The system of claim 4, wherein the addressable slave circuit is a memory circuit. The system of claim 1, further comprising: a configuration communication path between the first integrated circuit die and the second integrated circuit die, the configured communication path being used Operating mode information is provided between the first integrated circuit die and the second integrated circuit die. A system as claimed in claim 1, wherein the addressable slave circuit is a memory circuit. A system as claimed in claim 1, wherein the addressable slave circuit is a peripheral circuit. A system as claimed in claim 1, wherein during the at least one mode of operation, the second core is in a low power mode during data access to the addressable slave circuit. The system of claim 1, wherein the first integrated circuit die is characterized as a microcontroller, and the second integrated circuit die is characterized as a microcontroller. The system of claim 1, wherein: the first integrated circuit die further comprises: a second main control circuit communicably coupled to one of the first plurality of masters a second master control circuit, the second master control circuit is coupled to an external terminal of the first integrated circuit die, wherein the external terminals are configured in an unavailable state; the second integrated circuit die further include: a second slave circuit communicatively coupled to the second plurality of slaves of the second plurality of slaves, the second slave circuit being coupled to an external terminal of the second integrated circuit die The external terminals of the second integrated circuit die are configured in an unavailable state; and at least one of the second slave circuit and the second master circuit includes an address translation circuit for Translate an address. The system of claim 1, the system comprising: a memory configured to store configuration information, wherein the configuration information is used to control the system to operate in one of a plurality of modes, wherein: In the first mode of the plurality of modes, the first integrated circuit die operates as a main integrated circuit die, and the second integrated circuit die operates as a primary integrated circuit die; In one of the plurality of modes, in the second mode, the second integrated circuit die operates as a main integrated circuit die, and the first integrated circuit die operates as a primary integrated circuit die. The system of claim 1, wherein the first integrated circuit die and the second integrated circuit die are incorporated in an integrated circuit package. A method of operating an information processing system, the method comprising: providing power to a first integrated circuit die, the first integrated circuit die comprising: a first system interconnect, the first system interconnect comprising a plurality of masters and a first plurality of slaves, the first system interconnection can be followed a first system interconnect protocol operation; a first processor core communicatively coupled to one of the first plurality of masters; a first slave circuit; and a first slave circuit The first slave circuit is communicatively coupled to the first slave of the first plurality of slaves; providing power to a second integrated circuit die, the second integrated circuit die comprising: a first a second system interconnect comprising a second plurality of masters and a second plurality of slaves, the second system interconnect operable in accordance with the first system interconnect protocol; a second processor core The second processor core is communicably coupled to one of the second plurality of masters; an addressable slave circuit communicatively coupled to the second plurality a first slave of the slave, the addressable slave circuit having an addressable address range corresponding to a first address range within one of the address maps of the first integrated circuit die The addressable address range and corresponding to the second integrated body a addressable address range of one of the second address ranges in one of the address lands; and a first main control circuit communicatively coupled to the second plurality of main Controlling one of the second masters; and performing a data access to one of the addressable slave circuits by one of the first system interconnects of the first integrated circuit die interconnecting the master circuit The data access is interconnected by the first system, the first slave The circuit, the first main control circuit and the second system are interconnected and executed. The method of claim 14, wherein the performing a data access further comprises: by the system interconnecting the main control circuit, providing the first address of the data access in the first address range to the first address Receiving, by the first slave circuit, the first address from the first system interconnection; translating the first address from the first address range to the second address range Transmitting a translated address; providing the translated address to the second system interconnect by the first master circuit; and receiving, by the addressable slave circuit, the second system The translated address of the interconnection. The method of claim 15, wherein the translation is performed by the first master circuit. The method of claim 15, wherein the translation is performed by the first slave circuit. The method of claim 15, wherein the performing a data access further comprises: providing, by the system interconnecting the main control circuit, a first address on the first system interconnect, the first address being An address within one of the address ranges of one of the second slave circuits, the second slave circuit being communicably coupled to the second plurality of slaves of the first plurality of slaves of the first system interconnect; Receiving, by the first slave circuit, the data access from the first system interconnect, and wherein the second slave circuit does not receive the data access; providing the data access from the first slave circuit To the first main control circuit; the data access is provided to the second system interconnect by the first main control circuit; and the interconnected slave circuit is configured to receive the interconnection from the second system Data access. The method of claim 14, further comprising: inhibiting operation of the second processor core during the performing a data access.