TWI589032B - System-in-package module with memory - Google Patents

Description

System-in-package memory module with memory

The invention relates to a system-level package memory module with memory, in particular to a system-level package memory module integrating a cache memory and a dynamic random access memory.

In general, memory circuits are typically designed to be standard memory circuits that are independent of the application logic circuit based on specific industry standards, such as the Joint Electronic Device Engineering Council (JEDEC). That is, based on specific industry standards, memory circuits are standard memory circuits designed to be suitable for a variety of different application logic circuits.

In application logic, the application logic requires a memory controller to control communication between the standard memory circuit and the application logic. Because memory controllers must communicate with a variety of standard memory circuits, memory controllers in application logic tend to be designed with sub-optimal performance, efficiency, and cost to accommodate a variety of standard memory circuits. .

However, the industry now tends to provide known good dies for memory circuits to facilitate integration of application logic into system in package (SIP) modules. Because the application logic only needs to communicate with the memory circuit to confirm the chip, if the memory controller in the application logic circuit is designed to have sub-optimal performance, efficiency and cost, in response to various standard memory types. Circuitry, system-in-package modules will not perform at their best.

An embodiment of the invention provides a system level package memory module having a memory. The system-in-package memory module includes a cache memory circuit, a memory controller, a memory circuit, and a substrate, wherein the cache memory circuit, the memory controller, and the memory circuit are common The package is mounted on the substrate, and the cache memory circuit and the memory controller are formed on the same semiconductor wafer.

Another embodiment of the present invention provides a system-in-package memory module having a memory. The system-in-package memory module includes a non-memory circuit, a memory controller, a memory circuit, and a substrate, wherein the non-memory circuit, the memory controller, and the memory circuit are co-packaged in the Above the substrate, the memory circuit and the memory controller are formed on the same semiconductor wafer.

Another embodiment of the present invention provides a system-in-package memory module having a memory. The system-in-package memory module includes a non-memory circuit, a substrate, and a memory circuit. The non-memory circuit has a first portion and a second portion. The substrate has a window and the substrate electrically connects the second portion of the non-memory circuit. The memory circuit is disposed on a window of the substrate and electrically connected to the first portion of the non-memory circuit, and there is no direct metal connection between the memory circuit and the substrate.

Another embodiment of the present invention provides a system-in-package memory module having a memory, the system-in-package memory module including a non-memory circuit, a substrate, and a memory circuit. The non-memory circuit has a first portion and a second portion, wherein the non-memory circuit includes a plurality of first electrical contacts and a plurality of second electrical contacts, and the plurality of first electrical contacts and the plurality of The two electrical contacts are respectively disposed in the first portion and the second portion of the non-memory circuit. The memory circuit has a plurality of third electrical contacts disposed on one side of itself. The substrate has a plurality of fourth electrical contacts disposed on one side of itself. The plurality of first electrical contacts electrically connect the plurality of third electrical contacts to Electrically connecting the memory circuit to the non-memory circuit, the plurality of second electrical contacts electrically connecting the plurality of fourth electrical contacts to electrically connect the substrate to the non-memory circuit, and the substrate and the memory circuit are Electrically connected to the same side or different sides of the non-memory circuit.

The invention provides a system level package memory module with a memory. The system-in-package memory module integrates a memory circuit (embedded dynamic random access memory), a non-memory circuit (logic circuit), and a substrate in a system-level package, so the present invention can reduce the The area of the system-level package memory module. In addition, since the system-in-package memory module of the present invention can be customized to accommodate different memory circuits (embedded dynamic random access memory) and non-memory circuits (logic circuits), the system of the present invention Level-package memory modules have optimized performance, efficiency, or cost.

100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 450‧‧‧ system-level package memory modules

102, 202, 302‧‧‧ cache memory circuits

104, 204, 304‧‧‧ memory controller

106, 206, 306‧‧‧ Dynamic Random Access Memory Circuit

108, 208, 406, 506, 606, 706, 1006‧‧‧ substrates

310‧‧‧First reconfigurable busbar

312‧‧‧External CPU

314‧‧‧Second reconfigurable bus

3042, 9102‧‧‧ mode register

3044, 9104‧‧‧ configuration circuit

3046, 9106‧‧‧ clock generator

30442, 91042‧‧‧Input/Output Width Controller

30444, 91044‧‧‧ Output unit

30446, 91046‧‧‧ input unit

402, 502, 602, 704, 804, 904, 1004, 1106, 1208, 1304‧‧‧ memory circuits

404, 504, 604, 702, 802, 902, 1010, 1104, 1204, 1306‧‧‧ non-memory circuits

4022‧‧‧ Third electrical contact

4042‧‧‧First electrical contact

4044‧‧‧second electrical contact

4062‧‧‧4th electrical contact

4064‧‧‧ fifth electrical contact

4066, 7062‧‧‧ window

508‧‧‧welding line

510, 608‧‧‧ mould material

6044, 408, 412‧‧ ‧bump structure

8022, 9022‧‧‧ parallel to serial bus bar programmable intermediation unit

8024, 9024, 9026‧‧‧Reconfigurable busbars

9108‧‧‧Parallel/serial controller

9028, 8026‧‧‧High speed serial bus

1002, 1008, 1102‧‧‧ resin

1202‧‧‧First radiator

1206‧‧‧second heat sink material

1302‧‧‧Additional memory

1308‧‧‧Electrical contacts

C1-C4‧‧‧ nuclear

DVFS‧‧‧Dynamic voltage frequency adjustment unit

eDRAM‧‧‧Embedded Dynamic Random Access Memory

ECC‧‧‧Error Correction Code Unit

L1, L2, L3‧‧‧ cache memory

MMU‧‧‧Cache Management Unit

TSV, 6042, 410‧‧‧Direct crystal perforation

1 is a schematic view showing a system-in-package memory module having a memory according to a first embodiment of the present invention.

2 is a schematic view showing a system-in-package memory module having a memory according to a second embodiment of the present invention.

Fig. 3 is a schematic view showing a system-in-package memory module having a memory according to a third embodiment of the present invention.

4A is a schematic diagram showing a system-in-package memory module having a memory according to a fourth embodiment of the present invention.

Figure 4B is a schematic diagram showing the explosion of the system-in-package memory module.

FIG. 4C is a schematic diagram showing a system-in-package memory module having a memory according to a fifth embodiment of the present invention.

Fig. 5 is a schematic view showing a system-in-package memory module having a memory according to a sixth embodiment of the present invention.

Figure 6 is a schematic diagram showing a system-in-package memory module having a memory according to a seventh embodiment of the present invention.

Figure 7 is a schematic diagram showing a system-in-package memory module having a memory according to an eighth embodiment of the present invention.

Figure 8 is a diagram showing a system-in-package memory module having a memory according to a ninth embodiment of the present invention.

Figure 9 is a schematic diagram showing a system-in-package memory module having a memory according to a tenth embodiment of the present invention.

Figure 10 is a schematic diagram showing a system-in-package memory module having a memory according to an eleventh embodiment of the present invention.

Figure 11 is a block diagram showing a system-in-package memory module having a memory according to a twelfth embodiment of the present invention.

Figure 12 is a diagram showing a system-in-package memory module having a memory according to a thirteenth embodiment of the present invention.

Figure 13A is a diagram showing a system-in-package memory module having a memory in accordance with a fourteenth embodiment of the present invention.

FIG. 13B is a schematic diagram showing a system-in-package memory module having a memory according to a fifteenth embodiment of the present invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram showing a system-in-package (SIP) memory module 100 having a memory according to a first embodiment of the present invention. As shown in FIG. 1, the system-in-package memory module 100 includes a cache memory circuit 102, a memory controller 104, a dynamic random access memory (DRAM) circuit 106, and a substrate 108, wherein the dynamic random access memory circuit 106 (the main memory in the system-in-package memory module 100) is a dynamic random access memory (Dynamic Random Access Memory (DRAM), or a plurality of dynamic random access memories assembled or stacked together. In addition, the cache memory circuit 102, the memory controller 104, and the memory circuit 106 are collectively packaged on the substrate 108, and the cache memory circuit 102 and the memory controller 104 are formed on the same semiconductor wafer. The same semiconductor wafer is a germanium wafer fabricated according to a complementary metal-oxide-semiconductor (CMOS) process. The cache memory circuit 102 can be a static random access memory (SRAM) or a dynamic random access memory having a higher operating speed or bandwidth than the dynamic random access memory circuit 106. For example, the bandwidth or operating speed of the cache memory circuit 102 is three times or more that of the dynamic random access memory circuit 106. The cache memory circuit 102 and the dynamic random access memory circuit 106 may be disposed on the substrate 108 or stacked on the substrate 108 after being stacked on each other. The substrate 108 can be a flexible organic substrate or a conventional printed circuit board (eg, a Ball Grid Array (BGA) substrate.

As shown in FIG. 1, the memory controller 104 is part of the cache memory circuit 102. However, in another embodiment of the invention, the memory controller 104 is external to the cache memory circuit 102. As shown in FIG. 1, the memory controller 104 includes a cache management unit MMU, a dynamic voltage frequency adjustment unit DVFS, and an error correction code unit ECC. According to the instruction of the system-level package memory module 100, the cache management unit MMU does not control the read (or write to) cache memory circuit 102 or control the read (or write to) dynamic random access memory. The output data (or input data) of the body circuit 106. The error correction code unit ECC can correct data errors stored in the cache memory circuit 102 or the dynamic random access memory circuit 106. The dynamic voltage frequency adjustment unit DVFS can dynamically change a combination of the operating voltage, the operating frequency, and the bus bar width of the system-in-package memory module 100.

Referring to FIG. 2, FIG. 2 is a schematic diagram showing a system-in-package memory module 200 having a memory according to a second embodiment of the present invention. As shown in Figure 2, dynamic random access The memory circuit 206 (main memory) includes a plurality of dynamic random access memories stacked together, and the dynamic random access memory circuit 206 is disposed on the cache memory circuit 202 and through direct twinning ( Through Silicon Via, TSV) electrically connects the cache memory circuit 202. As shown in FIG. 2, the cache memory circuit 202 includes a memory controller 204 and is disposed on the substrate 208. The bandwidth or operation speed of the cache memory circuit 202 is the dynamic random access memory circuit 206. Three times or more, however, the storage capacity of the dynamic random access memory circuit 206 is three times the storage capacity of the cache memory circuit 202. In addition, in the case of accessing the dynamic random access memory circuit 206 and the cache memory circuit 202 the same number of times, the power consumption of the dynamic random access memory circuit 206 is three times that of the cache memory circuit 202. . In addition, the present invention is not limited to the bandwidth or operation speed of the cache memory circuit 202 being three times or more than that of the dynamic random access memory circuit 206 and the storage capacity of the dynamic random access memory circuit 206 is cached. The storage capacity of the memory circuit 202 is three times or more.

Please refer to FIG. 3. FIG. 3 is a schematic diagram showing a system-in-package memory module 300 having a memory according to a third embodiment of the present invention. As shown in FIG. 3, the dynamic voltage frequency adjustment unit DVFS of the memory controller 304 can pass through a first reconfigurable bus bar between the memory controller 304 and the dynamic random access memory circuit 306 (eg, 128). , 256 or more bit width buss 310) accessing the DRAM circuit 306, and converting the first reconfigurable bus data to another second reconfigurable bus data to an external central processing (or other logic circuit) 312. The mode register 3042 in the dynamic voltage frequency adjustment unit DVFS can reconfigure the memory channels required by the first reconfigurable bus bar 310 or the second reconfigurable bus bar 314 in a relatively fast round trip time, Granularity, frequency, data voltage swing, or bus width. For example, when four DRAM chips having a memory depth of 512M and a busbar width of 32 bits are stacked in the DRAM circuit 306, the DRAM circuit 306 can be temporarily stored according to the mode. The content in the device 3042 is set to have a dynamic randomness with a memory depth of 1 G and a bus bar width of 64 bits or a memory depth of 512 M and a bus bar width of 128 bits. The memory circuit 306 is accessed.

As shown in FIG. 3, the dynamic voltage frequency adjustment unit DVFS further includes a configuration circuit 3044 and a clock generator 3046. As shown in FIG. 3, the mode register 3042 can be set by an external central processing unit (or other logic circuit) 312, and the configuration circuit 3044 can control and reconstruct the dynamic random according to the contents of the mode register 3042. The first reconfigurable bus bar 310 between the memory 306 and the memory controller 304 is accessed. For example, when four DRAM chips having a memory depth of 512M and a bus bar width of 32 bits are stacked in the DRAM circuit 306, the bus bar width of the first reconfigurable bus bar 310 can be It is set to 32-bit, 64-bit or 128-bit, and its memory depth can be set to 2G, 1G or 512M, respectively.

As shown in FIG. 3, the configuration circuit 3044 includes an input/output width controller 30442, an output unit 30444, and an input unit 30446. The input/output width controller 30442 can access the content within the mode register 3042 and configure the first reconfigurable bus bar 310 or the second reconfigurable bus bar 314. Therefore, the present invention can realize configurations of different bus bar widths. For example, in an embodiment of the invention, the bus bar width of the first reconfigurable bus bar 310 is set to M bits and the voltage swing on the first reconfigurable bus bar 310 (between the logic potentials) The voltage difference between the 1" signal and the logic potential "0" signal is set to 1.8V, the bus bar width of the second reconfigurable bus bar 314 is set to N bits, and in the second reconfigurable bus bar 314. The upper voltage swing is set to 1.2V, and the output unit 30444 in the configuration circuit 3044 receives the M-bit data of the first reconfigurable bus bar 310, and outputs the N according to the clock signal generated by the clock generator 3046. The bit data is transferred to the second reconfigurable bus bar 314. At this time, the output unit 30444 can also reduce the voltage swing of the M-bit data from 1.8V to 1.2V (or lower). Therefore, the output unit 30444 can receive the M-bit data with the voltage swing of 1.8V from the dynamic random access memory circuit 306 (or the cache memory circuit 302) through the first reconfigurable bus bar 310, and generate the voltage. N-bit data of 1.2V is swung and passed through a second reconfigurable bus 314 between the external central processor 312 and the memory controller 304 Send to external CPU 312.

On the other hand, as shown in FIG. 3, the input unit 30446 of the configuration circuit 3044 is configured to receive parallel N-bit data having a voltage swing of 1.2 V from the external central processing unit 312 through the second reconfigurable bus bar 314. The parallel N-bit data having a voltage swing of 1.2 V is converted into parallel M-bit data having a voltage swing of 1.8 V to the first reconfigurable bus bar 310, and written by the first reconfigurable bus bar 310 having 1.8 The parallel M-bit data of the V voltage swing is applied to the DRAM circuit 306 (or the cache memory circuit 302).

At this time, the operating frequency of the first reconfigurable bus bar 310 or the second reconfigurable bus bar 314 is also variable according to the content of the mode register 3042, and the clock generator in the dynamic voltage frequency adjusting unit DVFS. The reference frequency of the first reconfigurable bus bar 310 or the second reconfigurable bus bar 314 can be controlled 3046.

Please refer to FIG. 4A-4C. FIG. 4A is a schematic diagram showing a system-in-package memory module 400 with a memory according to a fourth embodiment of the present invention, and FIG. 4B is a diagram showing a system-in-package memory module 400. FIG. 4C is a schematic diagram showing a system-in-package memory module 450 having a memory according to a fifth embodiment of the present invention. As shown in FIG. 4A, the system-in-package memory module 400 is a Dual Die Flat (DDF) Ball Grid Array (BGA) with embedded dynamic random access memory. The system-in-package memory module 400 includes a memory circuit 402, a non-memory circuit 404, and a substrate 406. The memory circuit 402 can be a known good die memory (KGDM) or a plurality of known good wafer memories assembled or stacked together. The non-memory circuit 404 can be a logic circuit, such as a central processing unit. The substrate 406 can be a flexible organic substrate or a conventional printed circuit board, such as a Ball Grid Array (BGA) substrate.

The non-memory circuit (or logic circuit) 404 has a central portion and a peripheral portion. As shown in FIG. 4B, the plurality of first electrical contacts 4042 and the plurality of second electrical contacts 4044 of the non-memory circuit 404 are respectively disposed at the central portion and the peripheral portion, wherein the plurality of first electrical Each of the contacts 4042 and the plurality of second electrical contacts 4044 can be a solder ball or a copper post. As shown in FIG. 4B, the memory circuit 402 includes a plurality of third electrical contacts 4022 disposed on one side thereof, and the substrate 406 also includes a plurality of fourth electrical contacts 4062 disposed on one side thereof and on itself. The other plurality of fifth electrical contacts 4064 on the other side. As shown in FIG. 4B, since the plurality of first electrical contacts 4042 are electrically connected to the plurality of third electrical contacts 4022, the memory circuit 402 can be electrically connected to the central portion of the non-memory circuit 404, and because of the plurality of The second electrical contact 4044 is electrically connected to the plurality of fourth electrical contacts 4062, so the substrate 406 can be electrically connected to the peripheral portion of the non-memory circuit 404. Therefore, as shown in FIG. 4A, the memory circuit 402 is disposed under the central portion of the non-memory circuit 404 and the substrate 406 is disposed under the peripheral portion of the non-memory circuit 404.

As shown in FIG. 4B, the substrate 406 further includes a hollow space (or window) 4066, wherein the memory circuit 402 is disposed in a hollow space of the substrate 406 to electrically connect the non-memory circuit 404. Therefore, both the substrate 406 and the memory circuit 402 are disposed on the same side of the non-memory circuit 404. Thus, as shown in FIG. 4A, there is no direct metal connection between the memory circuit 402 and the substrate 406. In addition, the system-in-package memory module 400 can be disposed on an external circuit board (not shown in FIG. 4B) and electrically connected to the external circuit board through a plurality of fifth electrical contacts 4064 disposed on the substrate 406.

As shown in FIG. 4C, the memory circuit 402 of the system-in-package memory module 450 is disposed on the non-memory circuit 404 and electrically connected through a face-to-face bumping structure 408. The non-memory circuit 404 and the substrate are electrically connected by a face-to-face bumping structure 408 and a direct twinned via (TSV) 410. 406. The non-memory circuit 404 of the system-in-package memory module 450 electrically connects the substrate 406 through another face-to-face bump structure 412.

Referring to FIG. 5, FIG. 5 is a schematic diagram showing a system-in-package memory module 500 having a memory according to a sixth embodiment of the present invention. As shown in FIG. 5, a non-memory circuit 504 of the system-in-package memory module 500 has a wire-bond 508 between the surface of the active device area and the substrate 506, and a memory. The circuit 502 (embedded dynamic random access memory) can electrically connect the non-memory circuit 504 (logic circuit) through a face-to-face bumping structure. The bump structure is related to a solder or bump process wherein the solder or bump process includes solder bump steps, copper to copper bumps or other similar bump processing steps. In addition, a mold material 510 may be formed over portions of the memory circuit 502 (embedded dynamic random access memory) and the substrate 506, wherein the mold material 510 may cover the memory circuit 502 (embedded dynamic random access memory) And non-memory circuit 504 (logic circuit). In addition, the non-memory circuit 504, a memory controller and the memory circuit 502 are collectively packaged on the substrate 506, and the memory circuit 502 and the memory controller are formed on the same semiconductor wafer.

Please refer to FIG. 6. FIG. 6 is a schematic diagram showing a system-in-package memory module 600 having a memory according to a seventh embodiment of the present invention. As shown in FIG. 6, the non-memory circuit 604 (logic circuit) has a direct twin via (TSV) 6042, wherein the active device region of the non-memory circuit 604 (logic circuit) is electrically connected to the substrate 606 through the bump structure 6044. . The bump structure 6044 described in FIG. 6 includes solder bumps, bumps produced by copper-to-copper bumps or other similar bump processes. The memory circuit 602 (embedded dynamic random access memory) can electrically connect the back surface (矽 substrate) of the non-memory circuit 604 (logic circuit) through the direct twinned via 6042 and the bump structure 6044. In addition, a mold material 608 may be formed over the memory circuit 602 (embedded dynamic random access memory) and a portion of the substrate 606, wherein the mold material 608 may cover the memory circuit 602 (embedded dynamic random access memory) And non-memory circuit 604 (logic circuit). Additionally, in another embodiment of the invention, The portion of the top or non-memory circuit 604 (logic circuit) of the memory circuit 602 (embedded dynamic random access memory) may be an open space that is not covered by the mold material 608. In addition, a heat sink or a heat sink may be disposed on top of the memory circuit 602 (embedded dynamic random access memory) or a portion of the non-memory circuit 604 (logic circuit) to enable the memory circuit 602 (embedded dynamics) The random access memory) or non-memory circuit 604 (logic circuit) dissipates heat more efficiently during operation to prevent overheating.

Please refer to FIG. 7. FIG. 7 is a schematic diagram showing a system-in-package memory module 700 with a memory according to an eighth embodiment of the present invention. As shown in FIG. 7, the non-memory circuit 702 of the system-in-package memory module 700 is a multi-core CPU, such as Intel's Haswell central processor (4-core CPU). Each of the four cores C1-C4 of the non-memory circuit 702 may include an internal level 1 cache memory L1 and a level 2 cache memory L2, and the non-memory circuit 702 additionally includes an additional 4 core C1. - Internal level 3 cache memory L3 shared by each core in -C4 (as shown in Figure 7). The memory circuit 704 of the system-in-package memory module 700 can be an embedded dynamic random access memory chip or a plurality of embedded dynamic random access memory chips stacked together, wherein the memory circuit 704 can be The memory is cached for an external level 4 of the non-memory circuit 702. As shown in FIG. 7, the substrate 706 is a ball grid array package substrate having a window 7062, and the memory circuit 704 is disposed at the window 7062 to electrically connect the non-memory circuit 702. In another embodiment of the present invention, the multi-core (4-core C1-C4) of the non-memory circuit 702 may have a plurality of computing functions, wherein several cores of the multi-core of the non-memory circuit 702 are used as a general The computational uses of the purpose (such as the core of the central processing unit, etc.) and the other cores of the multicore of the non-memory circuit 702 are used for drawing, display, or high-bandwidth computing purposes (such as the core of a graphics processor). The memory circuit 704 can be partitioned into a number of working channels, with a fixed number of bits per channel being defined according to the workload of the last stage of the cache memory in a given hardware configuration. In another embodiment of the present invention, the memory circuit 704 includes a plurality of memory arrays, wherein the plurality of memory arrays are based on a central processor core in the non-memory circuit 702. The workload of each core of the heart or graphics processor core is dynamically allocated to different cores in the multicore of the non-memory circuit 702. For example, more than 50%-80% of memory arrays are dynamically allocated to one or more graphics processor cores based on workloads from different software programs (ie, applications), one or more of the central processing units. Memory arrays that occupy less than 50%-80% should be used based on lighter workload requirements. Since the plurality of memory arrays can be dynamically allocated to different cores according to the workload of each core of the central processor core or the graphics processor core in the non-memory circuit 702, the cache mechanism of the memory circuit 704 can save The standby power and computational power consumption of the memory circuit 704 and the battery life in a common electronic device such as a notebook computer, a handheld computing device, a smart phone, a tablet computer, or a communication device. To save the cost of the memory circuit 704 during the manufacturing of the system-in-package memory module 700, one or more memory arrays within the memory circuit 704 can be buffered by one or more registers within the memory circuit 704. Disabled, or may be disabled by one or more registers outside of memory circuit 704 (i.e., by one or more registers in another circuit). In another embodiment of the present invention, the memory circuit 704 includes one or more memory arrays, wherein the or the plurality of memory arrays are "tag memory" for accompanying data cache arrays. )"use. In another embodiment of the present invention, the memory circuit 704 includes a control logic module, wherein the control logic module is used for control of a cache and/or a tag memory. When the memory circuit 704 is accessed (read or written) by the central processing unit core or the graphics processor core, the control logic module can schedule the cached selected/unselected programs. The memory circuit 704 further includes one or more static random access memory arrays for reading or writing at a higher speed. For example, a tag memory can be used to enhance the cache memory accompanying the dynamic random access memory array. The read/write speed performance of the body can be used as a control register to dynamically control the allocation, operating voltage level or operating frequency of the plurality of memory arrays to the central processor core/plot processor core. The memory circuit 704 further includes an error correction code unit circuit module, wherein the error correction code unit circuit module is used to recover dynamic errors during the read/write process, or can be used to recover the process in the semiconductor Defective bits or arrays produced in . As such, the memory circuit 704 can have both higher yield and lower cost.

Please refer to FIG. 8. FIG. 8 is a schematic diagram showing a system-in-package memory module 800 having a memory according to a ninth embodiment of the present invention. As shown in FIG. 8, the system-in-package memory module 800 includes a parallel-to-serial bus-programmable interleave unit 8022, wherein the parallel-to-serial-bank bus-programmable interleave unit 8022 can be connected in a parallel-to-serial series. The reconfigurable bus bar 8024 (for example, a busbar of 128, 256 or more bit widths) between the programmable intermediation unit 8022 and the memory circuit 804 accesses the memory circuit 804 and converts the wide bus data to a high speed string. List of bus data. In addition, the parallel to serial bus bar programmable interposer 8022 can transmit the high speed concatenated bus bar data to the non-memory circuit 802 through the high speed serial bus bar 8026. The mode register in the parallel-to-serial bus-programmable interleave unit 8022 can reconstruct the memory channel, granularity, power consumption, and data width of the memory circuit 804 in a relatively fast round-trip time. The memory circuit 804 can be viewed as a "virtual external cache memory." For example, when four embedded DRAM chips having a memory depth of 512M and a busbar width of 32 bits are stacked in the memory circuit 804, the memory circuit 804 (virtual external cache memory) can be The content of the mode register in the parallel-to-serial bus bar programmable interleave unit 8022 is set to have a memory depth of 1 G and a bus bar width of 64 bits or a memory depth of 512 M and a bus bar width of 128 bits. Virtual external cache memory.

Referring to FIG. 9, FIG. 9 is a schematic diagram showing a system-in-package memory module 900 having a memory according to a tenth embodiment of the present invention. As shown in FIG. 9, the parallel-to-serial bus-programmable interleave unit 9022 includes a mode register 9102, a configuration circuit 9104, a clock generator 9106, and a parallel/serial controller 9108. The mode register 9102 can be set by the non-memory circuit 902 (central processing unit), and the configuration circuit 9104 can control and reconstruct between the memory circuit 904 and the configuration circuit 9104 according to the contents of the mode register 9102. Reconfigurable busbar 9024. For example, when the memory circuit 904 is four embedded DRAM chips whose memory depth is 512M and the bus width is 32 bits, the memory circuit 904 is interposed. The bus width of the reconfigurable bus bar 9024 with the configuration circuit 9104 can be set to 32 bits, 64 bits or 128 bits, and the address width thereof can be set correspondingly respectively. It is 2G, 1G or 512M.

As shown in FIG. 9, the configuration circuit 9104 includes an input/output width controller 91042, an output unit 91044, and an input unit 91046. The input/output width controller 91042 can access the contents of the mode register 9102 and configure the reconfigurable bus bar 9024 between the memory circuit 904 and the configuration circuit 9104. Therefore, the present invention can realize a configuration of different bus bar widths between the memory circuit 904 (virtual external cache memory) and the non-memory circuit 902. For example, in one embodiment of the invention, the busbar width of the reconfigurable busbar 9024 is set to M bits and the voltage swing across the reconfigurable busbar 9024 (between the logic potential "1" signal and The voltage difference between the logic potential "0" signals is set to 1.8V, and the output unit 91044 in the configuration circuit 9104 receives the M-bit data of the memory circuit 904 (virtual external cache memory) and generates according to the clock. The first clock signal generated by the device 9106 simultaneously outputs the M-bit data to the parallel/serial controller 9108. For energy saving purposes, the output unit 91044 can reduce the voltage swing of the M-bit data from 1.8V to 1.2V (or lower) and generate M-bit data with a voltage swing of 1.2V and pass between parallel/serial A reconfigurable busbar 9026 between the controller 9108 and the configuration circuit 9104 is passed to the parallel/serial controller 9108. The parallel/serial controller 9108 receives the parallel M-bit data having a voltage swing of 1.2 V, and converts the parallel M-bit data having a voltage swing of 1.2 V according to the second clock signal generated from the clock generator 9106. A set of serial data conforming to a high-speed serial bus communication protocol (such as a Universal Serial Bus (USB) 3.0 communication protocol or a Peripheral Component Interconnect Express (PCIe) communication protocol) And transmitting the set of serial data to the non-memory circuit 902 (central processing unit) via the high speed serial bus 9090.

On the other hand, the non-memory circuit 902 (central processing unit) can transmit a set of high speed serials. The material (for example, the data of the universal serial bus 3.0 or the data of the high-speed peripheral device interconnection interface) to the parallel/serial controller 9108 of the parallel-to-serial bus programmable programmable unit 9022, and then converted by the parallel/serial controller 9108 The high-speed serial data of the group is parallel M-bit data with a voltage swing of 1.2V. The parallel/serial controller 9108 transmits parallel M-bit data having a voltage swing of 1.2V to the input unit 91046 through the reconfigurable bus bar 9026, and the input unit 91046 can increase the voltage swing of the parallel M-bit data from 1.2V. M to 1.8V with a voltage swing of 1.8V through a reconfigurable busbar 9024 between the parallel-to-serial bus-programmable interposer 9022 and the memory circuit 904 (virtual external cache) The bit data is to the memory circuit 904 (virtual external cache memory).

Referring to FIG. 10, FIG. 10 is a schematic diagram showing a system-in-package memory module 1000 having a memory according to an eleventh embodiment of the present invention. As shown in FIG. 10, a resin (or other encapsulating material) 1002 can be embedded in the space between the memory circuit 1004 and the substrate 1006. Additionally, a resin 1008 can be disposed at the edge of the non-memory circuit 1010 to seal the edges of the non-memory circuit 1010.

Referring to FIG. 11, FIG. 11 is a schematic diagram showing a system-in-package memory module 1100 having a memory according to a twelfth embodiment of the present invention. As shown in FIG. 11, a resin (or other encapsulating material) 1102 can enclose the non-memory circuit 1104 and the memory circuit 1106.

Referring to FIG. 12, FIG. 12 is a schematic diagram showing a system-in-package memory module 1200 having a memory according to a thirteenth embodiment of the present invention. As shown in FIG. 12, a first heat sink 1202 is coupled to the non-memory circuit 1204 to accelerate heat dissipation of the non-memory circuit 1204, and a second heat dissipating material 1206 is coupled to the memory circuit 1208 to accelerate the memory circuit. The heat dissipation of 1208, wherein the second heat dissipation material 1206 is a thermal paste.

Referring to FIG. 13A, FIG. 13A is a schematic diagram showing a system-in-package memory module 1300 having a memory according to a fourteenth embodiment of the present invention. As shown in FIG. 13A, the additional memory 1302 covers a system-in-package memory module 1400 having a memory, and the structure of FIG. 13A is called a package on package (POP). . As shown in FIG. 13A, the additional memory 1302 is a conventional dynamic random access memory or a stacked dynamic random access memory. In FIG. 13A, the memory circuit 1304 is an external cache memory of the non-memory circuit 1306 in the system-in-package memory module 1400, and an additional memory 1302 can be used as the system-level package memory module 1400. The main memory circuit of the internal non-memory circuit 1306. In addition, as shown in FIG. 13A, there is an electrical contact 1308 between the additional memory 1302 and the system-in-package memory module 1400. In addition, as shown in FIG. 13B, the electrical contacts 1308 extend through the system-in-package memory module 1400.

In summary, the system-in-package memory module with memory provided by the present invention is an integrated memory circuit (embedded dynamic random access memory), a non-memory circuit (logic circuit), and a substrate at the system level. Within the package, the present invention can reduce the area of the system-in-package memory module. In addition, since the system-in-package memory module of the present invention can be customized to accommodate different memory circuits (embedded dynamic random access memory) and non-memory circuits (logic circuits), the system of the present invention Level-package memory modules have optimized performance, efficiency, or cost.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

400‧‧‧System-level package memory module

402‧‧‧ memory circuit

404‧‧‧Non-memory circuits

406‧‧‧Substrate

Claims (23)

A system-in-package memory module having a memory, the system-level package memory module comprising: a cache memory circuit; a memory controller; a memory circuit; a substrate, wherein the cache memory circuit, the memory controller and the memory circuit are co-packaged on the substrate, and the cache memory circuit and the memory controller are formed on the same semiconductor wafer The memory controller has at least one of dynamically changing an operating voltage, an operating frequency, and a bus bar width of the system-in-package memory module. The system-in-package memory module of claim 1, wherein the cache memory circuit, the memory controller, and the memory circuit are respectively disposed on a substrate or stacked on each other Above the substrate. The system-in-package memory module of claim 2, wherein the same semiconductor wafer is a germanium wafer fabricated according to a complementary metal-oxide-semiconductor (CMOS) process. The system-level package memory module of claim 1, wherein the cache memory circuit is a static random access memory (SRAM) or a dynamic random access memory (Dynamic Random Access Memory). Memory, DRAM), and the memory circuit is a dynamic random access memory, or a plurality of dynamic random access memories assembled or stacked together, and the operating speed or bandwidth of the cache memory circuit is greater than The operating speed or bandwidth of the memory circuit. The system-level package memory module of claim 1, further comprising: a first reconfigurable bus bar, wherein the memory controller accesses the memory circuit through the first reconfigurable bus bar and a cache memory circuit; and a second reconfigurable bus, wherein the memory controller transmits data to the external circuit or receives data of the external circuit through the second reconfigurable bus. The system-level package memory module of claim 5, wherein the memory controller is configured to access the cache memory circuit or the memory circuit according to an instruction of the system-level package memory module Data for correcting data errors stored in the cache memory circuit or the memory circuit for dynamically changing the bus bar width, memory depth, voltage swing or operating frequency of the first reconfigurable bus bar, Or to dynamically change the busbar width, memory depth, voltage swing or operating frequency of the second reconfigurable busbar. The system-in-package memory module of claim 1, wherein the memory circuit is disposed on the cache memory circuit and electrically connected to the cache memory through a through-silicon via (TSV) Body circuit. A system-in-package memory module having a memory, the system-level package memory module comprising: a non-memory circuit; a memory controller; a memory circuit; and a substrate comprising a hollow space The memory circuit is configured to electrically connect the non-memory circuit, wherein the non-memory circuit, the memory controller and the memory circuit are co-packaged on the substrate, and the memory circuit and the memory are controlled Device is formed On the same semiconductor wafer. The system-in-package memory module of claim 8, wherein the active device region of the non-memory circuit is electrically connected to the substrate through a wire-bond, and the memory circuit is convex through the face-to-face The block structure electrically connects the non-memory circuit. The system-in-package memory module of claim 8, wherein the active device region of the non-memory circuit is electrically connected to the substrate through a face-to-face bump structure, and the memory circuit is through a direct twinned via and Another face-to-face bump structure electrically connects the non-memory circuit. A system-in-package memory module having a memory, the system-in-package memory module comprising: a non-memory circuit having a first portion and a second portion; a substrate having a window and the substrate electrically connected to the second portion of the non-memory circuit; and a memory circuit disposed on the window of the substrate and electrically connected to the first portion of the non-memory circuit; wherein there is no between the memory circuit and the substrate A direct metal connection, a gap exists between the memory circuit and the substrate, and the gap is filled with resin. A system-in-package memory module having a memory, the system-in-package memory module comprising: a non-memory circuit having a first portion and a second portion, wherein the non-memory circuit comprises a plurality of first An electrical contact and a plurality of second electrical contacts, and the plurality of first electrical contacts and the plurality of second electrical contacts are respectively disposed in the first portion and the second portion of the non-memory circuit; a memory circuit having a plurality of third electrical contacts disposed on one side thereof; and a substrate having a plurality of fourth electrical contacts disposed on one side thereof and a plurality of fifth electrical contacts on the other side thereof; wherein the plurality of first electrical contacts electrically connect the plurality of third electrical contacts a point for electrically connecting the memory circuit to the non-memory circuit, the plurality of second electrical contacts electrically connecting the plurality of fourth electrical contacts to electrically connect the substrate to the non-memory circuit, and the substrate and the memory The circuit is electrically connected to the same side or different sides of the non-memory circuit; wherein there is no direct metal connection between the memory circuit and the substrate. The system-level package memory module of claim 12, wherein the plurality of first electrical contacts, the plurality of second electrical contacts, the plurality of third electrical contacts, and the plurality of fourth electrical connections The material of the point or the plurality of fifth electrical contacts comprises tin or copper. The system-in-package memory module of claim 11 or 12, wherein the memory circuit is a dynamic random access memory or a plurality of dynamic random access memories assembled or stacked together, the non-memory The circuit is a logic circuit. The system-level package memory module of claim 11 or 12, further comprising: a memory controller for accessing the non-memory circuit or the memory according to an instruction of the system-level package memory module The data of the circuit is used to correct data errors stored in the non-memory circuit or the memory circuit, or to dynamically change the operating voltage, operating frequency or bus width of the system-in-package memory module. The system-in-package memory module of claim 11 or 12, wherein the non-memory circuit comprises a plurality of cores and each core comprises at least one first cache memory, and an additional one of the plurality of cores The second cache memory shared by each core in the middle. The system-level package memory module of claim 11 or 12, further comprising: a parallel-to-serial bus-strip programmable intermediation unit; a first reconfigurable bus bar coupled to the parallel-to-serial-string confluence Between the programmable intermediation unit and the memory circuit, wherein the first reconfigurable bus bar is a parallel bus bar; and a second reconfigurable bus bar coupled to the parallel interleaving bus bar programmable intermediaries Between the unit and the non-memory circuit, wherein the second reconfigurable bus bar is a serial bus bar; wherein the first reconfigurable bus bar has a bus width or an address width The bus bar width or memory depth that is dynamically changed or the second reconstructed bus bar can be dynamically changed. The system-in-package memory module of claim 11 or 12, further comprising: a resin for embedding a space between the memory circuit and the substrate, and being disposed at an edge of the non-memory circuit to seal the non- The edge of the memory circuit. The system-in-package memory module of claim 11 or 12, further comprising: a resin for encapsulating the non-memory circuit and the memory circuit. The system-level package memory module of claim 11 or 12, further comprising: a first heat sink coupled to the non-memory circuit to accelerate heat dissipation of the non-memory circuit; and a second heat dissipation material coupled Connected to the memory circuit to accelerate heat dissipation of the memory circuit. The system-in-package memory module of claim 20, wherein the second heat dissipating material is a thermal paste. The system-level package memory module of claim 11 or 12, further comprising: An additional memory for covering the non-memory circuit, the memory circuit and the substrate, the additional memory and the package covering the non-memory circuit and the memory circuit having a plurality of electrical contacts, And the additional memory is a dynamic random access memory or a stacked dynamic random access memory. The system-in-package memory module of claim 22, wherein the plurality of electrical contacts extend through a package encapsulating the non-memory circuit and the memory circuit.