JPS6152765A - One chip microcomputer - Google Patents

Abstract

PURPOSE:To access to ROM, RAM and I/O freely from CPU connected from the external part through a two-way buffer by separating CPU with a bus separating switch. CONSTITUTION:A bus control part 15 is operated by a request signal from CPU21, a bus separating switch 12 is opened, two-way buffers 13 and 14 are operated as the two-way buffer, CPU21, ROM2, RAM3 and an external memory 11 are connected to common buses 5-7 and controlled by CPU21. In controlling of CPU1, the bus separating switch 12 is closed by the bus control part 15, and two-way buffers 13 and 14 prevent an output from the outside and CPU21 is separated.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention provides a system that combines a CPU and a ROM in one package.
(read-only memory), RAM (random access memory), data output unit (hereinafter abbreviated as I10), and a control signal bus, address bus, and data bus that interconnect these. It concerns chip microcomputers.

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of a conventional one-chip microcomputer. In the figure, tll is a CPU, (2
1 is ROM, +31 is Makoto, (41 is L, (51 is control signal bus, (6) is address bus, (7) is data bus, +81, 19) are each unidirectional bus buffer, LIOI is bidirectional. The bus buffer, ttn, is external memory.

A conventional one-chip microcomputer has 111, 121, 131, +41 in a single IC package.
, +51, 161.

+71, +81, +91, tl(l117
) part is built in and the Hasbuff 7181.

+91, (101k can be connected to external memory, and Ilo I416 can be used to transfer data to and from external circuits.

Since the operation of the device shown in FIG. 2 is well known, a brief explanation will be given below.
Output all address signals to ROM +21, RA
The control signal bus (5) sends 18 control signals that specify the addresses of M+31 and IO+41 and all data transfer directions.
i1t controls data reading and writing. In addition, the program is sequentially read out from (2), data processing determined by the program is executed, and intermediate data and processing result data are stored in t RAM +31.

For the insufficient capacity of ROM +21 and RAM +31, external memory u11 is used via buffer +81, t9+, and tlG.

[Problem that the invention seeks to solve]

The conventional device as described above is inconvenient when two one-chip microcomputers are connected to each other. Figure 3 is a block diagram showing the interconnection of two one-chip microcomputers with similar configurations.
00) and (200) are one-chip microcomputers, respectively, and [11, 121.

+31 and +41 indicate all the same symbols and minus symbols in Figure 2, (21), (22), (23), (2
4) r/″i ill, I21, i3 respectively
＋.

(CPU, ROM, RAM, corresponding to 4;
It is Ilo.

With such a connection, it is impossible for the CPU (21) to use the program stored in the HROM +21, and the microcomputer (200)
Referring to (reading) or changing (performing V-input) the contents of +31 is done under the control of the CPU (+1117) according to the program sequence.
/(I10 +4 after data transfer between J +41
1 and Ilo (24), it takes time, and referencing and changing a large amount of RA+VI data has the problem of reducing system throughput.

[Means for solving problems]

In this invention, a one-chip microcomputer CPU
K system? A general bus isolation switch that can be disconnected from the Ml signal bus, address bus, and data bus was installed, and all bidirectional buffers were opened to these buses so that other CPU's could be connected.

[Effect]

When the CPUs are connected to their respective buses by the bus isolation switch, this one-chip microcomputer operates in the same way as a conventional one.When the CPU is disconnected by the bus isolation switch, it is possible to connect other CPUs externally. ROM, RAM, and Ilo can be freely accessed from other CPUs via the bidirectional bus buffer.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention.
The same reference numerals as in Figures and Figure 3 indicate the same or equivalent parts, Oa
is a bus separation switch, (131 is a 1ljll V signal bus bidirectional buffer, (1→ is an address bus bidirectional buffer, α is a bus control unit, and (21) corresponds to the same reference numerals in Fig. 3. The CPU (21) is connected to another one-chip microcomputer (200) (not shown in FIG. 1) via a bidirectional buffer α3.α→, (IOIK-connected and a bus It is configured to be able to send a control signal to the control section of the control section 09.

A one-chip microcomputer (100) is a CPU (
1) In the state of operation under the control of the bus control unit (to)
The bus isolation switch Qa is closed under the control of , and the bidirectional buffer (131, α4) is controlled to block input from the outside, that is, operates as a unidirectional buffer,
The device shown in FIG. 1 operates similarly to the device shown in FIG.

The bus controller αe receives a request signal from the CPU (21).
operates, the bus isolation switch αa opens, and the bidirectional buffer (131, tl→ starts to operate as a bidirectional buffer), this system operates as follows: CPU (21), R(J
M I21, along m1 (3).

Ilo +41, external memory (11) is on a common bus +
It becomes a system connected by 51, , +61, and +71, and is processed under the processing of the CPU (21).

In addition, in the above embodiment, from the CPU (21) to the RUM 1
2+.

When accessing RAM +31, all are shown, but like a display LSI in external memory mode, a one-chip microcomputer that outputs an address signal to all external memories, reads out the data at that address, and displays all of it, can be used with other CPUs.
The same effect money can be obtained when controlling from.

〔Effect of the invention〕

As explained above, this invention has a simple structure in which all the bus separation switches etc.
, RAIVI, Ilo, etc., making it possible to easily interconnect one-chip microcomputers and increase system throughput.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a block diagram showing a conventional one-chip microcomputer.
FIG. 2 is a block diagram showing mutual connection of two one-chip microcomputers. In the figure, +11 and (21) Vi, respectively CPt
J, 12+ is 1 (CM, (31 is RAIVI, (41 is Ilo, +51 U system signal bus, (61 is address bus, (7) is data bus, tlol, (131
, (b) are bidirectional buffers, ul) is an external memory, 0 is a bus separation switch, and α9 is the bus control side 1 part. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of Claim] A one-chip microcomputer comprising a CPU, ROM, RAM, data input/output section, and a control signal bus, address bus, and data bus for interconnecting these in one IC package, A bus isolation switch provided to separate the CPU from the control signal bus, address bus, and data bus; and a bus separation switch that connects the control signal bus, address bus, and data bus with the external circuits, respectively. each bidirectional bus buffer provided for transmission; a bus control unit that controls opening and closing of the bus isolation switch based on an external control signal and correspondingly controls the signal transmission direction of each of the bidirectional bus buffers; A one-chip microcomputer characterized by having.