JP2005276033A - Multiprocessor module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain miniaturization and acceleration of a multiprocessor module. <P>SOLUTION: In a multiprocessor module packaging first and second processor chips on the same substrate, the first and second processor chips have the same structure, input/output ports for performing inputting/outputting between the processor chips are disposed on one side of each processor chip in a concentrated manner, and the first and second processor chips are packaged on said substrate, while confronting one side of each processor chip with each other. Particularly, each of the input/output ports is comprised of a main bus to which a bus arbiter is connected, a sub-bus connected with said main bus via a shared memory, and the main bus of the first processor chip is connected with the sub-bus of the second processor chip. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a multiprocessor module in which a plurality of processor chips are mounted on the same substrate.

  In response to the recent demand for smaller, faster, and higher performance electronic devices, multiprocessor modules have been developed that can process a large amount of data in a short time by simultaneously driving a plurality of processor chips.

  This multiprocessor module has a structure in which a plurality of processor chips are mounted on the same substrate.

The conventional multiprocessor module is designed to satisfy the specifications required for the multiprocessor module by using a combination of a plurality of types of processor chips that have already been developed as a single processor.
JP-A-5-250315

  However, in the existing processor chip, the position of the input / output port is different for each processor chip, and the input / output ports are distributed and arranged in each processor chip. If the existing processor chips are used in combination, the length of the wiring connecting the input / output ports of each processor chip becomes longer, thereby reducing the size and speed of the multiprocessor module. Could become difficult.

  In particular, when the bus provided inside the processor chip is used as an input / output port for connecting the processor chips, the bus arbiter is connected to the internal bus of each processor chip. As a result, the bus arbiters interfere with each other, and the buses cannot operate independently, so that there is a possibility that the transfer efficiency is lowered and the performance is lowered.

  Therefore, in the present invention according to claim 1, in the multiprocessor module in which the first and second processor chips are mounted on the same substrate, the first and second processor chips have the same structure, and each processor chip The first and second processor chips are mounted on the substrate in a state where input / output ports for performing input / output between the processor chips are concentrated on one side, and the input / output ports face each other. It was to be.

  According to a second aspect of the present invention, in the first aspect of the present invention, the input / output port includes a main bus connected to a bus arbiter and a sub bus connected to the main bus via a shared memory. The main bus of the first processor chip is connected to the sub-bus of the second processor chip.

  Further, in the present invention according to claim 3, in the present invention according to claim 1 or 2, the input / output port has the input pad portion and the output pad portion arranged on both sides of the boundary line, respectively. It was to be.

  And in this invention, there exists an effect described below.

  That is, in the present invention according to claim 1, in the multiprocessor module in which the first and second processor chips are mounted on the same substrate, the first and second processor chips have the same structure, and An input / output port for performing input / output between processor chips is concentrated on one side, and the first and second processor chips are mounted on the substrate with the input / output ports facing each other. As a result, the length of the wiring connecting the input / output ports of the processor chip can be shortened, the influence of wiring resistance and wiring capacity can be reduced, and the speed of the processor module can be increased. The mounting density of the processor chip can be improved and the processor module can be downsized.

  Further, by making the processor chips have the same structure, it is possible to reduce the time, labor and cost required for the development and manufacture of the processor chips.

  According to the second aspect of the present invention, the input / output port includes a main bus connected to the bus arbiter and a sub bus connected to the main bus via a shared memory, and the main bus of the first processor chip. And the sub-bus of the second processor chip are connected to each other, so that the bus arbiters provided in each processor chip can be prevented from interfering with each other, and the bus can operate independently. Increase efficiency and improve performance.

  In the present invention according to claim 3, since the input pad portion and the output pad portion are arranged on both sides of the boundary line, the first processor chip and the second processor chip are provided. By arranging them on the substrate in a rotationally symmetric positional relationship, the wiring between the input and output ports can be formed in a straight line, and the wiring length can be minimized.

  The multiprocessor module according to the present invention is obtained by mounting the first and second processor chips having the same structure on the same substrate.

  The first and second processor chips having the same structure concentrate the input / output ports for performing input / output between the first processor chip and the second processor chip on one of the four sides. It is arranged.

  This input / output port is composed of a main bus connected to a bus arbiter that performs arbitration when the bus is used, and a sub-bus connected to the main bus via a shared memory.

  In the multiprocessor module according to the present invention, the first and second processor chips are mounted on the substrate in a state where the sides on which the input / output ports are arranged are opposed to each other. The bus and the sub bus of the second processor chip are connected, and the sub bus of the first processor chip and the main bus of the second processor chip are connected.

  Thus, in the multiprocessor module according to the present invention, the input / output ports are concentrated on one side of each processor chip and are mounted on the same substrate with the input / output ports facing each other. In addition, the length of the wiring connecting the input / output ports of the processor chip can be shortened.

  As a result, when data is transferred between the input / output ports of the processor chip, the influence of wiring resistance and wiring capacity can be reduced and the data transfer speed can be improved. Can be achieved.

  Further, since the processor can be mounted in a state where the processors are close to each other on the substrate by reducing the wiring length, the mounting density of the processor chips can be improved, and the size of the processor module can be reduced.

  Further, since the processor chips have the same structure, it is not necessary to develop and manufacture a plurality of types of processor chips, and the time, labor, and cost required for developing and manufacturing the processor chips can be reduced.

  In particular, the input / output port is composed of a main bus to which a bus arbiter is connected and a sub bus connected to the main bus via a shared memory, and connects the main bus of the first processor and the sub bus of the second processor. In this case, it is possible to prevent interference between the bus arbiters provided in each processor chip, and to operate the multiprocessor module satisfactorily.

  When the input pad portion and the output pad portion are arranged on both sides of the boundary line, the first processor chip and the second processor chip are arranged on the substrate in a rotationally symmetric positional relationship. Thus, the wiring between the input / output ports can be formed in a straight line, and the wiring length can be minimized.

  The specific configuration of the multiprocessor module according to the present invention will be described below with reference to the drawings.

  As shown in FIG. 1, the multiprocessor module 1 according to the present invention has a first processor chip 3 and a second processor chip 4 having the same structure mounted on the same semiconductor substrate 2 to form a semiconductor. The first processor chip 3 and the second processor chip 4 are connected using the wiring formed on the substrate 2.

  As shown in FIG. 2, the first and second processor chips 3 and 4 form a processor 5 therein, and a main bus 6 is connected to the processor 5. A bus arbiter 7 is connected to the main bus 6. doing.

  The first and second processor chips 3 and 4 connect the first peripheral 8 to the processor 5 via the main bus 6, and connect the second peripheral 9 to the processor 5 and the main bus 6 and the bridge 10. It is connected to the internal bus 11.

  Further, the first and second processor chips 3 and 4 connect one port of the two-port shared memory 12 functioning as a bus slave to the main bus 6 and connect the sub-bus 13 to the other port of the shared memory 12. Is connected.

  Moreover, the first and second processor chips 3 and 4 form a port of the main bus 6 on one side (upper side in FIG. 2) of one of the four sides, while the other side (FIG. 2) on the same side. The port of the sub-bus 13 is formed on the lower side), whereby the input / output port 14 consisting of the port of the main bus 6 and the port of the sub-bus 13 is concentrated on one of the four sides, The input / output port 14 is mounted on the semiconductor substrate 2 with the sides facing each other.

  The multiprocessor module 1 connects the port of the main bus 6 of the first processor chip 3 and the port of the sub-bus 13 of the second processor chip 4 via the bus wiring 15 formed on the semiconductor substrate 2. The port of the sub-bus 13 of the first processor chip 3 and the port of the main bus 6 of the second processor chip 4 are connected via a bus wiring 16 formed on the semiconductor substrate 2.

  The multiprocessor module 1 configured as described above performs data communication between the first processor chip 3 and the second processor chip 4 as follows. Of course, the data communication method between the first processor chip 3 and the second processor chip 4 is not limited to the following method.

  First, the first processor chip 3 writes data from the processor 5 to the shared memory 12 via the main bus 6. At this time, the use of the bus is arbitrated by the bus arbiter 7 provided in the first processor chip 3.

  Next, the first processor chip 3 transmits an interrupt signal to the second processor chip 4.

  Next, the second processor chip 4 having received the interrupt signal sends the processor 5 from the shared memory 12 of the first processor chip 3 to the main bus 6 and the bus wiring 16 of the second processor chip 4 and the first processor chip. 3 through the sub-bus 13. At this time, use of the bus is arbitrated by the bus arbiter 7 provided in the second processor chip 4.

  Next, the second processor chip 4 transmits an interrupt signal to the first processor chip 3.

  As described above, the multiprocessor module 1 is provided with the main bus 6 to which the bus arbiter 7 is connected to each of the processor chips 3 and 4 and the subbus 13 to which the bus arbiter 7 is not connected. Since the sub-bus 13 is connected via the shared memory 12 and the main bus 6 of one processor chip 3 and the sub-bus 13 of the other processor chip 4 are mutually connected, bus contention during data communication Will not occur, and data communication can be performed smoothly.

  The multiprocessor module 1 according to the present invention is not limited to the above configuration shown in FIG. 2, and a plurality of processor chips 18 may be connected in series like the multiprocessor module 17 shown in FIG. Alternatively, a plurality of processor chips 21 may be connected in parallel to one processor chip 20 as in the multiprocessor module 19 shown in FIG. 3 and 4, the same reference numerals are given to components having the same functions as those of the multiprocessor module shown in FIG. 2.

  Further, as shown in FIG. 5, the input pad portions 6i-1, 6i-2, 6i-3 of the main bus 6 and the input pad portions 13i-1, 13i-2, 13i of the sub-bus 13 are arranged on one side of the boundary line L. -3 and the output pad portions 6o-1, 6o-2, 6o-3 of the main bus 6 and the output pad portions 13o-1, 13o-2, 13o-3 of the sub-bus 13 on the other side of the boundary line L. And the input pad sections 6i-1, 6i-2, 6i-3, 13i-1, 13i-2, 13i-3 and the output pad sections 6o-1, 6o-2, 6o-3, 13o -1, 13o-2, and 13o-3 can be arranged on both sides of the boundary line L, respectively. In this case, by arranging the first processor chip 3 and the second processor chip 4 on the substrate in a rotationally symmetrical positional relationship, the wiring between the input and output ports can be formed in a straight line, and the wiring length is minimized. Can be.

The perspective view which shows the external appearance of the multiprocessor module which concerns on this invention. The block diagram which shows a multiprocessor module. The block diagram which shows another multiprocessor module. The block diagram which shows another multiprocessor module. Explanatory drawing which shows another multiprocessor module.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Multiprocessor module 2 Semiconductor substrate 3 1st processor chip 4 2nd processor chip 5 Processor 6 Main bus 7 Bus arbiter
12 Shared memory
13 Subbus
14 I / O ports

Claims (3)

In a multiprocessor module in which the first and second processor chips are mounted on the same substrate,
The first and second processor chips have the same structure, and input / output ports for performing input / output between the processor chips are concentrated on one side of each processor chip, and the input / output ports are opposed to each other. A multiprocessor module, wherein the first and second processor chips are mounted on the substrate in a state of being mounted.   The input / output port includes a main bus connected to a bus arbiter and a sub bus connected to the main bus via a shared memory, and the main bus of the first processor chip and the sub bus of the second processor chip. The multiprocessor module according to claim 1, wherein   3. The multiprocessor module according to claim 1, wherein the input / output port includes an input pad portion and an output pad portion arranged on both sides of a boundary line. 4.

Images