JP2551342B2 - Dual microprocessor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual microprocessor device, and more particularly to a dual microprocessor device for distributed processing.

[0002]

2. Description of the Related Art Recently, a processing device using a microprocessor is required to have a higher processing capability. This demand sometimes extends beyond the processing power of a single microprocessor. To solve this problem, many multiprocessor systems using a plurality of CPUs have been proposed. An example of such a system is the dual processor system described in JP-A-61-250223. The system comprises two processors, each processor provided with memory. These memories are connected to each other by a bus and hold the same data. The dual processor system operates by selecting either the first mode or the second mode in response to a predetermined condition. In the first mode, both processors are active and perform their respective tasks independently. In the second mode, one processor is inactive and the other is active, and the active processor is
The selected task of the respective tasks is executed. In this way, the processing capacity and reliability are improved.

[0003]

In the above-mentioned conventional dual microprocessor system, it is necessary to mount two microprocessors and peripheral circuit components on the substrate, which requires twice the area, and the microprocessor is also required. The more complicated the function of, the larger the number of terminals, the larger the occupied area, and the problem that a multilayer board must be used for wiring. It is an object of the present invention to provide a dual microprocessor device which allows each microprocessor to operate independently, has a small mounting area, and is suitable for load balancing processing.

[0004]

A dual microprocessor device of the present invention comprises a first chip on which a first microprocessor is formed and the same components as the first microprocessor. Has a corresponding component of the first microprocessor and a second chip on which a second microprocessor is arranged which is arranged symmetrically with respect to each other, and the first and second chips are ,
The back surfaces are attached to each other and fixed to the IC substrate.

The first and second microprocessors respectively include first and second CPUs and first and second caches in which programs to be executed by the respective CPUs are stored.
A memory function and an external memory in which a program to be read into each cache memory means is access-controlled via an external bus; and a function for respectively controlling access to the first and second cache memory means First and second external memory access control means,
It has first and second shared memory means which are accessed according to the access requests of the first and second CPUs.

The first and second microprocessors further include an external bus use right for preferentially using the external bus and a shared memory for preferentially executing access to the first and second shared memory means. It has a priority setting means for setting both the access right and the other to either one of the first and second microprocessors.

[0007]

Since the two plane-symmetrical microprocessors are attached back to back, the processing capacity is improved and the mounting area is reduced. Since each microprocessor has its own CPU and its own peripheral device, it can operate independently, and for the parts that conflict with each other due to their independent operation, priority is set for their use to avoid conflict. can do. Since the two microprocessors each have a shared memory means that can be accessed by their respective CPUs, each shared memory means is used for independent operation of each microprocessor as well as for mutual interaction between the microprocessors. Can be used for communication. As described above, the dual microprocessor device of the present invention is capable of independent operation and is equipped with the mutual communication means, and thus is suitable for load distribution processing.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.
I do. FIG. 1 shows a dual microprocessor device of the present invention.
FIG. 2 is a perspective view of one embodiment. FIG. 2 shows the dual-purpose device of the present invention.
FIG. 3 is a block diagram of an embodiment of an icroprocessor device.
In FIG. 1, a mask pattern group having plane symmetry is manufactured.
Attached microprocessor chips A and B to each other
And a dual microphone bonded to the IC substrate
The external appearance of the processor is shown, and the correspondence between chips A and B
The terminals to be connected are connected by the bonding terminal TE.
You. One pair of bonding terminals
Terminal TE ₁ , TE₂ (TE₂ Is not shown) is after
As mentioned, microprocessor master / slave
It is used to specify the operation, which is specified in this implementation.
In the example, the switch of the pair of bonding terminals
Terminal TE connected to the Rave microprocessor₂ To
This is done by making a ground connection (see FIG. 2).

In FIG. 2, microprocessors 1 and 2 are provided.
Is manufactured so that its components are located in plane symmetry. In the figure, black circles indicate the terminals of the microprocessor that are mutually connected by the bonding terminals. C
The PUs 10 and 20 perform arithmetic operations / controls according to programs stored in the cache memories 11 and 21. The external memory (EM) access control circuits 12 and 22 are CPUs.
In order to read an external memory (not shown) in which a program to be executed by 10 or 20 is stored via the external bus 300, read control of the external memory is performed and the read program is cache memory 11 , 2
Write control for writing 1 is performed. Two external memory access control circuits 12 and 22 form one external bus 3
The conflict caused by using 00 is avoided by giving priority to one microprocessor as the master processor and giving the bus use right to the external memory access control circuit belonging to the master processor.
Hereinafter, a microprocessor to which no priority is given is referred to as a slave processor.

As described above, the dual microprocessor device of the present invention constitutes a distributed processing system for load balancing. Therefore, a communication system for communicating the processing result executed by one microprocessor to the other microprocessor is provided. The communication system of the present embodiment is configured by the shared memories 16 and 26 provided in the respective microprocessors, and each shared memory 1
6, 26 can be accessed by both CPUs 10 and 20. The access conflict that occurs when both CPUs 10 and 20 access at the same time is
This is avoided by giving priority to the access request from the master processor. Each shared memory 1
6 and 26 are structurally dual port memories (D
PM), the communication memories 13 and 23 and the DPM control circuit 1
4, 24. DPM control circuit 14
When there is a write or read request from the CPU 10, the CPU controls the communication memory 13 to write or read information specified by the CPU 10. Similarly, D
When there is a writing or reading request from the CPU 20, the PM control circuit 24 controls the communication memory 23 to write or read the information specified by the CPU 20.

Communication between the CPUs is achieved by reading the communication memory on the transmitting side and writing the communication memory on the receiving side in parallel. CPU20 is C
When the transmission request is sent to the PU 10, the DPM control circuit 14
The information specified by the CPU 20 is read from the communication memory 13 onto the internal bus 100, and the DPM control circuit 24 writes the information in the communication memory. Similarly, when there is a transmission request from the CPU 10, the DPM control circuit 24
The information specified by the PU 10 is read from the communication memory 23 onto the internal bus 200, and the DPM control circuit 14 writes the information into the communication memory 13. The information stored in the communication memory and transmitted / received by the inter-CPU communication includes the identification number of the job executed by each CPU, the address of the external shared memory (not shown) that stores the processing result of the job, Information such as whether or not the job execution is completed,
This is information regarding the processing result of each CPU.

The competition of access from the two CPUs 10 and 20 to the external memory and the competition of access to the shared memory are
Avoided by the priority setting circuit. The priority setting circuit comprises a + 5V power source, pull-up resistors R ₁ and R ₂ connected to the power source, and priority setting lines 104 and 204 pulled up by the pull-up resistors. , 204 has a bonding terminal TE ₁ ,
It is connected to TE ₂ . In this embodiment, the bonding terminal TE ₂ is grounded to set the microprocessor 2 as a slave processor. Respective priority setting lines 104 and 204 are connected to the priority setting signal inputs of the DPM control circuit and the external memory access control circuit. Therefore, the DPM control circuit 14 prioritizes the access request from the CPU 20 over the access request from the CPU 20 according to the logic 1 priority setting signal and the DPM control circuit 24 according to the logic 0 priority setting signal. When the external memory access control circuit 12 receives the logic 1 priority setting signal, it recognizes that its own circuit 12 has the right to use the external bus 300 and processes the access to the external memory. When the external memory access control circuit 22 receives the logic 0 priority setting signal, it recognizes that the own circuit 22 does not have the right to use the external bus 300, and obtains permission from the external memory access control circuit 12 (external memory access control). Either access the external memory (by confirming that the control circuit 12 does not have an indicator that the external bus is in use), or access the external memory via the external memory access control circuit 12. In the latter case, the slave side external memory access control circuit 22 performs external access to the master side external memory access control circuit 12
It is only transmitted to.

The interrupt signal line 301 is connected to the interrupt selection circuits 15 and 25 via bonding terminals and transmits a plurality of interrupt request signals. Interrupt selection circuit 15, 25
Compares the job assigned to each CPU 10 and 20 with the interrupt processing content indicated by the interrupt request signal, and selects an interrupt request signal other than the interrupt request signal corresponding to the job assigned to each CPU. The masking is performed and the interrupt request signal corresponding to the job is transmitted to the CPUs 10 and 20 via the signal lines 103 and 203.

In FIG. 2, the signal lines 101 and 201 are
When there is no program to be executed by the CPU 10 or 20 in the cache memory 11 or 21 or data necessary for the CPU 10 or 20 to execute the program,
A control line for transmitting an access request to the external memory from the cache memories 11 and 21 to the external memory access control circuits 12 and 22, and a program or data transmitted from the external memory to the external memory access control circuit 1
Data lines and address lines transmitted to the cache memories 11 and 21 via the lines 2 and 22. External bus 300
Is a bus composed of address lines, data lines, and control lines. The signal lines 102 and 202 are an address line, a data line and a control line for accessing the communication memory.

Next, the operation of this embodiment will be described. First,
In order to avoid contention for use of the external buses of the first and second microprocessors and contention for access to the shared memories 16 and 26, the bonding terminal TE ₂ is grounded to set priority to the microprocessor 1. . Normally, the CPU 10 does not need to access the external memory because it operates according to the program of the cache memory 11. However, if there is no necessary program or data in the cache memory 11, the external memory access control circuit 12 Under control, the program or data is read from the external memory onto the cache memory. Similarly, since the CPU 20 operates according to the program of the cache memory 21, there is no need to access the external memory. However, if the cache memory 21 does not have the necessary program or data, the cache memory 21
Transmits an external memory access request to the slave side external memory access control circuit 22, and the slave side external memory access control circuit 22 accesses the external memory with the permission of the master side external memory access control circuit 12.
As another embodiment of this case, the cache memory 21 issues an access request to the master side external memory access control circuit 12 via the external memory access control circuit 22 and under the control of the external memory access control circuit 12. The program or data is read from the external memory to the cache memory. At this time, the slave side external memory access control circuit 22 merely transmits the external access to the master side external memory access control circuit 12. C
The jobs executed by the PUs 10 and 20 are distributed loads.
Therefore, each of the CPUs temporarily outputs information regarding the processing result executed by the CPU to the shared memory 16, 26.
Then, the CPU 10 gives priority to the reading and then reads the shared memories 16 and 26 as necessary to communicate the respective processing results.

When an interrupt request occurs, the CPU accepts the interrupt request corresponding to the job assigned to each CPU by load balancing. In this way, load distribution is achieved by causing the CPU to execute a process corresponding to each CPU according to the interrupt processing content.

[0017]

As described above, the present invention has the following effects.

1) Since two microprocessors having plane symmetry are attached back to back, the processing capacity is improved and the mounting area is reduced. 2) Since each microprocessor has its own CPU and its own peripheral device, it can operate independently. For parts that compete with each other due to their independent operation, priority is set for their use and competition occurs. Can be avoided.
3) Since the two microprocessors each have a shared memory means that can be accessed by each CPU, each shared memory means is used for independent operation of each microprocessor and between the microprocessors. It can be used for mutual communication. 4)
As described above, since the independent operation is possible and the mutual communication means is provided, it is suitable for load balancing processing.

[Brief description of drawings]

FIG. 1 is a perspective view of an embodiment of a dual microprocessor device of the present invention.

FIG. 2 is a block diagram of one embodiment of a dual microprocessor device of the present invention.

[Explanation of symbols]

1, 2 Microprocessor 10, 20 CPU 11, 21 Cache memory 12, 22 External memory (EM) access control circuit 13, 23 Communication memory 14, 24 DPM control circuit 15, 25 Interrupt selection circuit 16, 26 Shared memory 100, 200 Internal Bus 104, 204 Priority Setting Line 300 External Bus 301 Interrupt Signal Line 101, 102, 103, 201, 202, 203
Signal line TE, TE ₁ , TE ₂ Bonding terminal R ₁ , R ₂ Pull-up resistor

Claims (5)

(57) [Claims] 1. A first chip in which a first microprocessor is formed and the same constituent elements as the first microprocessor, each constituent element being mutually compatible with the corresponding constituent element of the first microprocessor. A second chip formed with a second microprocessor arranged in a plane-symmetrical position,
The back surfaces of the first and second chips are attached to each other and I
The first and second microprocessors are fixed to the C board, and the first and second CPUs respectively have first and second cache memory means for storing programs to be executed by the respective CPUs. Access control of an external memory storing a program to be read into the cache memory means via an external bus, and first and second caches
A first and a second external memory access control means having a function of respectively controlling access to the memory means, and a first and a second shared memory means accessed according to access requests of the first and second CPUs, The first and second microprocessors further have an external bus use right for preferentially using the external bus and a shared memory access right for preferentially executing access to the first and second shared memory means. A dual microprocessor device having priority setting means for setting both of them in either one of the first and second microprocessors. 2. The first cache memory means is the first cache memory means.
First cache the program to be executed by this CPU
When the memory means is not accumulating, or the first CPU
Includes means for outputting an access request to the external memory when the first cache memory means does not store the data necessary for executing the program, and the first external memory access control means sets the priority setting. When the means sets the external bus use right to the first microprocessor and the access request is issued from the first cache memory, the use of the external bus of the second external memory access control means is prohibited, When the program or the data is read from the external memory via the bus and written to the first cache memory means, and when there is no access request from the first cache memory, the external bus of the second external memory access control means is used. And the priority setting means sets the external bus use right to the second microprocessor. In the case, the first
When there is an access request from the cache memory means, the first and second shared memories are provided with means for accessing the external memory with permission from the second external memory access control means. 2. When there are simultaneous access requests from the CPUs, the priority setting means includes means for preferentially responding to the access requests from the CPUs belonging to the microprocessors that have set the shared memory access right. The described device. 3. A dual microprocessor device is a device for load balancing processing, and a program to be executed by each CPU is a program for executing a job assigned to the CPU for load balancing processing. The device according to claim 2. 4. The first and second CPUs respectively write first and second information, which is information relating to a distributed processing result executed by each, to the first and second shared memory means, and the first CPU From the second CPU to the second CPU
Is performed by reading the first information from the first shared memory means, and the communication from the second CPU to the first CPU is such that the first CPU reads the second information from the second shared memory means. The device according to claim 3, which is performed by reading. 5. The first and second microprocessors respectively have first and second interrupt selection circuits, and the first and second interrupt selection circuits are interrupted from an external device via the same bonding terminal. The apparatus according to claim 4, wherein a signal is input to transmit an interrupt request corresponding to a job assigned to each of the first and second CPUs to the first and second CPUs.