TWI474763B - Multi-layer wiring board and manufacturing method for same - Google Patents
Multi-layer wiring board and manufacturing method for same Download PDFInfo
- Publication number
- TWI474763B TWI474763B TW102103973A TW102103973A TWI474763B TW I474763 B TWI474763 B TW I474763B TW 102103973 A TW102103973 A TW 102103973A TW 102103973 A TW102103973 A TW 102103973A TW I474763 B TWI474763 B TW I474763B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- hole
- metal pattern
- substrate
- silver paste
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000010410 layer Substances 0.000 claims description 351
- 229910052709 silver Inorganic materials 0.000 claims description 202
- 239000004332 silver Substances 0.000 claims description 202
- BQCADISMDOOEFD-UHFFFAOYSA-N silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 193
- 239000000758 substrate Substances 0.000 claims description 122
- 229910052751 metal Inorganic materials 0.000 claims description 102
- 239000002184 metal Substances 0.000 claims description 102
- 239000000463 material Substances 0.000 claims description 52
- 239000000853 adhesive Substances 0.000 claims description 39
- 230000001070 adhesive Effects 0.000 claims description 39
- 239000011241 protective layer Substances 0.000 claims description 28
- 238000000059 patterning Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 230000000873 masking Effects 0.000 claims description 2
- 230000000149 penetrating Effects 0.000 claims 2
- 230000000881 depressing Effects 0.000 claims 1
- 239000002052 molecular layer Substances 0.000 claims 1
- 239000002356 single layer Substances 0.000 description 7
- 229920001721 Polyimide Polymers 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 5
- 108010053763 EC 6.4.1.1 Proteins 0.000 description 4
- 229920000106 Liquid crystal polymer Polymers 0.000 description 4
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 4
- 102100007000 PC Human genes 0.000 description 4
- 229920000139 polyethylene terephthalate Polymers 0.000 description 4
- 239000005020 polyethylene terephthalate Substances 0.000 description 4
- 239000002002 slurry Substances 0.000 description 4
- 229920001225 Polyester resin Polymers 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229920000728 polyester Polymers 0.000 description 3
- 239000004645 polyester resin Substances 0.000 description 3
- -1 polyethylene terephthalate Polymers 0.000 description 3
- 239000011148 porous material Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminum Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000003247 decreasing Effects 0.000 description 2
- 125000003700 epoxy group Chemical group 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006011 modification reaction Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- LCTONWCANYUPML-UHFFFAOYSA-N pyruvic acid Chemical compound CC(=O)C(O)=O LCTONWCANYUPML-UHFFFAOYSA-N 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N tin hydride Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 210000002381 Plasma Anatomy 0.000 description 1
- 229940076788 Pyruvate Drugs 0.000 description 1
- 229940107700 Pyruvic Acid Drugs 0.000 description 1
- 230000003292 diminished Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 230000001678 irradiating Effects 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Description
本發明有關一種線路板以及其製程方法,且特別是有關於一種多層線路板以及其製造方法。The present invention relates to a circuit board and a method of fabricating the same, and more particularly to a multilayer wiring board and a method of fabricating the same.
一般而言,多層線路板的製造過程包括,先將單層板或雙層板進行堆疊黏合以形成多層板。再對多層板進行蝕刻製程以形成多層線路板。單層板的結構包括一金屬層、一絕緣層以及一黏著層,而雙層板的結構包括兩金屬層、一絕緣層以及一黏著層。然而,利用單層板與雙層板堆疊黏合所形成的多層板會具有較大的厚度,使得所形成的多層線路板無法具有薄型化的特性。In general, the manufacturing process of a multilayer wiring board includes first stacking a single layer board or a double layer board to form a multilayer board. The multilayer board is then etched to form a multilayer wiring board. The structure of the single layer board comprises a metal layer, an insulating layer and an adhesive layer, and the structure of the double layer board comprises two metal layers, an insulating layer and an adhesive layer. However, the multilayer board formed by stacking a single layer board and a double layer board has a large thickness, so that the formed multilayer wiring board cannot have a thin profile.
本發明提供一種多層線路板,其可以達到產品薄型化的需求。The present invention provides a multilayer wiring board that can meet the demand for thinning products.
本發明提供一種多層線路板的製造方法,其用來製造上述多層線路板。The present invention provides a method of manufacturing a multilayer wiring board for manufacturing the above multilayer wiring board.
本發明提供一種多層線路板,此多層線路板包括線路基板、絕緣基板、第二孔洞、第一奈米銀導電柱、第二奈米銀導電柱、第一銀漿層、第二銀漿層、第一保護層以及第二保護層。線路基板包括基板層以及貼附於基板層上的金屬圖案層。絕緣基板位於金屬圖案層上,並包括黏著層、絕緣層以及第一孔洞。黏著層貼附於金屬圖案層上,而絕緣層貼附於黏著層上。第一孔洞貫穿絕緣基板並暴露出金屬圖案層。而第一孔洞的孔徑是從第一孔洞的開口向金屬 圖案層遞減。第二孔洞位於基板層,並且暴露出金屬圖案層。第二孔洞的孔徑是從第二孔洞的開口向金屬圖案層遞減。第一奈米銀導電柱填入第一孔洞之中,而第二奈米銀導電柱填入第二孔洞之中。第一銀漿層覆蓋絕緣層以及第一奈米銀導電柱,而第二銀漿層覆蓋基板層以及第二奈米銀導電柱。第一保護層覆蓋第一銀漿層,而第二保護層覆蓋第二銀漿層。The invention provides a multilayer circuit board comprising a circuit substrate, an insulating substrate, a second hole, a first nano silver conductive column, a second nano silver conductive column, a first silver paste layer, and a second silver paste layer a first protective layer and a second protective layer. The circuit substrate includes a substrate layer and a metal pattern layer attached to the substrate layer. The insulating substrate is located on the metal pattern layer and includes an adhesive layer, an insulating layer and a first hole. The adhesive layer is attached to the metal pattern layer, and the insulating layer is attached to the adhesive layer. The first hole penetrates the insulating substrate and exposes the metal pattern layer. The aperture of the first hole is from the opening of the first hole to the metal The pattern layer is decremented. The second hole is located in the substrate layer and exposes the metal pattern layer. The aperture of the second hole is decremented from the opening of the second hole toward the metal pattern layer. The first nano silver conductive pillar is filled into the first hole, and the second nano silver conductive pillar is filled into the second hole. The first silver paste layer covers the insulating layer and the first nano silver conductive pillar, and the second silver paste layer covers the substrate layer and the second nano silver conductive pillar. The first protective layer covers the first silver paste layer and the second protective layer covers the second silver paste layer.
本發明提供一種多層線路板的製造方法。首先,提供一線路基板,其包括一基板層以及一貼附於基板層上的金屬層。圖案化金屬層以形成一金屬圖案層。形成一絕緣基板於金屬圖案層上,其包括一黏著層、一絕緣層以及至少一第一孔洞。黏著層貼附於金屬圖案層上,絕緣層貼附於黏著層上。而第一孔洞貫穿絕緣基板,並暴露出金屬圖案層。之後,形成一第二孔洞於基板層,第二孔洞暴露出金屬圖案層。再來,形成第一奈米銀導電柱於第一孔洞之中,並形成第二奈米銀導電柱於第二孔洞之中。形成第一銀漿層於絕緣層之上,並形成第二銀漿層於基板層上。形成第一保護層於第一銀漿層上,並形成第二保護層於第二銀漿層上。The present invention provides a method of manufacturing a multilayer wiring board. First, a circuit substrate is provided which includes a substrate layer and a metal layer attached to the substrate layer. The metal layer is patterned to form a metal pattern layer. An insulating substrate is formed on the metal pattern layer, and includes an adhesive layer, an insulating layer and at least one first hole. The adhesive layer is attached to the metal pattern layer, and the insulating layer is attached to the adhesive layer. The first hole penetrates the insulating substrate and exposes the metal pattern layer. Thereafter, a second hole is formed in the substrate layer, and the second hole exposes the metal pattern layer. Then, a first nano silver conductive pillar is formed in the first hole, and a second nano silver conductive pillar is formed in the second hole. A first silver paste layer is formed on the insulating layer, and a second silver paste layer is formed on the substrate layer. Forming a first protective layer on the first silver paste layer and forming a second protective layer on the second silver paste layer.
綜上所述,本發明提供了一種多層線路板以及其製造方法,此多層線路板包含一線路基板、一第一奈米銀導電柱、一第二奈米銀導電柱、一第一銀漿層以及一第二銀漿層。線路基板包括基板層以及金屬圖案層,第一銀漿層透過第一奈米銀導電柱電性連接金屬圖案層。而第二銀漿層透過第二奈米銀導電柱電性連接金屬圖案層。第一銀漿層以及第二銀漿層可以用來取代單層板以及雙層板的結構, 以形成多層線路板的結構。如此可以降低多層板的層數,進而減少多層板的厚度,以達到產品薄型化的目的。In summary, the present invention provides a multilayer circuit board comprising a circuit substrate, a first nano silver conductive pillar, a second nano silver conductive pillar, and a first silver paste. a layer and a second layer of silver paste. The circuit substrate includes a substrate layer and a metal pattern layer, and the first silver paste layer is electrically connected to the metal pattern layer through the first nano silver conductive pillar. The second silver paste layer is electrically connected to the metal pattern layer through the second nano silver conductive pillar. The first silver paste layer and the second silver paste layer can be used to replace the structure of the single layer board and the double layer board. To form a structure of a multilayer wiring board. In this way, the number of layers of the multi-layer board can be reduced, and the thickness of the multi-layer board can be reduced to achieve the purpose of thinning the product.
為使能更進一步瞭解本發明之特徵及技術內容,請參閱以下有關本發明之詳細說明與附圖,但是此等說明與所附圖式僅係用來說明本發明,而非對本發明的權利範圍作任何的限制。The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.
圖1為本發明一實施例之多層線路板1的剖面示意圖。請參閱圖1,多層線路板1包括一線路基板100、一絕緣基板200’、一第二孔洞160、一第一奈米銀導電柱422、一第二奈米銀導電柱442、一第一銀漿層520、一第二銀漿層540、一第一保護層620以及一第二保護層640。1 is a cross-sectional view showing a multilayer wiring board 1 according to an embodiment of the present invention. Referring to FIG. 1 , the multilayer circuit board 1 includes a circuit substrate 100 , an insulating substrate 200 ′, a second hole 160 , a first nano silver conductive pillar 422 , a second nano silver conductive pillar 442 , and a first A silver paste layer 520, a second silver paste layer 540, a first protective layer 620, and a second protective layer 640.
線路基板100包括一基板層120’以及一金屬圖案層140’。金屬圖案層140’貼附在基板層120’之上,並做為多層線路板1的線路層。絕緣基板200’位於金屬圖案層140’之上,包括一黏著層220’、一絕緣層240’以及一第一孔洞260。而黏著層220’貼附於金屬圖案層140’上,絕緣層240’則貼附於黏著層220’上。第一孔洞260貫穿絕緣基板200’,且此第一孔洞260暴露出位於絕緣基板200’下方的金屬圖案層140’。The circuit substrate 100 includes a substrate layer 120' and a metal pattern layer 140'. The metal pattern layer 140' is attached over the substrate layer 120' and serves as a wiring layer of the multilayer wiring board 1. The insulating substrate 200' is located on the metal pattern layer 140' and includes an adhesive layer 220', an insulating layer 240', and a first hole 260. The adhesive layer 220' is attached to the metal pattern layer 140', and the insulating layer 240' is attached to the adhesive layer 220'. The first hole 260 penetrates the insulating substrate 200', and the first hole 260 exposes the metal pattern layer 140' under the insulating substrate 200'.
須說明的是,如圖1所示,第一孔洞260的孔徑是從第一孔洞260的開口向金屬圖案層140’遞減。也就是說,第一孔洞260的最大孔徑位在絕緣層240’的上表面,而第一孔洞260的最小孔徑位在黏著層220’的下表面。詳細而言,在本實施例中,第一孔洞260的最大孔徑為0.2mm,最小孔徑為0.1mm。然而本發明不限定第一孔洞260的形 狀以及孔徑大小。It should be noted that, as shown in FIG. 1, the aperture of the first hole 260 is decreased from the opening of the first hole 260 toward the metal pattern layer 140'. That is, the maximum aperture of the first hole 260 is at the upper surface of the insulating layer 240', and the minimum aperture of the first hole 260 is at the lower surface of the adhesive layer 220'. In detail, in the present embodiment, the first hole 260 has a maximum aperture of 0.2 mm and a minimum aperture of 0.1 mm. However, the present invention does not limit the shape of the first hole 260. Shape and pore size.
另外,基板層120’的材質可以是聚醯亞胺(Polyimide,PI)、聚對苯二甲酸乙二酯(Polyethylene Terephthalate,PET)、液晶高分子(Liquid Crystal polyester,LCP),或者是丙酮酸羧化酶(Pyruvate Carboxylase,PC)。金屬圖案層140’的材質包括銅、鋁或是錫。而黏著層220’的材料包括環氧樹脂(Epoxy)、聚酯樹脂(Polyester)或者是壓克力樹脂(Acrylic)。此外,基板層120’的厚度為12μm。絕緣基板200’的厚度為27μm,其中黏著層220’的厚度為15μm,絕緣層240’的厚度為12μm。In addition, the material of the substrate layer 120 ′ may be polyimide (PI), polyethylene terephthalate (PET), liquid crystal polymer (LCP), or pyruvic acid. Pyruvate Carboxylase (PC). The material of the metal pattern layer 140' includes copper, aluminum or tin. The material of the adhesive layer 220' includes epoxy resin (Epoxy), polyester resin (Polyester) or acrylic resin (Acrylic). Further, the thickness of the substrate layer 120' is 12 μm. The thickness of the insulating substrate 200' was 27 μm, in which the thickness of the adhesive layer 220' was 15 μm, and the thickness of the insulating layer 240' was 12 μm.
請再次參閱圖1,第二孔洞160貫穿基板層120’,並且暴露出位於基板層120’上方的金屬圖案層140’。而第二孔洞160的孔徑是從第二孔洞160的開口向金屬圖案層140’遞減。也就是說,第二孔洞160的最大孔徑位在基板層120’的下表面上,而第二孔洞160的最小孔徑位在基板層120’的上表面上。詳細而言,在本實施例中,第二孔洞160的最大孔徑為0.2mm,最小孔徑為0.1mm。然而本發明不限定第二孔洞160的形狀以及孔徑大小,在其他實施例中,第二孔洞160也可以只有單一孔徑,而孔徑大小可以是0.15-0.35mm。Referring again to Figure 1, the second hole 160 extends through the substrate layer 120' and exposes the metal pattern layer 140' over the substrate layer 120'. The aperture of the second hole 160 is decremented from the opening of the second hole 160 toward the metal pattern layer 140'. That is, the maximum aperture of the second hole 160 is on the lower surface of the substrate layer 120', and the minimum aperture of the second hole 160 is on the upper surface of the substrate layer 120'. In detail, in the present embodiment, the second hole 160 has a maximum pore diameter of 0.2 mm and a minimum pore diameter of 0.1 mm. However, the present invention does not limit the shape of the second hole 160 and the size of the aperture. In other embodiments, the second hole 160 may have only a single aperture, and the aperture size may be 0.15-0.35 mm.
如圖1所示,第一奈米銀導電柱422填入第一孔洞260之中,並電性連接金屬圖案層140’。而第二奈米銀導電柱442填入第二孔洞160之中,並電性連接金屬圖案層140’。第一銀漿層520位於絕緣層240’以及第一奈米銀導電柱422之上,並覆蓋絕緣層240’以及第一奈米銀導電柱422。而第一銀漿層520的厚度為4-12μm。第二銀漿層540位於 基板層120’以及第二奈米銀導電柱442之上,並覆蓋基板層120’以及第二奈米銀導電柱442。而第二銀漿層540的厚度為4-12μm。須說明的是,第一銀漿層520以及第二銀漿層540可以取代一般多層線路板中的雙層線路板以及單層線路板,如此可以降低多層線路板1的厚度,以達到產品薄型化的需求。As shown in FIG. 1, the first nano silver conductive pillar 422 is filled in the first hole 260 and electrically connected to the metal pattern layer 140'. The second nano silver conductive pillar 442 is filled in the second hole 160 and electrically connected to the metal pattern layer 140'. The first silver paste layer 520 is over the insulating layer 240' and the first nano-silver conductive pillars 422 and covers the insulating layer 240' and the first nano-silver conductive pillars 422. The first silver paste layer 520 has a thickness of 4-12 μm. The second silver paste layer 540 is located The substrate layer 120' and the second nano-silver conductive pillars 442 are overlying the substrate layer 120' and the second nano-silver conductive pillars 442. The second silver paste layer 540 has a thickness of 4-12 μm. It should be noted that the first silver paste layer 520 and the second silver paste layer 540 can replace the double-layer circuit board and the single-layer circuit board in the general multilayer circuit board, so that the thickness of the multilayer circuit board 1 can be reduced to achieve a thin product. Demand.
承上述,第一銀漿層520藉由第一奈米銀導電柱422電性連接金屬圖案層140’,而第二銀漿層540藉由第二奈米銀導電柱442電性連接金屬圖案層140’。也就是說,第一銀漿層520、第二銀漿層540以及金屬圖案層140’彼此電性導通。在本實施例中,第一銀漿層520以及第二銀漿層540可以不具線路圖案,以做為多層線路板1的接地層。然而在其他實施例中,第一銀漿層520以及第二銀漿層540也可以是線路圖案層。也就是說,多層線路板1具有三層線路圖案,且彼此之間可以透過第一奈米銀導電柱422以及第二奈米銀導電柱442電性連接。The first silver paste layer 520 is electrically connected to the metal pattern layer 140 ′ by the first nano silver conductive pillar 422 , and the second silver paste layer 540 is electrically connected to the metal pattern by the second nano silver conductive pillar 442 . Layer 140'. That is, the first silver paste layer 520, the second silver paste layer 540, and the metal pattern layer 140' are electrically connected to each other. In the present embodiment, the first silver paste layer 520 and the second silver paste layer 540 may have no wiring pattern as the ground layer of the multilayer wiring board 1. In other embodiments, however, the first silver paste layer 520 and the second silver paste layer 540 may also be line pattern layers. That is, the multilayer wiring board 1 has a three-layer wiring pattern and is electrically connected to each other through the first nano silver conductive pillar 422 and the second nano silver conductive pillar 442.
請再次參閱圖1,第一保護層620位於第一銀漿層520上,並覆蓋第一銀漿層520。而第二保護層640位於第二銀漿層540上,並覆蓋第二銀漿層540,也就是說第二銀漿層540會位於第二保護層640以及基板層120之間。第一保護層620以及第二保護層640的材料可以是聚酯類或聚醯亞胺,其可保護第一銀漿層520以及第二銀漿層540避免刮傷,並且可以避免第一銀漿層520以及第二銀漿層540和其他電子元件或者是其他多層線路板電性導通。Referring again to FIG. 1 , the first protective layer 620 is located on the first silver paste layer 520 and covers the first silver paste layer 520 . The second protective layer 640 is located on the second silver paste layer 540 and covers the second silver paste layer 540, that is, the second silver paste layer 540 is located between the second protective layer 640 and the substrate layer 120. The material of the first protective layer 620 and the second protective layer 640 may be polyester or polyimine, which can protect the first silver paste layer 520 and the second silver paste layer 540 from scratching, and can avoid the first silver The slurry layer 520 and the second silver paste layer 540 are electrically conductive with other electronic components or other multilayer wiring boards.
以上所述為本發明一實施例之多層線路板1的結構。接下來要介紹此多層線路板1的製造方法。圖1A至圖1G 為本發明一實施例之多層線路板1的製造流程剖面示意圖。The above is the structure of the multilayer wiring board 1 according to an embodiment of the present invention. Next, a method of manufacturing the multilayer wiring board 1 will be described. Figure 1A to Figure 1G A schematic cross-sectional view showing a manufacturing process of the multilayer wiring board 1 according to an embodiment of the present invention.
請參閱圖1A,首先提供一線路基板100,線路基板100包括一基板層120以及一金屬層140。金屬層140貼附在基板層120之上。請參閱圖1B,之後依照使用者的需求圖案化金屬層140以形成金屬圖案層140’。圖案化金屬層140的方法包括利用影像轉移搭配化學藥液的方式,在金屬層140上形成線路圖案。請參閱圖1B以及圖1C,接下來,形成一絕緣基板200’於金屬圖案層140’上。絕緣基板200’包括一黏著層220’、一絕緣層240’以及一第一孔洞260。第一孔洞260會貫穿黏著層220’以及絕緣層240’,並且暴露出位於黏著層220’下方的金屬圖案層140’。Referring to FIG. 1A, a circuit substrate 100 is first provided. The circuit substrate 100 includes a substrate layer 120 and a metal layer 140. The metal layer 140 is attached over the substrate layer 120. Referring to FIG. 1B, the metal layer 140 is then patterned to form a metal pattern layer 140' in accordance with the needs of the user. The method of patterning the metal layer 140 includes forming a line pattern on the metal layer 140 by means of image transfer with a chemical liquid. Referring to FIG. 1B and FIG. 1C, next, an insulating substrate 200' is formed on the metal pattern layer 140'. The insulating substrate 200' includes an adhesive layer 220', an insulating layer 240', and a first hole 260. The first hole 260 will penetrate the adhesive layer 220' and the insulating layer 240' and expose the metal pattern layer 140' under the adhesive layer 220'.
詳細而言,形成一絕緣基板200’於金屬圖案層140’的方法包括,提供一絕緣基板200,此絕緣基板200包括一黏著層220以及一絕緣層240,而絕緣層240貼附於黏著層220之上。之後,可以利用例如是熱壓合的方法將絕緣基板200貼附於金屬圖案層140’之上,而黏著層220貼附於金屬圖案層140’上。黏著層220的厚度為15μm,絕緣層240的厚度為12μm,也就是說絕緣基板200的厚度為27μm。In detail, the method of forming an insulating substrate 200' on the metal pattern layer 140' includes providing an insulating substrate 200 including an adhesive layer 220 and an insulating layer 240, and the insulating layer 240 is attached to the adhesive layer. Above 220. Thereafter, the insulating substrate 200 may be attached onto the metal pattern layer 140' by, for example, a thermocompression bonding method, and the adhesive layer 220 is attached to the metal pattern layer 140'. The thickness of the adhesive layer 220 is 15 μm, and the thickness of the insulating layer 240 is 12 μm, that is, the thickness of the insulating substrate 200 is 27 μm.
另外,基板層120的材質可以是聚醯亞胺(Polyimide,PI)、聚對苯二甲酸乙二酯(Polyethylene Terephthalate,PET)、液晶高分子(Liquid Crystal polyester,LCP),或者是丙酮酸羧化酶(Pyruvate Carboxylase,PC)。金屬層140的材質包括銅、鋁或是錫。而黏著層220的材料包括環氧樹脂(Epoxy)、聚酯樹脂(Polyester)或者是壓克力樹脂 (Acrylic)。In addition, the material of the substrate layer 120 may be polyimide (PI), polyethylene terephthalate (PET), liquid crystal polymer (LCP), or pyruvate carboxylate. Pyruvate Carboxylase (PC). The material of the metal layer 140 includes copper, aluminum or tin. The material of the adhesive layer 220 includes epoxy resin (Epoxy), polyester resin (Polyester) or acrylic resin. (Acrylic).
如圖1B所示,之後在金屬圖案層140’上欲形成孔洞的位置上,利用雷射L對絕緣基板200進行鑽孔,以形成第一孔洞260於絕緣基板200'。如圖1C所示,第一孔洞260的孔徑是從第一孔洞260的開口往金屬圖案層140’遞減。也就是說,第一孔洞260的孔徑是從絕緣層240’的上表面向黏著層220’的下表面遞減(如圖1C所示),其最小孔徑為0.1mm,而最大孔徑為0.2mm。也就是說,在本實施例中,可以先將絕緣基板200貼附於金屬圖案層140’上,之後根據金屬圖案層140’欲導通的位置在絕緣基板200上形成一第一孔洞260。利用上述方法形成絕緣基板200’於金屬圖案層140’可以使得第一孔洞260落在比較精準的位置上。As shown in Fig. 1B, the insulating substrate 200 is drilled by the laser light L at a position where a hole is to be formed in the metal pattern layer 140' to form the first hole 260 in the insulating substrate 200'. As shown in FIG. 1C, the aperture of the first aperture 260 is diminished from the opening of the first aperture 260 toward the metal pattern layer 140'. That is, the aperture of the first hole 260 is decremented from the upper surface of the insulating layer 240' toward the lower surface of the adhesive layer 220' (as shown in Fig. 1C), and has a minimum aperture of 0.1 mm and a maximum aperture of 0.2 mm. That is, in the present embodiment, the insulating substrate 200 may be attached to the metal pattern layer 140' first, and then a first hole 260 is formed on the insulating substrate 200 according to the position at which the metal pattern layer 140' is to be turned on. Forming the insulating substrate 200' to the metal pattern layer 140' by the above method allows the first hole 260 to fall at a relatively precise position.
請參閱圖1C以及圖1D,之後在金屬圖案層140’上欲鑽孔的位置上,利用雷射L對基板層120進行鑽孔,以形成第二孔洞160於基板層120’。第二孔洞160會貫穿基板層120’,並暴露出位於基板層120’上方的金屬圖案層140’。而第二孔洞160的孔徑是從第二孔洞160的開口往的金屬圖案層140’遞減(如圖1D所示)。也就是說,第二孔洞160的孔徑是從基板層120’的上表面向基板層120’的下表面遞減。而第二孔洞160的最小孔徑為0.1mm,而最大孔徑為0.2mm。Referring to FIG. 1C and FIG. 1D, the substrate layer 120 is then drilled by the laser beam L at a position on the metal pattern layer 140' to be drilled to form a second hole 160 in the substrate layer 120'. The second via 160 will penetrate the substrate layer 120' and expose the metal pattern layer 140' over the substrate layer 120'. The aperture of the second hole 160 is decremented from the opening of the second hole 160 toward the metal pattern layer 140' (as shown in Fig. 1D). That is, the aperture of the second hole 160 is decreased from the upper surface of the substrate layer 120' toward the lower surface of the substrate layer 120'. The second hole 160 has a minimum aperture of 0.1 mm and a maximum aperture of 0.2 mm.
須說明的是,在本實施例中,形成第一孔洞260以及第二孔洞160之後會進行清孔以及檢查的步驟。清孔的步驟可以去除殘留在第一孔洞260底部的部分絕緣基板200’以及在第二孔洞160底部的部分基板層120’。而清孔的步 驟可包括化學藥液或電漿。而檢查的步驟可以確保第一孔洞260以及第二孔洞160清孔完全。如此可以維持或提升後續形成的第一奈米銀導電柱422以及第二奈米銀導電柱442對於金屬圖案層140’電性連接的品質。It should be noted that, in this embodiment, the steps of clearing holes and inspecting are performed after the first holes 260 and the second holes 160 are formed. The step of clearing the holes can remove a portion of the insulating substrate 200' remaining at the bottom of the first hole 260 and a portion of the substrate layer 120' at the bottom of the second hole 160. The step of clearing the hole The chemical may include a chemical liquid or a plasma. The step of inspecting ensures that the first hole 260 and the second hole 160 are completely clear. Thus, the quality of the subsequently formed first nano silver conductive pillar 422 and the second nano silver conductive pillar 442 to the metal pattern layer 140' can be maintained or improved.
請參閱圖1E,接下來,分別形成第一奈米銀導電柱422以及第二奈米銀導電柱442於第一孔洞260以及第二孔洞160之中。形成第一奈米銀導電柱422的方法包括,設置一第一遮罩板320於絕緣層240’以及第一孔洞260之上。第一遮罩板320具有一個第一簍空處322,且此簍空處322的面積會大於第一孔洞260的開口面積。也就是說,簍空處322會暴露出第一孔洞260。須說明的是,本發明不限定第一孔洞260的數量。在其他實施例中,多層線路板1也可以具有多個第一孔洞260,而第一簍空處322會對應第一孔洞260的數量。Referring to FIG. 1E, next, a first nano silver conductive pillar 422 and a second nano silver conductive pillar 442 are formed in the first hole 260 and the second hole 160, respectively. The method of forming the first nano silver conductive pillar 422 includes disposing a first mask 320 over the insulating layer 240' and the first via 260. The first mask 320 has a first hollow 322, and the area of the hollow 322 is larger than the opening area of the first hole 260. That is, the hollow 322 exposes the first hole 260. It should be noted that the present invention does not limit the number of first holes 260. In other embodiments, the multilayer circuit board 1 may also have a plurality of first holes 260, and the first hollow portion 322 may correspond to the number of the first holes 260.
接著,如圖1E所示,塗佈一第一奈米銀材料420於第一遮罩板板320上,使得第一奈米銀材料420填滿第一孔洞260。最後,移除遮罩板320並且固化第一奈米銀材料420,以形成第一奈米銀導電柱422於第一孔洞260中。固化第一奈米銀材料420的方法包括以130-140℃的溫度加熱第一奈米銀材料420大約30分鐘。另外,也可以是以UV光照射第一奈米銀材料420。而此第一奈米銀導電柱422的電阻值≦20mΩ/square/mil。Next, as shown in FIG. 1E, a first nano silver material 420 is coated on the first mask plate 320 such that the first nano silver material 420 fills the first holes 260. Finally, the mask 320 is removed and the first nanosilver material 420 is cured to form a first nanosilver conductive post 422 in the first aperture 260. The method of curing the first nanosilver material 420 includes heating the first nanosilver material 420 at a temperature of 130-140 ° C for about 30 minutes. Alternatively, the first nanosilver material 420 may be irradiated with UV light. The resistance of the first nano silver conductive pillar 422 is m20mΩ/square/mil.
如圖1E所示,形成第二奈米銀導電柱442的方法包括,設置第二遮罩板340於基板層120’以及第二孔洞160之上。第二遮罩板340包括第二簍空處342,且此第二簍空處342的面積會大於第二孔洞160的開口面積。也就是 說第二簍空處342會暴露出位於第二遮罩板340下方的第二孔洞160。之後,塗佈一第二奈米銀材料440於第二遮罩板340上(如圖1E所示),使得第二奈米銀材料440填滿第二孔洞160。再來,移除第二遮罩板340,並且固化第二奈米銀材料440以形成第二奈米銀導電柱442。固化第二奈米銀材料440的方法包括以130-140℃的溫度加熱第二奈米銀材料440大約30分鐘。另外,也可以是以UV光照射第二奈米銀材料440。而此第二奈米銀導電柱442的電阻值≦20mΩ/square/mil。在其他實施例中,多層線路板1也可以具有多個第二孔洞160,而第二簍空處342會對應第二孔洞160的數量。As shown in FIG. 1E, a method of forming a second nanosilver conductive pillar 442 includes disposing a second mask 340 over the substrate layer 120' and the second via 160. The second mask 340 includes a second hollow 342, and the area of the second hollow 342 is greater than the open area of the second hole 160. That is It is said that the second hollow 342 exposes the second hole 160 below the second mask 340. Thereafter, a second nanosilver material 440 is applied to the second mask 340 (as shown in FIG. 1E) such that the second nanosilver material 440 fills the second hole 160. Again, the second masking plate 340 is removed and the second nanosilver material 440 is cured to form a second nanosilver conductive pillar 442. The method of curing the second nanosilver material 440 includes heating the second nanosilver material 440 at a temperature of 130-140 ° C for about 30 minutes. Alternatively, the second nanosilver material 440 may be irradiated with UV light. The second nano silver conductive pillar 442 has a resistance value of m20 mΩ/square/mil. In other embodiments, the multilayer circuit board 1 may also have a plurality of second holes 160, and the second hollow portions 342 may correspond to the number of the second holes 160.
須說明的是,本發明不限定所述第一孔洞260、第二孔洞160、第一奈米銀導電柱422以及第二奈米銀導電柱442的數量,在其他實施例中,使用者可依照實際需求以及走線設計決定第一孔洞260、第二孔洞160、第一奈米銀導電柱422以及第二奈米銀導電柱442的數量。It should be noted that the present invention does not limit the number of the first hole 260, the second hole 160, the first nano silver conductive pillar 422, and the second nano silver conductive pillar 442. In other embodiments, the user may The number of the first hole 260, the second hole 160, the first nano silver conductive pillar 422, and the second nano silver conductive pillar 442 is determined according to actual needs and the routing design.
另外,第一孔洞260以及第二孔洞160的孔徑、深度以及形狀皆會影響第一奈米銀材料420以及第二奈米銀材料440填入的難易度以及填充的均勻度。在本實施例中,第一孔洞260的深度即為基板層120’的厚度,也就是12μm。而第二孔洞160的深度即為黏著層220’以及絕緣層240’的厚度總合,也就是27μm。另外,第一孔洞260的開口是向金屬圖案層140’遞減,其最小孔徑為0.1mm,而最大孔徑為0.2mm。第二孔洞160的開口也是向金屬圖案層140’遞減,其最小孔徑為0.1mm,而最大孔徑為0.2mm。In addition, the aperture, depth and shape of the first hole 260 and the second hole 160 affect the ease of filling of the first nano silver material 420 and the second nano silver material 440 and the uniformity of filling. In the present embodiment, the depth of the first hole 260 is the thickness of the substrate layer 120', that is, 12 μm. The depth of the second hole 160 is the total thickness of the adhesive layer 220' and the insulating layer 240', that is, 27 μm. Further, the opening of the first hole 260 is decremented toward the metal pattern layer 140' with a minimum aperture of 0.1 mm and a maximum aperture of 0.2 mm. The opening of the second hole 160 is also tapered toward the metal pattern layer 140' with a minimum aperture of 0.1 mm and a maximum aperture of 0.2 mm.
以上所述第一孔洞260以及第二孔洞160的孔徑、深 度以及形狀會使得第一奈米銀材料420以及第二奈米銀材料440可以較輕易的填滿第一孔洞260以及第二孔洞160。然而本發明不以此為限。The aperture and depth of the first hole 260 and the second hole 160 described above The degree and shape may cause the first nano silver material 420 and the second nano silver material 440 to fill the first hole 260 and the second hole 160 relatively easily. However, the invention is not limited thereto.
接下來,請參閱圖1F,形成一第一銀漿層520於絕緣層240'以及第一奈米銀導電柱422之上。而第一銀漿層520的厚度為4-12μm。形成第一銀漿層520的方法包括利用塗佈的方式將第一銀漿材料塗佈於絕緣層240’以及第一奈米銀導電柱422之上。之後,固化第一銀漿材料,以形成第一銀漿層520。固化第一銀漿材料的方式包括加熱第一銀漿材料或者是利用UV照射第一銀漿材料。另外,第一銀將層520會電性連接第一奈米銀導電柱422以及金屬圖案層140’。Next, referring to FIG. 1F, a first silver paste layer 520 is formed over the insulating layer 240' and the first nano silver conductive pillars 422. The first silver paste layer 520 has a thickness of 4-12 μm. The method of forming the first silver paste layer 520 includes applying a first silver paste material onto the insulating layer 240' and the first nano silver conductive pillars 422 by coating. Thereafter, the first silver paste material is cured to form a first silver paste layer 520. The means for curing the first silver paste material includes heating the first silver paste material or irradiating the first silver paste material with UV. In addition, the first silver layer 520 is electrically connected to the first nano silver conductive pillar 422 and the metal pattern layer 140'.
之後,形成第二銀漿層540於基板層120’以及第二奈米銀導電柱442之上。形成第二銀漿層540的方法和形成第一銀漿層520的方法相同,在此不多做贅述。而第二銀將層540的厚度為4-12μm。另外第二銀將層540會電性連接第二奈米銀導電柱442以及金屬圖案層140’。須說明的是,第一銀漿層520以及第二銀漿層540可以取代一般多層線路板中的雙層線路板以及單層線路板,如此可以降低多層線路板1的厚度,以達到產品薄型化的需求。Thereafter, a second silver paste layer 540 is formed over the substrate layer 120' and the second nano silver conductive pillars 442. The method of forming the second silver paste layer 540 is the same as the method of forming the first silver paste layer 520, and will not be described here. The second silver layer 540 has a thickness of 4-12 μm. In addition, the second silver layer 540 is electrically connected to the second nano silver conductive pillar 442 and the metal pattern layer 140'. It should be noted that the first silver paste layer 520 and the second silver paste layer 540 can replace the double-layer circuit board and the single-layer circuit board in the general multilayer circuit board, so that the thickness of the multilayer circuit board 1 can be reduced to achieve a thin product. Demand.
在本實施例中,第一銀漿層520以及第二銀漿層540為多層線路板1的接地層。然而,在其他實施例中,可以再對第一銀漿層520以及第二銀漿層540進行圖案化的步驟以形成第一線路圖案層以及第二線路圖案層。而多層線路板1為一三層線路板的結構。在此,本發明不限定第一銀漿層520以及第二銀漿層540的功用。In the present embodiment, the first silver paste layer 520 and the second silver paste layer 540 are ground layers of the multilayer wiring board 1. However, in other embodiments, the first silver paste layer 520 and the second silver paste layer 540 may be further patterned to form a first line pattern layer and a second line pattern layer. The multilayer circuit board 1 is a three-layer circuit board structure. Here, the present invention does not limit the functions of the first silver paste layer 520 and the second silver paste layer 540.
另外,第一銀漿層520以及第二銀漿層540的材料可以是金屬銀與樹脂所混合而成的黏稠狀漿料。而第一奈米銀材料420以及第二奈米銀材料440的材料是奈米金屬銀與樹脂所混合而成的黏稠狀漿料,且此奈米金屬銀為小於100nm的金屬銀,且總固體含量為82±3%。由於第一奈米銀材料420以及第二奈米銀材料440為小於100nm的金屬銀,因此第一奈米銀材料420以及第二奈米銀材料440可以較輕易的填入第一孔洞260以及第二孔洞160。In addition, the material of the first silver paste layer 520 and the second silver paste layer 540 may be a viscous slurry in which metal silver and a resin are mixed. The material of the first nano silver material 420 and the second nano silver material 440 is a viscous slurry of a mixture of nano metal silver and a resin, and the nano metal silver is a metallic silver of less than 100 nm, and the total solid is The content is 82 ± 3%. Since the first nano silver material 420 and the second nano silver material 440 are metallic silver of less than 100 nm, the first nano silver material 420 and the second nano silver material 440 can be easily filled into the first hole 260 and The second hole 160.
值得說明的是,由於第一奈米銀導電柱422與第一銀漿層520以及第二奈米銀導電柱442與第二銀漿層540的主成分皆為銀,因此當形成第一銀漿層520於第一奈米銀導電柱422以及形成第二銀漿層540於第二奈米銀導電柱442時,較不會因為材料的差異而產生電性連接或者是爆板等問題。It should be noted that since the main components of the first nano silver conductive pillar 422 and the first silver paste layer 520 and the second nano silver conductive pillar 442 and the second silver paste layer 540 are both silver, the first silver is formed. When the slurry layer 520 is on the first nano silver conductive pillar 422 and the second silver paste layer 540 is formed on the second nano silver conductive pillar 442, there is no problem that electrical connection or explosion is caused by the difference of materials.
另外,在本實施例中,是先形成絕緣基板200’於線路基板100上,再利用雷射切割形成第一孔洞260於絕緣基板200’上。這樣的作法可以使得第一孔洞260落在比較精準的位置上。因此所形成的第一奈米銀導電柱422會較準確的落在金屬圖案層140’上欲電性導通的位置上。特別是針對金屬圖案層140’之線路分佈較密集的情況下,這樣的做法可以更準確的電性連接金屬圖案層140’以及第一銀漿層520。Further, in the present embodiment, the insulating substrate 200' is first formed on the wiring substrate 100, and the first holes 260 are formed by laser cutting on the insulating substrate 200'. This practice allows the first hole 260 to fall in a more precise position. Therefore, the formed first nano silver conductive pillar 422 will fall more accurately on the metal pattern layer 140' where it is electrically conductive. In particular, in the case where the line distribution of the metal pattern layer 140' is dense, such a method can electrically connect the metal pattern layer 140' and the first silver paste layer 520 more accurately.
請參閱圖1G,接下來,形成第一保護層620於第一銀漿層520之上,並形成第二保護層640於第二銀漿層540之上,也就是說第二銀漿層540會位於第二保護層640以及基板120之間。第一保護層620以及第二保護層640的 材料可以是聚酯類樹脂或聚醯亞胺,其介電係數為3.5,而絕緣阻抗為1011 Ω。此外,第一保護層620以及第二保護層640可保護第一銀漿層520以及第二銀漿層540避免刮傷,並且可以避免第一銀漿層520以及第二銀漿層540和其他電子元件或者是其他多層線路板電性導通。Referring to FIG. 1G, next, a first protective layer 620 is formed over the first silver paste layer 520, and a second protective layer 640 is formed over the second silver paste layer 540, that is, the second silver paste layer 540. It will be located between the second protective layer 640 and the substrate 120. The material of the first protective layer 620 and the second protective layer 640 may be a polyester resin or a polyimide, having a dielectric constant of 3.5 and an insulation resistance of 10 11 Ω. In addition, the first protective layer 620 and the second protective layer 640 can protect the first silver paste layer 520 and the second silver paste layer 540 from scratches, and can avoid the first silver paste layer 520 and the second silver paste layer 540 and others. Electronic components or other multilayer circuit boards are electrically conductive.
圖2A至2B為本發明另一實施例之多層線路板的製造流程剖面示意圖。請參閱圖2A,和前一實施例不同的是,本實施例形成絕緣基板200”於金屬圖案層140’的方法包括,提供一絕緣基板200”。此絕緣基板200”包括黏著層220”以及絕緣層240”,而絕緣層240”貼附於黏著層220”之上。之後,根據金屬圖案層140’所欲形成孔洞的位置,利用雷射L在絕緣基板200”上形成一第一孔洞260’。此第一孔洞260’會貫穿絕緣基板200”,並暴露出金屬圖案層140’。2A to 2B are schematic cross-sectional views showing a manufacturing process of a multilayer wiring board according to another embodiment of the present invention. Referring to FIG. 2A, unlike the previous embodiment, the method of forming the insulating substrate 200" on the metal pattern layer 140' of the present embodiment includes providing an insulating substrate 200". The insulating substrate 200" includes an adhesive layer 220" and an insulating layer 240", and the insulating layer 240" is attached to the adhesive layer 220". Thereafter, the laser is used according to the position of the hole where the metal pattern layer 140' is to be formed. A first hole 260' is formed on the insulating substrate 200". This first hole 260' will penetrate the insulating substrate 200" and expose the metal pattern layer 140'.
將絕緣基板200”貼附於金屬圖案層140’上,使得第一孔洞260’對應到金屬圖案層140’所欲形成孔洞的位置。而絕緣基板200”貼附的方式可以是利用熱壓合的方式。之後,利用雷射L對於基板層120'進行鑽孔,以形成第二孔洞160於基板層120’。而多層線路板的其他步驟以及結構大致上和前一實施例相同,在此不多做贅述。值得說明的是,在本實施例中,是先形成第一孔洞260’於絕緣基板200”上,再將絕緣基板200”貼附於線路基板100上。The insulating substrate 200 ′′ is attached to the metal pattern layer 140 ′ such that the first hole 260 ′ corresponds to the position where the metal pattern layer 140 ′ is to form a hole. The insulating substrate 200 ′ can be attached by thermal pressing. The way. Thereafter, the substrate layer 120' is drilled using the laser light L to form a second hole 160 in the substrate layer 120'. The other steps and structures of the multilayer circuit board are substantially the same as those of the previous embodiment, and will not be described here. It should be noted that in the present embodiment, the first hole 260' is formed on the insulating substrate 200", and the insulating substrate 200" is attached to the circuit substrate 100.
綜上所述,本發明提供了一種多層線路板以及其製造方法,此多層線路板包含一線路基板、一第一奈米銀導電柱、一第二奈米銀導電柱、一第一銀漿層以及一第二銀漿層。線路基板包括基板層以及金屬圖案層,第一銀漿層、 金屬圖案層以及第二銀漿層之間會透過第一奈米銀導電柱以及第二奈米銀導電柱電性連接。而第一銀漿層以及第二銀漿層可以取代單層板以及雙層板,以形成多層線路板的結構。如此可降低多層板的層數,進而減少多層板的厚度,以達到產品薄型化的目的。In summary, the present invention provides a multilayer circuit board comprising a circuit substrate, a first nano silver conductive pillar, a second nano silver conductive pillar, and a first silver paste. a layer and a second layer of silver paste. The circuit substrate includes a substrate layer and a metal pattern layer, and the first silver paste layer, The metal pattern layer and the second silver paste layer are electrically connected through the first nano silver conductive pillar and the second nano silver conductive pillar. The first silver paste layer and the second silver paste layer may replace the single layer board and the double layer board to form a structure of the multilayer wiring board. In this way, the number of layers of the multilayer board can be reduced, and the thickness of the multilayer board can be reduced to achieve the purpose of thinning the product.
以上所述僅為本發明的實施例,其並非用以限定本發明的專利保護範圍。任何熟習相像技藝者,在不脫離本發明的精神與範圍內,所作的更動及潤飾的等效替換,仍為本發明的專利保護範圍內。The above is only an embodiment of the present invention, and is not intended to limit the scope of the invention. It is still within the scope of patent protection of the present invention to make any substitutions and modifications of the modifications made by those skilled in the art without departing from the spirit and scope of the invention.
1‧‧‧多層線路板1‧‧‧Multilayer circuit board
100‧‧‧線路基板100‧‧‧Line substrate
120、120’‧‧‧基板層120, 120'‧‧‧ substrate layer
140‧‧‧金屬層140‧‧‧metal layer
140’‧‧‧金屬圖案層140’‧‧‧metal pattern layer
160‧‧‧第二孔洞160‧‧‧Second hole
200、200’、200”‧‧‧絕緣基板200, 200', 200" ‧ ‧ insulating substrates
220、220’、220”‧‧‧黏著層220, 220’, 220” ‧ ‧ adhesive layer
240、240’、240”‧‧‧絕緣層240, 240', 240" ‧ ‧ insulation
260、260’‧‧‧第一孔洞260, 260’ ‧ ‧ first hole
320‧‧‧第一遮罩板320‧‧‧First mask
322‧‧‧第一簍空處322‧‧‧First empty space
340‧‧‧第二遮罩板340‧‧‧Second mask
342‧‧‧第二簍空處342‧‧‧Second Hollow
420‧‧‧第一奈米銀材料420‧‧‧First nano silver material
422‧‧‧第一奈米銀導電柱422‧‧‧First nano silver conductive column
440‧‧‧第二奈米銀材料440‧‧‧Second nano silver material
442‧‧‧第二奈米銀導電柱442‧‧‧Second nano silver conductive column
520‧‧‧第一銀漿層520‧‧‧First silver paste layer
540‧‧‧第二銀漿層540‧‧‧Second silver paste layer
620‧‧‧第一保護層620‧‧‧First protective layer
640‧‧‧第二保護層640‧‧‧Second protective layer
L‧‧‧雷射L‧‧‧Laser
圖1為本發明一實施例之多層線路板的剖面示意圖。1 is a cross-sectional view showing a multilayer wiring board according to an embodiment of the present invention.
圖1A至圖1G為本發明一實施例之多層線路板的製造流程剖面示意圖。1A to 1G are schematic cross-sectional views showing a manufacturing process of a multilayer wiring board according to an embodiment of the present invention.
圖2A至圖2B為本發明另一實施例之多層線路板的製造流程剖面示意圖。2A to 2B are schematic cross-sectional views showing a manufacturing process of a multilayer wiring board according to another embodiment of the present invention.
1‧‧‧多層線路板1‧‧‧Multilayer circuit board
100‧‧‧線路基板100‧‧‧Line substrate
120’‧‧‧基板層120'‧‧‧ substrate layer
140’‧‧‧金屬圖案層140’‧‧‧metal pattern layer
160‧‧‧第二孔洞160‧‧‧Second hole
200’‧‧‧絕緣基板200'‧‧‧Insert substrate
220’‧‧‧黏著層220’‧‧‧Adhesive layer
240’‧‧‧絕緣層240'‧‧‧Insulation
260‧‧‧第一孔洞260‧‧‧ first hole
422‧‧‧第一奈米銀導電柱422‧‧‧First nano silver conductive column
442‧‧‧第二奈米銀導電柱442‧‧‧Second nano silver conductive column
520‧‧‧第一銀漿層520‧‧‧First silver paste layer
540‧‧‧第二銀漿層540‧‧‧Second silver paste layer
620‧‧‧第一保護層620‧‧‧First protective layer
640‧‧‧第二保護層640‧‧‧Second protective layer
Claims (15)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW102103973A TWI474763B (en) | 2013-02-01 | 2013-02-01 | Multi-layer wiring board and manufacturing method for same |
CN 201320076299 CN203120285U (en) | 2013-02-01 | 2013-02-19 | Multilayer circuit board |
CN201310053051.6A CN103974521B (en) | 2013-02-01 | 2013-02-19 | Multilayer circuit board and its manufacture method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW102103973A TWI474763B (en) | 2013-02-01 | 2013-02-01 | Multi-layer wiring board and manufacturing method for same |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201433224A TW201433224A (en) | 2014-08-16 |
TWI474763B true TWI474763B (en) | 2015-02-21 |
Family
ID=48900591
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW102103973A TWI474763B (en) | 2013-02-01 | 2013-02-01 | Multi-layer wiring board and manufacturing method for same |
Country Status (2)
Country | Link |
---|---|
CN (2) | CN103974521B (en) |
TW (1) | TWI474763B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11205642B2 (en) | 2019-07-04 | 2021-12-21 | National Taipei University Of Technology | Twistable light emitting diode display module |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI474763B (en) * | 2013-02-01 | 2015-02-21 | Career Technology Mfg Co Ltd | Multi-layer wiring board and manufacturing method for same |
CN105657979A (en) * | 2016-04-01 | 2016-06-08 | 浪潮电子信息产业股份有限公司 | PCB (printed circuit board) and method for manufacturing same |
CN108076581A (en) * | 2016-11-17 | 2018-05-25 | 中国科学院苏州纳米技术与纳米仿生研究所 | Multi-layer flexible circuit board and preparation method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200942099A (en) * | 2008-03-24 | 2009-10-01 | Fujitsu Ltd | Multilayer wiring board, multilayer wiring board unit and electronic device |
TW200950622A (en) * | 2008-05-22 | 2009-12-01 | Unimicron Technology Corp | Method for fabricating embedded circuit |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002319763A (en) * | 2001-04-24 | 2002-10-31 | Matsushita Electric Ind Co Ltd | Multilayer wiring board and its producing method |
TWI474763B (en) * | 2013-02-01 | 2015-02-21 | Career Technology Mfg Co Ltd | Multi-layer wiring board and manufacturing method for same |
-
2013
- 2013-02-01 TW TW102103973A patent/TWI474763B/en active
- 2013-02-19 CN CN201310053051.6A patent/CN103974521B/en active Active
- 2013-02-19 CN CN 201320076299 patent/CN203120285U/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200942099A (en) * | 2008-03-24 | 2009-10-01 | Fujitsu Ltd | Multilayer wiring board, multilayer wiring board unit and electronic device |
TW200950622A (en) * | 2008-05-22 | 2009-12-01 | Unimicron Technology Corp | Method for fabricating embedded circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11205642B2 (en) | 2019-07-04 | 2021-12-21 | National Taipei University Of Technology | Twistable light emitting diode display module |
Also Published As
Publication number | Publication date |
---|---|
TW201433224A (en) | 2014-08-16 |
CN203120285U (en) | 2013-08-07 |
CN103974521B (en) | 2017-08-01 |
CN103974521A (en) | 2014-08-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20090101400A1 (en) | Method for manufacturing component-embedded substrate and component-embedded substrate | |
US7908744B2 (en) | Method for fabricating printed circuit board having capacitance components | |
US9560770B2 (en) | Component built-in board and method of manufacturing the same, and mounting body | |
US20150138741A1 (en) | Chip embedded board and method of manufacturing the same | |
TWI474763B (en) | Multi-layer wiring board and manufacturing method for same | |
TWI484875B (en) | Circuit board and method for manufacturing same | |
US7839650B2 (en) | Circuit board structure having embedded capacitor and fabrication method thereof | |
US10314179B2 (en) | Manufacturing method of circuit structure | |
TWI466610B (en) | Package structure and method for manufacturing same | |
US8541687B2 (en) | Coreless layer buildup structure | |
JP2019121763A (en) | Printed wiring board and manufacturing method thereof | |
TWI503902B (en) | Semiconductor package and manufacturing method thereof | |
TWI531291B (en) | Package board and method for manufactuing same | |
US10932373B2 (en) | Circuit board, electronic circuit device, and production method of circuit board | |
US9351408B2 (en) | Coreless layer buildup structure with LGA and joining layer | |
US8536459B2 (en) | Coreless layer buildup structure with LGA | |
TWM460488U (en) | Multi-layer substrate | |
TWI446849B (en) | Manufacturing method of circuit board structure | |
JP2016219452A (en) | Multilayer substrate and manufacturing method for multilayer substrate | |
JP5257518B2 (en) | Substrate manufacturing method and resin substrate | |
JP7137354B2 (en) | Multilayer circuit board and manufacturing method thereof | |
KR102052761B1 (en) | Chip Embedded Board And Method Of Manufacturing The Same | |
KR102054198B1 (en) | Method for manufacturing wiring board | |
JP5672675B2 (en) | Resin multilayer board | |
TWI479974B (en) | Method for forming printed circuit boards |