TWI467715B - 改良晶圓級晶片尺度封裝技術 - Google Patents

改良晶圓級晶片尺度封裝技術 Download PDF

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TWI467715B
TWI467715B TW98133163A TW98133163A TWI467715B TW I467715 B TWI467715 B TW I467715B TW 98133163 A TW98133163 A TW 98133163A TW 98133163 A TW98133163 A TW 98133163A TW I467715 B TWI467715 B TW I467715B
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dielectric layer
die
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TW201025530A (en
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Andrew George Holland
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Cambridge Silicon Radio Ltd
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Description

改良晶圓級晶片尺度封裝技術 發明領域
本發明是有關於改良晶圓級晶片尺度封裝技術。
 發明背景
市場對小尺寸、低成本但功能增強之電子裝置的需求，驅使封裝半導體晶粒之技術發展。在封裝之晶粒僅稍微大於該晶粒本身的尺寸下(例如，面積比不超過1.2:1)，晶片尺度封裝(CSP)包含了許多不同之封裝技術。在一CSP的例子中，晶粒可被安裝在已形成焊接球(或凸塊)的封裝件上(例如，銲球柵狀陣列封裝件)，使得晶粒可藉由引線接合的方式而電氣連接至封裝件，並且經組裝之封裝件可利用BGA技術或覆晶接合方式而安裝在印刷電路板(PCB)上。
在晶圓級晶片尺度封裝技術(WLCSP)，亦稱作晶圓級封裝技術中，在晶圓被切成個別的晶粒之前焊接球(或凸塊)即已直接形成在半導體晶圓上。如此可產生非常精小的封裝晶粒並為封裝晶粒之晶圓尺度測試帶來成本及效能上之利益。
 發明概要
此概要係以簡化的形式來介紹以下詳細之發明說明所述的概念。此概要並不用於辨別本案所請標的之重要或必要特徵，亦非用於決定本案所請標的之範圍。
在此所述之改良晶圓級晶片尺度封裝技術並未使用一囊封通孔以連接在一重分佈層與一半導體接墊環內的接墊之間。在一實施態樣中，所形成之一第一介電層係終止在各晶粒之接墊環內。接著，在一傳導層中形成軌線，其中該傳導層接觸該等接墊之一並且在第一介電層之表面上覆蓋過一開口之邊緣。這些軌線用於在該接墊與一焊接球之間形成一電氣連接。
本發明之第一方面提供了一種封裝半導體裝置，其包含：一半導體晶粒，其包含數個配置在該晶粒之一主動面周圍的接墊；一形成在該主動面上之第一介電層，其中該第一介電層係終止在圍繞該晶粒之主動面周圍之該等數個接墊之內；數條形成在一傳導層內之軌線，其中各條軌線係連接至該等數個接墊之一並包含在該第一介電層上形成之一上方部分；一配置來囊封該主動面之第二介電層；以及數個焊接元件，各個該等焊接元件係被電氣連接至一軌線之一上方部分。
各條軌線可形成於該第一介電層之一端部上。
各條軌線可直接連接至該等數個接墊之一。
該第二介電層可終止在該晶粒之該主動面周圍之外。
該裝置可以是一晶圓級晶片尺度封裝裝置。
本發明之第二方面提供了一種製造封裝半導體裝置之方法，其包含下列步驟：在包含一半導體晶粒陣列的半導體主動面上形成一第一介電層，其中各個半導體晶粒包含數個配置在該晶粒之一主動面周圍的接墊，並且該第一介電層係終止在各個晶粒之上並位於圍繞該晶粒之主動面周圍之該等數個接墊之內；在該主動面之一傳導層及該第一介電層內形成數條軌線，其中一晶粒之各條軌線包含形成於該等接墊之一之一下方部分以及形成於該第一介電層上之一上方部份；在各個半導體晶粒上形成一第二介電層；形成數個焊接元件，各個該等焊接元件係電氣連接至一軌線之一上方部份；並且將該半導體晶圓切割成數個封裝半導體裝置。
各條軌線可包含一中心部份，該中心部份係形成於該第一介電層之一端部之上。
各條軌線可包含一位在該下方部份及該中心部份間的另一部份，該另一部份係形成於該晶粒之該主動面上。
一種在一半導體晶圓之主動面上形成一第一介電層之方法，可包含：在一半導體晶圓之主動面上沉積一第一介電層；以及選擇性地蝕刻各晶粒之該第一介電層，使其終止在圍繞該晶粒之主動面周圍之數個接墊之內。
該裝置可以是一晶圓級晶片尺度封裝裝置。
本發明之第三方面提供了一種實質如圖式第3至4及6至7圖所述之封裝半導體裝置。
本發明之第四方面提供了一種實質如圖式第5圖所述之製造封裝半導體裝置之方法
如同熟知此技者所瞭解地，該等特徵可被適當地組合並可和本發明之其他方面相組合。
圖式簡單說明
本發明之實施例將參考以下圖式並用示例之方式來作說明，其中：第1及第2圖所顯示者為一種以習知技術所製得之WLCSP裝置其之截面及平面圖；第3圖所顯示者為一種改良之WLCSP示例之截面圖；第4圖所顯示者為另一種改良之WLCSP示例之平面圖；第5圖所顯示者為一種以改良之WLCSP程序來製造封裝半導體晶粒之例示方法的流程圖；並且第6及第7圖顯示者為經圖形化之介電層之示例。
在全部的圖式中相同之參考編號象徵類似之特徵，並應瞭解到這些圖示中所顯示之覆層及佈局僅屬示例而不依比例來繪製。
 較佳實施例之詳細說明
以下僅用示例的方式來說明本發明之實施例。這些示例雖非完成本發明之唯一方法，但代表申請人目前所知實施本發明之最佳方式。發明說明描述示例之功能以及建構並運作示例之步驟順序。然而，相同或相等之功能及順序係可藉由不同之示例來完成。
第1及第2圖顯示一種習知之晶圓級晶片尺度封裝技術的示例。第1圖顯示一穿過WLCSP之橫截面，該WLCSP包含一半導體晶粒101其進一步被處理以在該晶粒之主動面上附加若干之材料層102。應瞭解到為能清楚說明，在該半導體晶粒101中並未顯示出所有覆層。為能在該晶粒之一接墊103及焊接球104之間提供一電氣連接，在兩聚合物層106、107之較下方一層中採用一囊封通孔105。第2圖係一對應之平面圖，其顯示接墊103、穿過下方聚合物層106之通孔105以及將接墊103連接至焊接球104的軌線108。第2圖亦顯示上方聚合物層107內之通孔109能在軌線108與焊接球104之間提供電氣連接。在此亦顯示出位在晶粒邊緣之該二聚合物層106、107的端部116、117。
在這種已知的WLCSPs中，晶粒上之接墊103間距受限於可精確製造之囊封通孔105的最小尺寸。在一示例中，聚合物層內之蝕刻孔最小尺寸為直徑30微米並需有一金屬區(稱作捕捉接墊)，而在聚合物層108上方的金屬層內有直徑為61微米的最小尺寸。若金屬區之間的最小間隔為19微米，則最小的接墊間距為80微米。
以下所述之實施例並不僅限於解決習知晶圓級晶片尺度封裝體及封裝技術之任何或全部的缺點。
第3圖顯示穿過一改良WLCSP的橫截面圖，該WLCSP並未使用一囊封通孔。該改良之WLCSP包含一半導體晶粒301，其已經過額外之處理(在一晶圓尺度)而在該晶粒之主動面上附加了若干之額外覆層302。該半導體晶粒301係透過將材料沉積在一基本上係為矽晶圓之半導體晶圓的一面上所製得。因此，該晶圓之各個晶粒皆具有一金屬軌線與其他電路形成其上之主動面及一為基材本身之非主動面。該等額外覆層302可包含一或多層介電層(例如介電層303、304)，一或多層金屬層(例如重分佈層305、下凸塊金屬306及焊接點，例如焊接球307)。應瞭解為能清楚說明，並未顯示該半導體晶粒301之所有覆層。此外，其他示例可包括未顯示在第3圖中的附加WLCSP層。
如第3圖所顯示者，下方之介電層303被終止(如箭頭308所指出者)在遠離晶粒邊緣處並位於該晶粒之接墊環中。在此使用之“接墊環”一詞意指晶粒周邊之接墊，該等接墊可形成圍繞在晶粒周圍之一環或者僅在晶粒周邊之一部份有接墊。當接墊並非環繞整個周邊區域時，下方之介電層可被終止在晶粒周邊之接墊內，但在沒有接墊之周邊區域中，下方之介電層可更靠近地延伸到晶粒之邊緣並且在若干示例中可延伸到晶粒邊緣之後。可以採用任何適當之方法來作成下方介電層303之端部，例如藉由沉積、圖形化及蝕刻之步驟。為在晶粒301上之接墊309與焊接球307之間提供一電氣連接，重分佈層305係配置在介電層303之邊緣上。為囊封該晶粒並避免濕氣進入，上方之介電層304終止在該晶粒之邊緣或在該晶粒之後方。
下方介電層303之端部308亦顯示在第4圖中，該圖為改良WLCSP之另一示例的平面圖。為能清楚說明，第4圖僅顯示一些覆層。第4圖之示例顯示出三個晶粒上的接墊309以及形成於重分佈層305內的三條軌線401。這些軌線可利用任何適當的技術來形成(例如沉積後再蝕刻或者利用在晶圓上圖形化一光阻層之後再沉積的剝離方法)。下方之介電層303係終止308在晶粒之接墊環內(其處所顯示之接墊309為一接墊環之子集)，並且亦顯示出上方之介電層304的端部310。在一示例中，該二 介電質所終止的位置之間分開200微米或更大。路由層305內之軌線401與接墊309之間並無囊封通孔，而是在整個下方之介電層303之邊緣以及該等接墊309本身之上皆覆蓋軌線401。
應瞭解第4圖所顯示之配置僅作為例示之用，其他之示例可具有不同的構造，例如軌線與接墊可具有實質相同之寬度，而該等接墊可為圓形而非矩形等等。
利用以上所述以及顯示在第3及第4圖內之技術，可減小半導體晶粒之接墊所容許之最小間距。使用和以上詳述之示例相同的製程條件，新的最小接墊間距係由金屬區域之間的最小間隔(例如19微米)以及用半導體晶粒製程(為了製作接墊309)所能達到的最小軌線寬度(例如25微米)並且由WLCSP製程(為了製作軌線401)來決定。雖然除了WLCSP製程外仍有其他的限制會拘限實際使用的最小間距(例如引線接合之接墊最小間距目前為55微米)並且只能採用超過該最小值的間距，但在此示例中，最小間距降至44微米。移除WLCSP製程在接墊間距所造成之限制可將晶粒設計成適於引線接合及/或WLCSP而不會增加晶粒尺寸。依據特定之實施態樣，減少晶粒上之接墊所容許的最小間距可使整個晶粒的尺寸變小，亦可降低晶粒之製造成本(例如當每一片晶圓之成本為固定時)。此外，減少所容許之 最小接墊間距可使得沿著一晶粒邊緣有更多的接墊(即更多I/O)。
由於在晶粒之間的線道中或在接近線道之處所終止之介電層數量減少，以上所述之技術(如第3及第4圖所示)亦可改善封裝晶粒的產量。在一示例中，藉由將下方之介電層終止在晶粒區域內，可將上方之介電層終止在更遠離線道中心之處。晶圓切割刀之路徑與上方介電層之間的距離增加將可降低切割過程中介電層被破壞的可能性，也因此提高了WLCSP製程的產量。
第5圖顯示一種採用改良之WLCSP製程來製造封裝半導體晶粒之方法。該製程涉及到在一包含一半導體晶粒陣列之半導體晶圓上形成一第一介電層(方塊501)，該第一介電層包含有圍繞各晶粒之接墊環的多個開口(亦稱為缺口或孔洞)，其中各晶粒係獨立於該第一介電質，如此使得該第一介電層被終止在接墊環內之各晶粒上。這些開口較起自接墊環之單一接墊為大並且各開口含有一個以上起自接墊環之接墊。在一例示之實施態樣中，該第一介電層可藉由在整個晶圓上沉積一層完整之覆層來形成(方塊510)，接著再選擇地性移除圍繞接墊環之區域(方塊511)，譬如利用微影術來圖形化覆層並以蝕刻的方式去除所界定區域內的覆層。在另一例示之實施態樣中，該第一介電層可利用在該介電層中界 定開口之印刷方法來形成(例如使用屏蔽印刷的方式)。
形成經圖形化之第一介電層(方塊501)之後，再沉積或形成一重分佈層(方塊502)。該重分佈層包含覆蓋過該第一介電層邊緣及接墊環內之接墊上的軌線，並且，再一次地，這些軌線可藉由在沉積之後進行蝕刻或其他方法來形成。接著可形成額外覆層，諸如在形成第二覆層(方塊503)之後接著形成下凸塊金屬(UBM)以及焊接層(方塊504)。完成晶圓之尺寸處理後，即以譬如一晶圓切割刀將該晶圓分割為個別之封裝晶粒(方塊505)。
在一例示之實施態樣中，標準的WLCSP製程以及標準的WLCSP材料可和改變第一介電層之設計使其終止在介電環內的改良方式一起使用。在其他示例中，亦可修改WLCSP製程及/或材料。
應瞭解的是，第5圖所顯示之方法可包含其他的步驟(譬如其他重分佈層及聚合物層)及/或替代的步驟。可採用任何適合之半導體製程技術來形成任何覆層並且可用任何適合之材料於各覆層。在一示例中，該介電層可為苯環丁烯(BCB)、聚苯噁唑(PBO)、聚亞醯胺(PI)或另一種聚合物。應瞭解的是，第3及第4圖所提及之PBO僅作為例示說明，而諸如BCB、PI、其他聚合物或其他材料可替代地用於任一介電層。
第6圖顯示一種圖形化之介電層，該介電層包含多個圍繞接墊環之開口使其並未覆蓋圍繞一半導體晶粒之接墊環的區域，並使該介電層終止在各晶粒之接墊環內。在第6圖中係以屏蔽式地顯示介電層601，以虛線602指出個別之晶粒並顯示出一晶粒之接墊環603的位置。第7圖顯示另外兩個示例701、702，有介電層之區域係以屏蔽式顯示而開口以非屏蔽式顯示。在第一個示例701中，第一介電層係終止在接墊環之內並且在接墊環的範圍中有一區域703沒有介電層。在此例中，接墊環與一晶粒邊緣之間也有其他之介電層704區域。如同在兩例示之展開圖711、712中所顯示者，如此之其他的介電層704區域使得在重分佈層內的軌線(譬如軌線705)可被路由到接墊環與晶粒邊緣之間，並且在若干示例中(譬如軌線705)，軌線可連接多個接墊接著在晶粒範圍內連續。儘管這樣的軌線可路由至介電層下方(譬如在鋁墊層(AP)中)，但也可能無法實施在某些應用中(譬如，其將造成電氣短路或者該層係作為諸如接地層之另一用途)或是有問題的(譬如，間距緊密之覆層內的軌線所造成之串擾)。在第二個示例702中，圍繞接墊環內之接墊群組的區域707沒有介電層。類似於第一個示例之方式，在若干示例中，軌線(譬如軌線708)可被路由至接墊環與晶粒之間(如例示之展開圖713所示)。
第3-7圖所述之技術可和其他技術相組合以用於減小在一晶粒之接墊環內的接墊間距。這些其他技術的示例包括在半導體晶粒上使用接墊層(例如AP層)以作為額外路由，譬如將接墊環內之接墊連接到以更大間距來配置的其他接墊(如，產生一種雙接墊環，其之內環及外環內的接墊較周邊接墊環之間隔為寬)，或使用額外的改向層或介電層以在一改向層中形成路由。
如熟知此技者所瞭解地，此處給定之範圍或裝置值可經擴展或改變而不會失其尋求之功效
應瞭解到，以上所述之效益及優點可和一個實施例或數個實施例相關。該等實施例並不僅限於用來解決上述之任何或全部的問題或僅帶來上述之效益及優點。
任何“一”項之用語意指一或多個項目。於此所使用之用語“包含”意指包括所使出之方法方塊或元件，而這些並不排除可包含額外方塊或元件的方法及裝置。
於此說明之方法步驟可用任何適合的順序來進行或同時進行。此外，個別的方塊可自該等方法之任一者中刪除而不會偏離本發明之精神與範圍。上述任一示例之層面可和其他示例之層面相組合以形成其他示例而不會喪失本發明所尋求之功效。
應可理解到，以上對於較佳實施例之說明僅是 採例示的方式，而熟知此技者可作不同的修改。雖然在此是用某些特定的方式來說明各種不同的實施例或參考依或多個實施例，但熟知此技者對於該等實施例所作之變更卻不會偏離本發明之精神與範圍。
101、301‧‧‧半導體晶粒
102‧‧‧材料層
103、309‧‧‧接墊
104、307‧‧‧焊接球
105、109‧‧‧通孔
106、107‧‧‧聚合物層
108、401、705、706、708‧‧‧軌線
116、117、308、310‧‧‧端部
302‧‧‧額外覆層
303、304、601、704‧‧‧介電層
305‧‧‧重分佈層
306‧‧‧下凸塊金屬
501-505‧‧‧區塊
602‧‧‧虛線
603‧‧‧接墊環
701、702‧‧‧示例
703、707‧‧‧區域
711、712、713‧‧‧展開圖
第1及第2圖所顯示者為一種以習知技術所製得之WLCSP裝置其之截面及平面圖；第3圖所顯示者為一種改良之WLCSP示例之截面圖；第4圖所顯示者為另一種改良之WLCSP示例之平面圖；第5圖所顯示者為一種以改良之WLCSP程序來製造封裝半導體晶粒之例示方法的流程圖；並且第6及第7圖顯示者為經圖形化之介電層之示例。
301．．．半導體晶粒
302．．．額外覆層
303、304．．．介電層
305．．．重分佈層
306．．．下凸塊金屬
307．．．焊接球
308、310．．．端部
309．．．接墊

Claims (13)

  1. 一種封裝半導體裝置，其包含：一半導體晶粒，其包含配置在圍繞該晶粒之一主動面上的該晶粒之周圍之一接墊環中的數個接墊；形成在該主動面上之一第一介電層，其中該第一介電層包含終止在該接墊環內的一第一區，及位在該接墊環與該晶粒之一邊緣之間的一另一區，使得圍繞該接墊環之一區域沒有該第一介電層；形成在一傳導層內之數條軌線，其中各條軌線係連接至該等數個接墊中之一者並包含形成在該第一介電層上之一上方部分，且其中該等數條軌線中之至少一者包含形成在該第一介電層之該另一區上的一上方部分；一配置來囊封該主動面之第二介電層；以及數個焊接元件，各該焊接元件係電氣連接至一軌線之一上方部分。
  2. 如請求項1之封裝半導體裝置，其中各條軌線係形成於該第一介電層之一端部上方。
  3. 如請求項1之封裝半導體裝置，其中各條軌線係直接連接至該等數個接墊中之一或多者。
  4. 如請求項3之封裝半導體裝置，其中各條軌線係終止於其直接連接之該等數個接墊中之該一者的 一區域內。
  5. 如請求項1之封裝半導體裝置，其中該第二介電層係終止在該晶粒之該主動面之周圍之外。
  6. 如請求項1至5中之任一項之封裝半導體裝置，其中該裝置係一晶圓級晶片尺度封裝裝置。
  7. 如請求項1之封裝半導體裝置，其中該等數條軌線中之至少一者與多於一個接墊連接一起，且包含形成在該第一介電層之該另一區上的一上方部分。
  8. 如請求項7之封裝半導體裝置，其中該等數條軌線中之該至少一者更包含形成在該第一介電層之該第一區上的一第二上方部分。
  9. 一種用於製造封裝半導體裝置之方法，其包含下列步驟：在包含一半導體晶粒陣列的一半導體晶圓之一主動面上形成一第一介電層，其中各個半導體晶粒包含配置在圍繞該晶粒之該主動面上的該晶粒之周圍之一接墊環中的數個接墊，並且該第一介電層包含終止在該接墊環內的一第一區，及位在該接墊環與該晶粒之一邊緣之間的一另一區，使得圍繞該接墊環的一區域沒有該第一介電層；在一傳導層中形成數條軌線，其中一晶粒上之各條軌線係連接至該等數個接墊中之一者且包含形成於該第一介電層上之一上方部分，且其中該等數條 軌線中之至少一者包含形成在該第一介電層之該另一區上的一上方部分；在各個半導體晶粒上形成一第二介電層；形成數個焊接元件，各該焊接元件係電氣連接至一軌線之一上方部分；及將該半導體晶圓切割成數個封裝半導體裝置。
  10. 如請求項9之方法，其中各條軌線包含一中心部分，該中心部分係形成於該第一介電層之一端部上方。
  11. 如請求項10之方法，其中各條軌線包含位在下方部分及該中心部分間的一另一部分，該另一部分係形成於該晶粒之該主動面上。
  12. 如請求項9之方法，其中在一半導體晶圓之一主動面上形成一第一介電層之步驟包含：在一半導體晶圓之主動面上沉積一第一介電層；以及選擇性地蝕刻該第一介電層，使該第一介電層在各個晶粒上終止於圍繞該晶粒之該主動面周圍之該等數個接墊內。
  13. 如請求項9至12中之任一項之方法，其中該裝置係一晶圓級晶片尺度封裝裝置。
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