TWI465020B - Can produce three times the input voltage of the gate driver and drive method - Google Patents

Description

Gate driver and driving method capable of generating three times input voltage

The invention relates to a gate driver and a driving method used in a power switch, in particular to a gate driver and a driving method capable of generating three times of input voltage.

The analog control integrated circuit plays an important role in the power electronic circuit. The analog control integrated circuit manufactured by the high-voltage process can operate at a high voltage from 10 volts to 20 volts. However, the design of power supply systems such as monitors, communication devices, or power management devices has become increasingly complex, and digital control technologies for power supply based on FPGAs, DSPs, microprocessors, or special ASICs have become a trend.

Too low a voltage cannot drive a metal oxide semiconductor field effect transistor (MOSFET). For example, a working voltage of 3.3 volts cannot drive the switching action of a metal oxide semiconductor field effect transistor, so it is required to generate a higher driving voltage. Gate drive. In addition, it is assumed that the logic circuit and the gate drive circuit are separated, and the two are independent of each other, which means that a certain number of separate components are used to increase the overall area. Therefore, it is necessary to simplify the design to realize digital circuit integration of high density and miniaturization design. .

Based on the foregoing, an n-channel MOSFET switching element or other similar component (eg, n-channel insulated gate bipolar crystal (Insulated-gate) Bipolar transistor (referred to as IGBT) power switch), it is necessary to design a simplified design, fast action to reduce switching losses, and must be able to generate a higher driving voltage to simultaneously supply digital control integrated circuit input voltage and drive n channel The gate driver of the MOSFET switching element.

Accordingly, it is an object of the present invention to provide a gate driver and a driving method that meet a simplified design and can be quickly discharged to reduce energy loss and generate three times the input voltage.

Thus, the gate driver capable of generating three times the input voltage of the present invention comprises a driving circuit, a first charge pump and a second charge pump.

The driving circuit is powered by an input voltage and has a pair of power switches. The pair of power switches collectively receive a pulse control signal and the outputs of the two are connected to a first node. The pulse control signal has a first mode and A second mode is to regulate whether the pair of power switches are turned on or off.

The first charge pump has a first charging circuit, a first discharging circuit and a first clamping circuit. The first clamping circuit includes a first diode and a first capacitor, and an anode end of the first diode. a power supply coupled to the input voltage, a cathode end of the first diode is connected in series with one end of the first capacitor, and the other end of the first capacitor is connected to the first node, and the first charging circuit has a third transistor, a three-electrode system-p-channel metal-oxide-semiconductor field-effect transistor component, a gate terminal of a third transistor coupled to a power supply of the input voltage, and a source terminal of the third transistor coupled to the first diode Between the cathode end of the body and one end of the first capacitor, the first discharge circuit has a fourth transistor, and the fourth transistor system has an n-channel metal oxide semiconductor field effect a crystal element, a gate control end of the fourth transistor is coupled to the power source of the input voltage, a source terminal of the fourth transistor is coupled to the first node, a drain of the third transistor, and a drain of the fourth transistor The pole is coupled to a second node.

The second charge pump has a second charging circuit, a second discharging circuit and a second clamping circuit. The second clamping circuit includes a second diode and a second capacitor. The anode end of the second diode a power source coupled to the input voltage, a cathode end of the second diode is connected to one end of the second capacitor, the other end of the second capacitor is connected to the second node, and the second charging circuit has a fifth transistor, and a fifth a p-channel MOSFET, a gate control terminal of a fifth transistor coupled to the input voltage source, and a source terminal of the fifth transistor coupled to the second diode Between the cathode end and one end of the second capacitor; the second discharge loop has a sixth transistor, the sixth transistor system, an n-channel metal oxide semiconductor field effect transistor component, and the sixth transistor gate control The terminal is coupled to the power supply of the input voltage, the source terminal of the sixth transistor is coupled to the second node, and the drain of the fifth transistor and the drain of the sixth transistor are coupled to an output end, and The first mode, the first charging circuit and the first Charging circuit is charged to three times the input voltage to the output terminal, and in the second mode, the first discharge circuit and said second discharge circuit to discharge.

Preferably, the pair of power switches comprises a first transistor and a second transistor, the first transistor system is a p-channel metal oxide semiconductor field effect transistor device, and the second transistor system has an n channel. Metal oxide semiconductor field effect transistor elements.

The invention provides a gate driving method package with three times input voltage The method includes the following steps: providing a driving circuit, receiving power supply of an input voltage and having a pair of power switches, the pair of power switches receiving a pulse wave control signal and the outputs of the two are connected to a first node, the pulse wave control The signal has a first mode and a second mode to regulate the conduction of the pair of power switches; providing a first charge pump having a first charging circuit, a first discharging circuit and a first clamping circuit, The clamping circuit includes a first diode and a first capacitor. The anode end of the first diode is coupled to the power source of the input voltage, and the cathode end of the first diode is connected to one end of the first capacitor. The other end of the first capacitor is connected to the first node, the first charging circuit has a third transistor, the third electro-crystalline system is a p-channel metal oxide semiconductor field effect transistor element, and the third transistor is gate-controlled. The terminal is coupled to the power supply of the input voltage, the source terminal of the third transistor is coupled between the cathode end of the first diode and one end of the first capacitor, and the first discharge circuit has a fourth transistor, and a fourth Electro-crystalline system An n-channel metal oxide semiconductor field effect transistor device, a gate control terminal of the fourth transistor is coupled to the power source of the input voltage, and a source terminal of the fourth transistor is coupled to the first node, the third The drain of the crystal and the drain of the fourth transistor are both coupled to a second node; and a second charge pump is provided, having a second charging circuit, a second discharging circuit and a second clamping circuit, The second clamping circuit includes a second diode and a second capacitor. The anode end of the second diode is coupled to the power source of the input voltage, and the cathode end of the second diode is serially connected to one end of the second capacitor. The other end of the second capacitor is connected to the second node, the second charging circuit has a fifth transistor, the fifth transistor system is a p-channel metal oxide semiconductor field effect transistor element, and the gate terminal of the fifth transistor is Coupled to the input voltage a power source, a source terminal of the fifth transistor is coupled between the cathode end of the second diode and one end of the second capacitor; the second discharge circuit has a sixth transistor, a sixth transistor system, and an n-channel metal An oxide semiconductor field effect transistor device, a gate control terminal of the sixth transistor is coupled to the power source of the input voltage, a source terminal of the sixth transistor is coupled to the second node, and a drain of the fifth transistor is The drain of the sixth transistor is coupled to an output terminal; and in the first mode, the first charging circuit and the second charging circuit are charged to three times the input voltage to the output terminal, and in the second mode The first discharge circuit and the second discharge circuit are discharged.

Preferably, in the first mode, the first transistor is turned on and the second transistor is not turned on, the first diode is reverse biased and the first capacitor is discharged, and the gate of the third transistor is The voltage between the pole and the source is a negative value of the input voltage to turn on the third transistor, and the output voltage is not between the gate and the source of the fourth transistor to make the fourth transistor non-conducting; The voltage between the gate and the source of the fifth transistor is twice the negative value of the input voltage to turn on the fifth transistor, and the voltage between the gate and the source of the sixth transistor is The negative value of the input voltage causes the sixth transistor to be non-conductive. In the second mode, the first transistor is non-conducting and the second transistor is turned on, the first diode and the second diode are forward biased, and the first capacitor and the second capacitor are Quickly charging to the input voltage, there is no output voltage between the gate and the source of the third transistor to make the third transistor non-conductive, and the voltage between the gate and the source of the fourth transistor is Inputting a voltage to turn on the fourth transistor; meanwhile, there is no output voltage between the gate and the source of the fifth transistor to make the fifth transistor non-conductive, the sixth transistor The voltage between the gate and the source of the body is the input voltage to turn on the sixth transistor.

The effect of the gate driver and the driving method of the invention capable of generating three times of input voltage is that the gate driver of the invention can provide an output voltage of three times the input voltage, and meets the requirements of streamlined design and fast action to reduce switching loss. .

100‧‧‧gate driver

10‧‧‧Drive circuit

11‧‧‧First charge pump

111‧‧‧First charging circuit

112‧‧‧First discharge circuit

113‧‧‧First clamp circuit

12‧‧‧Second charge pump

121‧‧‧Second charging circuit

122‧‧‧Second discharge circuit

123‧‧‧Second clamp circuit

B ₁ ‧‧‧Inverter

C ₁ ‧‧‧first capacitor

C ₂ ‧‧‧second capacitor

C _gs ‧‧‧ energy storage components

D ₁ ‧‧‧First Diode

D ₂ ‧‧‧Secondary

PWM, pwm‧‧‧ pulse wave control signal

Q ₁ ‧‧‧First transistor

Q ₂ ‧‧‧Second transistor

Q ₃ ‧‧‧The third transistor

Q ₄ ‧‧‧fourth transistor

Q ₅ ‧‧‧ Fifth transistor

Q ₆ ‧‧‧ sixth transistor

V _CC ‧‧‧ input voltage

v _gs ‧‧‧ drive signal

X ₁ ‧‧‧ first node

X ₂ ‧‧‧second node

Other features and advantages of the present invention will be apparent from the embodiments of the present invention, wherein: Figure 1 is a circuit diagram illustrating a preferred embodiment of the components of the gate driver of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a circuit diagram showing a preferred embodiment of a gate driver of the present invention in a first mode; FIG. 4 is a circuit diagram; The preferred embodiment of the gate driver of the present invention is in the second mode; FIG. 5 is a timing waveform diagram illustrating the voltage waveform of each component of the preferred embodiment, and the switching frequency is 10 kHz; FIG. 6 is a timing diagram. The waveform diagram illustrates the voltage waveform of each component of the preferred embodiment, and the switching frequency is 500 kHz. FIG. 7 is a timing waveform diagram illustrating the pulse wave control signal PWM of the preferred embodiment of the present invention. capacitor voltage v _C1, the second capacitor _C2 and the energy storage element voltage V v _gs voltage waveform; FIG. 8 is a timing waveform diagram illustrating the preferred embodiment of the present embodiment the switching frequency of the pulse control signal is a PWM 500kHz, A capacitor voltage v _C1, a second capacitor voltage waveform v _C2 and the voltage v _gs of the storage element; FIG. 9 is a timing waveform diagram illustrating the preferred embodiment of the present embodiment is the switching frequency of the PWM 10kHz pulse control signal, the first The waveforms of the node voltage v _X1 , the second node voltage v _X2 and the energy storage element voltage v _gs ; and FIG. 10 is a timing waveform diagram illustrating the pulse wave control signal PWM of the preferred embodiment of the present invention at 500 kHz. The waveform of the node voltage v _X1 , the second node voltage v _{X2 ,} and the energy storage element voltage v _gs .

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

Referring to FIG. 1 and FIG. 2, in a preferred embodiment of the gate driver 100 and the driving method for generating three times the input voltage of the present invention, the gate driver 100 includes a driving circuit 10, a first charge pump 11 and a The second charge pump 12 .

It is explained in advance that the preferred embodiment is applied to an n-channel MOSFET switching element (not shown) or other similar power switch, and in the preferred embodiment, the energy storage element C _gs is used to simulate the n-channel. The gate of the MOSFET switching element.

The driving circuit 10 is powered by a power supply of an input voltage V _CC and has an inverter B ₁ and a pair of power switches. In the preferred embodiment, the pair of power switches includes a first transistor Q ₁ and a first The two transistors Q ₂ , the first transistor Q ₁ is a p-channel metal oxide semiconductor field effect transistor element and the second transistor Q ₂ is an n-channel metal oxide semiconductor field effect transistor element.

The gates of the first transistor Q ₁ and the second transistor Q ₂ collectively receive a pulse control signal PWM and the outputs of the two are connected to a first node X ₁ , and the pulse control signal PWM is a pulse wave, which may be a wave. A pulse modulation control signal (PFM) is generated by a wide modulation or variable frequency modulation (PFM) method, and a pulse control signal pwm inverted by the inverter B ₁ has a first mode and a second mode to regulate the first transistor Q ₁ and the first The second transistor Q ₂ is turned on or not, wherein the first mode is a high level voltage and the second mode is a low level voltage.

The first charge pump 11 has a first charging circuit 111, a first discharge circuit 112, and a first clamping circuit 113, wherein the first clamping circuit 113 comprises a first diode D ₁ and a first capacitor C _1, a first diode D ₁ the anode terminal coupled to the power supply Vcc to the input voltage, the cathode of the first diode D ₁ is connected in series to the terminal end of the first capacitor C _1, the first capacitor C _1, the other One end is connected to the first node X ₁ .

The first charging circuit 111 has a third transistor Q ₃ , the third transistor Q ₃ is a p-channel metal oxide semiconductor field effect transistor element, and the gate control terminal of the third transistor Q ₃ is coupled to the gate a source voltage Vcc of the input voltage, a source terminal of the third transistor Q ₃ is coupled between the cathode terminal of the first diode D ₁ and one end of the first capacitor C ₁ ; the first discharge circuit 112 has a fourth transistor Q ₄ , the fourth transistor Q ₄ is an n-channel metal oxide semiconductor field effect transistor device, the gate control terminal of the fourth transistor Q ₄ is coupled to the input voltage power source Vcc, and the fourth transistor Q The source terminal of ₄ is coupled to the first node X ₁ , and the drain of the third transistor Q _{3 and} the drain of the fourth transistor Q ₄ are coupled to a second node X ₂ .

The second charge pump 12 having a second charging circuit 121, a second discharge circuit 122, a clamping circuit 123 and a second energy storage element C _gs, a second clamping circuit 123 comprises a second diode D ₂ and a second capacitor C ₂ , an anode end of the second diode D ₂ is coupled to the power supply V _{CC of} the input voltage, and a cathode end of the second diode D ₂ is serially connected to one end of the second capacitor C ₂ , The other end of the second capacitor C ₂ is connected to the second node X ₂ .

The second charging circuit 121 has a fifth transistor Q ₅ , the fifth transistor Q ₅ is a p-channel metal oxide semiconductor field effect transistor element, and the gate control terminal of the fifth transistor Q ₅ is coupled to the a source voltage Vcc of the input voltage, a source terminal of the fifth transistor Q ₅ is coupled between the cathode terminal of the second diode D ₂ and one end of the second capacitor C ₂ ; the second discharge circuit 122 has a sixth transistor Q ₆ , the sixth transistor Q ₆ is an n-channel metal oxide semiconductor field effect transistor component, and the gate control terminal of the sixth transistor Q ₆ is coupled to the input voltage power source Vcc, the sixth transistor Q The source terminal of ₆ is coupled to the second node X ₂ , and the drain of the fifth transistor Q _{5 and} the drain of the sixth transistor Q ₆ are both coupled to an output terminal coupled to the energy storage component C. One end of _gs .

Referring to FIG. 2, in conjunction with FIG. 3 and FIG. 4, the following describes how the two control modes of the gate driver 100 operate; it should be noted that this embodiment assumes that the feedforward voltage for all diodes is zero, along The values of the voltage v _{C1 of the} first capacitor C ₁ and the voltage v _C2 of the second capacitor C ₂ are both close to the input voltage (V _CC ).

Referring to FIG. 3 and FIG. 5, the gate driver 100 in the first mode, the detailed operation of each element is: a first transistor Q ₁ turns on and the second transistor Q ₂ is not turned on, a first diode D ₁ is reverse and the first capacitor C ₁ is discharged to the bias voltage (reverse biased), in this mode, the voltage v between the gate of the third transistor Q ₃ and the source electrode ₃ is _GS - V _CC, so that the third transistor Q ₃ is turned on, the voltage _v gs4 between the gate of the fourth transistor Q ₄ and the source is 0, so the fourth transistor Q ₄ nonconducting; while pole between the fifth transistor Q ₅ of the gate and source the voltage v _GS5 is -2 V _CC, so that the fifth transistor Q ₅ is turned on, the voltage v between the sixth transistor Q ₆ gate and the source ₆ is a _GS - V _CC, so that a sixth transistor Q ₆ is not turned on, so that the energy storage element C _gs load output voltage v _gs is 3 V _CC (three times the input voltage). Therefore, in the first mode, the first charging circuit 111 and the second charging circuit 121 both output three times the input voltage by charging the energy storage element C _gs by the input voltage V _CC .

Referring to FIG. 4 and FIG. 5, in the second mode, the first discharge circuit 112 and the second discharge circuit 122 discharge the energy storage element C _gs by the power source of the positive voltage (+V _CC ). The detailed action is as follows: the first transistor Q _{1 is} not turned on and the second transistor Q _{2 is} turned on, and the first diode D ₁ and the second diode D ₂ are forward biased and the first capacitor the second capacitor C ₂ C ₁ is quickly charged to V _CC, in this mode, the voltage v between the gate of the third transistor Q ₃ and the source is 0 _{GS 3,} so that the third transistor Q3 is not turned on, The voltage v _gs4 between the gate and the source of the fourth transistor Q ₄ is V _CC such that the fourth transistor Q _{4 is} turned on; meanwhile, the voltage between the gate and the source of the fifth transistor Q ₅ is v _gs5 is 0, so that the fifth transistor Q ₅ is not turned on, the voltage v between the sixth transistor Q ₆ gate and the source of the _{GS 6} is V _CC, so that the sixth transistor Q ₆ is turned on, so that the loading in The output voltage v _gs of the energy storage element C _gs is zero, that is, no voltage is generated.

Therefore, based on the above description, it is understood that the output of the gate driver 100 can intermittently generate three times the input voltage in the first mode and the second mode.

The conditions used in this embodiment for simulation and experiment are as follows: (i) the power supply voltage V _CC is +5 volts; (ii) the capacitance value of the first capacitor C ₁ is set to 10 μF; (iii) the capacitance value of the second capacitor C ₂ Set to 1μF; (iv) the capacitance of the analog gate capacitance C _gs is set to 220pF; (v) the first transistor Q ₁ and the second transistor Q ₂ use the output buffer switches of the model IXDD414P (vi) The third transistor Q ₃ , the fourth transistor Q ₄ , the fifth transistor Q _{3 ,} and the sixth transistor Q ₆ are formed by an integrated circuit of the type FDS8333C, which includes n-channel and p-channel metal oxides. The semiconductor field effect transistor; (vii) the first diode D ₁ and the second diode D ₂ are integrated circuits of the type 1N5819.

Referring to FIG. 2, FIG. 5 and FIG. 6, the voltage waveform of each component under the foregoing conditions by the gate driver 100 of FIG. 1 is used, and the switching frequencies are 10 kHz and 500 kHz, respectively, wherein the voltage of the pulse wave control signal pwm is used. Both are +5 volts, and the positive output voltage at the voltage of the energy storage element v _gs is +15 volts, showing good conversion.

Referring to FIG. 2 and FIG. 7 is a 10kHz switching frequency control signal of the PWM pulse, a first capacitor C voltage v _{C1 1,} the second voltage V ₂ of capacitor C and the energy storage element _C2 of the voltage waveform v _gs.

Referring to FIG. 2 and FIG. 8 is a pulse wave switching frequency control signal PWM 500kHz, the first capacitor C voltage v _{C1 1,} the second voltage V ₂ of capacitor C _C2 and _the energy storage element C _GS voltage waveform v _gs.

2 and FIG. 9 are waveforms of the pulse wave control signal PWM whose switching frequency is 10 kHz, the voltage v _{X1 of the} first node X ₁ , the voltage v _{X2 of the} second node X ₂ , and the voltage v _gs of the energy storage element C _gs .

2 and FIG. 10 are waveforms of the pulse wave control signal PWM whose switching frequency is 500 kHz, the voltage v _{X1 of the} first node X ₁ , the voltage v _{X2 of the} second node X ₂ , and the voltage v _gs of the energy storage element C _gs .

In summary, in the gate driver 100 and the driving method of the invention capable of generating three times of input voltage, only a single power supply is required to intermittently generate a driving signal v _{gs of} three times the output voltage to drive the gate of the n-channel MOSFET switching element. The pole (this embodiment is represented by the energy storage element C _gs ), therefore, the gate driver 100 of the present invention conforms to the simplified design of the overall circuit and has the effect of fast operation and reduced switching loss, so that the object of the present invention can be achieved.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent changes and modifications made by the patent application scope and patent specification content of the present invention, All remain within the scope of the invention patent.

100‧‧‧gate driver

10‧‧‧Drive circuit

11‧‧‧First charge pump

111‧‧‧First charging circuit

112‧‧‧First discharge circuit

113‧‧‧First clamp circuit

12‧‧‧Second charge pump

121‧‧‧Second charging circuit

122‧‧‧Second discharge circuit

123‧‧‧Second clamp circuit

B ₁ ‧‧‧Inverter

C ₁ ‧‧‧first capacitor

C ₂ ‧‧‧second capacitor

C _gs ‧‧‧ energy storage components

D ₁ ‧‧‧First Diode

D ₂ ‧‧‧Secondary

Pwm‧‧‧ pulse wave control signal

Q ₁ ‧‧‧First transistor

Q ₂ ‧‧‧Second transistor

Q ₃ ‧‧‧The third transistor

Q ₄ ‧‧‧fourth transistor

Q ₅ ‧‧‧ Fifth transistor

Q ₆ ‧‧‧ sixth transistor

V _CC ‧‧‧ input voltage

X ₁ ‧‧‧ first node

X ₂ ‧‧‧second node

Claims (4)

A gate driver capable of generating three times of input voltage, comprising: a driving circuit, is powered by a power source receiving an input voltage and has a pair of power switches, the pair of power switches collectively receiving a pulse wave control signal and the two outputs are connected to one a first node, the pulse wave control signal has a first mode and a second mode to regulate the conduction of the pair of power switches; a first charge pump having a first charging circuit, a first discharging circuit, and a first clamping circuit, the first clamping circuit includes a first diode and a first capacitor, the anode end of the first diode is coupled to the power source of the input voltage, and the cathode end of the first diode is connected in series At one end of the first capacitor, the other end of the first capacitor is connected to the first node, the first charging circuit has a third transistor, and the third transistor system is a p-channel metal oxide semiconductor field effect transistor component. The gate of the third transistor is coupled to the power supply of the input voltage, and the source terminal of the third transistor is coupled between the cathode end of the first diode and one end of the first capacitor, and the first discharge circuit has a First a fourth transistor, a fourth transistor system, an n-channel metal oxide semiconductor field effect transistor component, a gate control terminal of the fourth transistor coupled to the power source of the input voltage, and a source terminal coupling of the fourth transistor Connected to the first node, the drain of the third transistor and the drain of the fourth transistor are all coupled to a second node; and a second charge pump having a second charging loop and a second discharging loop And a second clamping circuit, the second clamping circuit comprises a second diode and a second capacitor, the anode end of the second diode is coupled to the power source of the input voltage, and the cathode end of the second diode is serially connected to one end of the second capacitor, the second capacitor The other end is connected to the second node, the second charging circuit has a fifth transistor, the fifth electro-crystalline system is a p-channel metal oxide semiconductor field effect transistor element, and the gate control end of the fifth transistor is coupled to the a power source of the input voltage, a source terminal of the fifth transistor is coupled between the cathode end of the second diode and one end of the second capacitor; the second discharge circuit has a sixth transistor, and the sixth transistor system a metal-oxide-semiconductor field-effect transistor component of the channel, a gate control terminal of the sixth transistor is coupled to the power source of the input voltage, a source terminal of the sixth transistor is coupled to the second node, and the fifth transistor is The drains of the drain and the sixth transistor are both coupled to an output terminal, and in the first mode, the first charging circuit and the second charging circuit are charged to three times the input voltage to the output terminal, and The second mode is performed by the first discharge circuit and the first Discharge circuit to discharge. The gate driver capable of generating three times the input voltage according to claim 1, wherein the pair of power switches comprises a first transistor and a second transistor, the first transistor system and a p-channel metal oxide A semiconductor field effect transistor component, the second transistor system, an n-channel metal oxide semiconductor field effect transistor component. A gate driving method capable of generating three times of input voltage, comprising the steps of: providing a driving circuit that is powered by an input voltage source and Having a pair of power switches, the pair of power switches collectively receiving a pulse wave control signal and the two outputs are coupled to a first node, the pulse wave control signal having a first mode and a second mode to regulate the pair of power switches Turning on or not; providing a first charge pump having a first charging circuit, a first discharging circuit and a first clamping circuit, the first clamping circuit comprising a first diode and a first capacitor, first The anode end of the diode is coupled to the power source of the input voltage, the cathode end of the first diode is connected in series with one end of the first capacitor, and the other end of the first capacitor is connected to the first node, and the first charging circuit has a a third transistor, a third transistor system, a p-channel metal oxide semiconductor field effect transistor device, a gate control terminal of the third transistor coupled to the power source of the input voltage, and a source terminal coupling of the third transistor Connected between the cathode end of the first diode and one end of the first capacitor, the first discharge circuit has a fourth transistor, and the fourth transistor system is an n-channel metal oxide semiconductor field effect transistor component. Four-crystal The pole control terminal is coupled to the power source of the input voltage, the source terminal of the fourth transistor is coupled to the first node, and the drain of the third transistor and the drain of the fourth transistor are coupled to a second node Providing a second charge pump having a second charging circuit, a second discharging circuit and a second clamping circuit, the second clamping circuit comprising a second diode and a second capacitor, the second diode The anode end is coupled to the power source of the input voltage, the cathode end of the second diode is serially connected to one end of the second capacitor, and the other end of the second capacitor is connected a second node, the second charging circuit has a fifth transistor, a fifth transistor system, a p-channel metal oxide semiconductor field effect transistor element, and a gate control terminal of the fifth transistor is coupled to the input voltage a power source, a source terminal of the fifth transistor is coupled between the cathode end of the second diode and one end of the second capacitor; the second discharge circuit has a sixth transistor, a sixth transistor system, and an n-channel metal An oxide semiconductor field effect transistor device, a gate control terminal of the sixth transistor is coupled to the power source of the input voltage, a source terminal of the sixth transistor is coupled to the second node, and a drain of the fifth transistor is The drain of the sixth transistor is coupled to an output terminal; and in the first mode, the first charging circuit and the second charging circuit are charged to three times the input voltage to the output terminal, and in the second mode The first discharge circuit and the second discharge circuit are discharged. The gate driving method capable of generating three times of an input voltage according to claim 3, wherein, in the first mode, the first transistor is turned on and the second transistor is not turned on, and the first diode is reversed Discharging and discharging the first capacitor, the voltage between the gate and the source of the third transistor being a negative value of the input voltage to turn on the third transistor, the gate of the fourth transistor There is no output voltage between the sources to make the fourth transistor non-conducting; the voltage between the gate and the source of the fifth transistor is twice the negative value of the input voltage, and the fifth transistor is turned on. The voltage between the gate and the source of the sixth transistor is a negative value of the input voltage to make the sixth transistor non-conductive; In the second mode, the first transistor is non-conducting and the second transistor is turned on, the first diode and the second diode are forward biased, and the first capacitor and the second capacitor are Quickly charging to the input voltage, there is no output voltage between the gate and the source of the third transistor to make the third transistor non-conductive, and the voltage between the gate and the source of the fourth transistor is Inputting a voltage to turn on the fourth transistor; meanwhile, there is no output voltage between the gate and the source of the fifth transistor to make the fifth transistor non-conductive, and the gate and source of the sixth transistor The voltage between the electrodes is the input voltage to turn on the sixth transistor.