JPH10337000A - Gate drive circuit - Google Patents
Gate drive circuitInfo
- Publication number
- JPH10337000A JPH10337000A JP14400097A JP14400097A JPH10337000A JP H10337000 A JPH10337000 A JP H10337000A JP 14400097 A JP14400097 A JP 14400097A JP 14400097 A JP14400097 A JP 14400097A JP H10337000 A JPH10337000 A JP H10337000A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor switch
- turned
- semiconductor
- voltage
- reactor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、ＭＯＳＦＥＴ，
ＩＧＢＴなどのＭＯＳゲート構造を有する電圧制御形半
導体素子をターンオン又はターンオフさせるゲート駆動
回路に関する。The present invention relates to a MOSFET,
The present invention relates to a gate drive circuit for turning on or off a voltage-controlled semiconductor device having a MOS gate structure such as an IGBT.
【０００２】[0002]
【従来の技術】図１７はこの種のゲート駆動回路の従来
例を示し、１は電圧制御形半導体素子としてのＭＯＳＦ
ＥＴ、５０はゲート駆動回路である。図１７において、
ゲート駆動回路５０は直流電源５１とトランジスタ５２
とトランジスタ５３とから構成されている。2. Description of the Related Art FIG. 17 shows a conventional example of this type of gate drive circuit, and 1 is a MOSF as a voltage control type semiconductor element.
ET and 50 are gate drive circuits. In FIG.
The gate drive circuit 50 includes a DC power supply 51 and a transistor 52.
And a transistor 53.
【０００３】このゲート駆動回路５０の動作を、図１８
に示す動作波形図を参照しつつ、以下に説明する。先
ず、トランジスタ５２をオン，トランジスタ５３をオフ
にすると、トランジスタ５２を介して期間に示すよう
な電流が流れ、ＭＯＳＦＥＴ１のゲート・ソース間の入
力容量が直流電源５１の直流電圧まで充電され、この充
電によりＭＯＳＦＥＴ１がターンオンする。The operation of the gate drive circuit 50 is shown in FIG.
This will be described below with reference to the operation waveform diagram shown in FIG. First, when the transistor 52 is turned on and the transistor 53 is turned off, a current as shown in a period flows through the transistor 52, and the input capacitance between the gate and the source of the MOSFET 1 is charged up to the DC voltage of the DC power supply 51. As a result, the MOSFET 1 is turned on.
【０００４】また、トランジスタ５２をオフ，トランジ
スタ５３をオンにすると、トランジスタ５３を介して期
間に示すような電流が流れ、ＭＯＳＦＥＴ１の入力容
量に蓄積された電荷が放電し、この放電によりＭＯＳＦ
ＥＴ１がターンオフする。When the transistor 52 is turned off and the transistor 53 is turned on, a current as shown in a period flows through the transistor 53, and the electric charge stored in the input capacitance of the MOSFET 1 is discharged.
ET1 turns off.
【０００５】[0005]
【発明が解決しようとする課題】上記従来のゲート駆動
回路５０において、直流電源５１の電圧をＶｄｃとし、
図１８に示す期間において、直流電源５１が出力する
電荷の総和をＱとすると、ＭＯＳＦＥＴ１がターンオン
するときに直流電源５１が出力するエネルギーＥｉｎ
は、式（１）で表される。In the conventional gate drive circuit 50, the voltage of the DC power supply 51 is set to Vdc,
In the period shown in FIG. 18, assuming that the sum of the charges output from the DC power supply 51 is Q, the energy Ein output from the DC power supply 51 when the MOSFET 1 is turned on.
Is represented by equation (1).
【０００６】[0006]
【数１】Ｅｉｎ＝Ｑ×Ｖｄｃ …（１） 次に、図１８に示す期間において、ＭＯＳＦＥＴ１の
入力容量に蓄積されるエネルギーＥｃｈは、式（２）で
表される。Ein = Q × Vdc (1) Next, during the period shown in FIG. 18, the energy Ech stored in the input capacitance of the MOSFET 1 is expressed by the following equation (2).
【０００７】[0007]
【数２】Ｅｃｈ＝（１／２）×Ｑ×Ｖｄｃ …（２） 従って、ＭＯＳＦＥＴ１がターンオンするときにゲート
駆動回路５０が消費するエネルギーＥｏｎは、式（３）
で表される。Ech = (1/2) × Q × Vdc (2) Therefore, the energy Eon consumed by the gate drive circuit 50 when the MOSFET 1 is turned on is given by the following equation (3).
It is represented by
【０００８】[0008]
【数３】 Ｅｏｎ＝Ｅｉｎ−Ｅｃｈ＝（１／２）×Ｑ×Ｖｄｃ …（３） 一方、ＭＯＳＦＥＴ１がターンオフするときにゲート駆
動回路５０が消費するエネルギーＥｏｆｆはＥｃｈに等
しいので、ＭＯＳＦＥＴ１が周波数ｆで繰り返してター
ンオン・ターンオフする場合、ゲート駆動回路５０の全
消費電力Ｐは、式（４）で表される。Eon = Ein−Ech = (１ ／) × Q × Vdc (3) On the other hand, when the MOSFET 1 is turned off, the energy Eoff consumed by the gate drive circuit 50 is equal to Ech. , The total power consumption P of the gate drive circuit 50 is expressed by equation (4).
【０００９】[0009]
【数４】 Ｐ＝（Ｅｏｎ＋Ｅｃｈ）×ｆ＝Ｑ×Ｖｄｃ×ｆ …（４） すなわち、式（４）において、Ｑまたはｆが大きくなる
と、ゲート駆動回路５０の消費電力が大きくなる。この
ため、入力容量の大きな電圧制御形半導体素子を採用
し、且つ前記繰り返し周波数（ｆ）を高くした場合に
は、このゲート駆動回路５０とＭＯＳＦＥＴ１とを含む
電力変換装置全体の変換効率が低下し、また、トランジ
スタ５２，トランジスタ５３には冷却フィンなどの冷却
機構が必要となり、その結果、ゲート駆動回路５０が大
型化するといった難点があった。P = (Eon + Ech) × f = Q × Vdc × f (4) That is, in equation (4), as Q or f increases, the power consumption of the gate drive circuit 50 increases. Therefore, when a voltage-controlled semiconductor device having a large input capacitance is employed and the repetition frequency (f) is increased, the conversion efficiency of the entire power conversion device including the gate drive circuit 50 and the MOSFET 1 is reduced. In addition, the transistors 52 and 53 require a cooling mechanism such as a cooling fin, and as a result, there is a problem that the gate drive circuit 50 becomes large.
【００１０】この発明の目的は、ゲート駆動回路を大型
化させず、前記装置の変換効率を向上させることにあ
る。An object of the present invention is to improve the conversion efficiency of the device without increasing the size of the gate drive circuit.
【００１１】[0011]
【課題を解決するための手段】この第１の発明は、直流
電源の正側端子と第１半導体スイッチの一端とを接続
し、直流電源の負側端子と第２半導体スイッチの一端と
を接続し、第１半導体スイッチの他端と第２半導体スイ
ッチの他端とリアクトルの一端とを接続し、電圧制御形
半導体素子のゲート端子と第３半導体スイッチの一端と
を接続し、電圧制御形半導体素子のソースまたはエミッ
タ端子と第４半導体スイッチの一端と直流電源の負側端
子とを接続し、第３半導体スイッチの他端と第４半導体
スイッチの他端とリアクトルの他端とを接続してなるゲ
ート駆動回路とする。According to the first invention, a positive terminal of a DC power supply is connected to one end of a first semiconductor switch, and a negative terminal of the DC power supply is connected to one end of a second semiconductor switch. Connecting the other end of the first semiconductor switch, the other end of the second semiconductor switch, and one end of the reactor, connecting the gate terminal of the voltage-controlled semiconductor element to one end of the third semiconductor switch, The source or emitter terminal of the element is connected to one end of the fourth semiconductor switch and the negative terminal of the DC power supply, and the other end of the third semiconductor switch is connected to the other end of the fourth semiconductor switch and the other end of the reactor. Gate drive circuit.
【００１２】この第２の発明は、第１直流電源と第２直
流電源とを直列接続し、前記第１直流電源の正側端子と
第１半導体スイッチの一端とを接続し、前記第２直流電
源の負側端子と第２半導体スイッチの一端とを接続し、
第１半導体スイッチの他端と第２半導体スイッチの他端
とリアクトルの一端とを接続し、電圧制御形半導体素子
のゲート端子と第３半導体スイッチの一端とを接続し、
電圧制御形半導体素子のソースまたはエミッタ端子と前
記第１，第２直流電源の中間接続点とを接続し、第３半
導体スイッチの他端とリアクトルの他端と第４半導体ス
イッチの一端とを接続し、第４半導体スイッチの他端と
前記第２直流電源の負側端子とを接続してなるゲート駆
動回路とする。In the second invention, a first DC power supply and a second DC power supply are connected in series, a positive terminal of the first DC power supply is connected to one end of a first semiconductor switch, and the second DC power supply is connected to the first DC power supply. Connecting the negative terminal of the power supply to one end of the second semiconductor switch,
Connecting the other end of the first semiconductor switch, the other end of the second semiconductor switch, and one end of the reactor, connecting the gate terminal of the voltage-controlled semiconductor device to one end of the third semiconductor switch,
A source or emitter terminal of the voltage controlled semiconductor device is connected to an intermediate connection point between the first and second DC power supplies, and the other end of the third semiconductor switch is connected to the other end of the reactor and one end of the fourth semiconductor switch. Then, a gate drive circuit is formed by connecting the other end of the fourth semiconductor switch and the negative terminal of the second DC power supply.
【００１３】第３の発明は前記第１又は第２の発明にお
いて、前記リアクトルに代えて、第１リアクトルと第１
ダイオードの直列回路と、第２リアクトルと第２ダイオ
ードの直列回路とを逆並列接続してなる回路としたゲー
ト駆動回路にする。第４の発明は前記第１〜第３のいず
れかの発明において、前記第１，第３半導体スイッチそ
れぞれは自己消弧形半導体素子とダイオードの逆並列回
路からなり、前記第２半導体スイッチは自己消弧形半導
体素子からなり、前記第４半導体スイッチはダイオード
からなり、前記電圧制御形半導体素子をターンオンさせ
るときには、先ず第１半導体スイッチと第３半導体スイ
ッチとをオンにし、前記リアクトルと該電圧制御形半導
体素子の入力容量とに基づき該リアクトルに流れる共振
電流が零になった時点で第３半導体スイッチをオフに
し、前記電圧制御形半導体素子をターンオフさせるとき
には、先ず第２半導体スイッチと第３半導体スイッチと
をオンにし、前記リアクトルと該電圧制御形半導体素子
の入力容量とに基づき該リアクトルに流れる共振電流が
最大となった時点より所定の期間が経過した後、第２半
導体スイッチをオフ，第１半導体スイッチをオンにす
る。In a third aspect based on the first or second aspect, the first reactor and the first reactor are replaced with the first reactor.
The gate drive circuit is a circuit in which a series circuit of a diode and a series circuit of a second reactor and a second diode are connected in anti-parallel. In a fourth aspect based on any one of the first to third aspects, each of the first and third semiconductor switches comprises an anti-parallel circuit of a self-extinguishing semiconductor element and a diode, and the second semiconductor switch comprises The fourth semiconductor switch is composed of a diode, and the fourth semiconductor switch is composed of a diode. When turning on the voltage-controlled semiconductor element, first, the first semiconductor switch and the third semiconductor switch are turned on, and the reactor and the voltage control are turned on. When the third semiconductor switch is turned off when the resonance current flowing through the reactor becomes zero based on the input capacitance of the semiconductor device and the voltage-controlled semiconductor device is turned off, first, the second semiconductor switch and the third semiconductor switch are turned off. A switch is turned on and a current flows through the reactor based on the reactor and the input capacitance of the voltage-controlled semiconductor device. After a predetermined period of time has elapsed from the time the resonant current is maximized that, the second semiconductor switch off, to turn on the first semiconductor switch.
【００１４】第５の発明は前記第１〜第３のいずれかの
発明において、前記第１，第３，第４半導体スイッチそ
れぞれは自己消弧形半導体素子とダイオードの逆並列回
路からなり、前記第２半導体スイッチは自己消弧形半導
体素子からなり、前記電圧制御形半導体素子をターンオ
ンさせるときには、先ず第１半導体スイッチと第４半導
体スイッチとを所定の期間オンにした後、第４半導体ス
イッチをオフ，第３半導体スイッチをオンにし、前記リ
アクトルと該電圧制御形半導体素子の入力容量とに基づ
き該リアクトルに流れる共振電流が零になった時点で第
３半導体スイッチをオフにし、前記電圧制御形半導体素
子をターンオフさせるときには、先ず第２半導体スイッ
チと第３半導体スイッチとをオンにし、前記リアクトル
と該電圧制御形半導体素子の入力容量とに基づき該リア
クトルに流れる共振電流が最大となった時点で第４半導
体スイッチをオンにし、所定の期間が経過した後、第２
半導体スイッチをオフ，第１半導体スイッチをオンにす
る。In a fifth aspect based on any one of the first to third aspects, each of the first, third and fourth semiconductor switches comprises an anti-parallel circuit of a self-extinguishing semiconductor element and a diode. The second semiconductor switch is composed of a self-extinguishing semiconductor element. When turning on the voltage-controlled semiconductor element, the first semiconductor switch and the fourth semiconductor switch are first turned on for a predetermined period, and then the fourth semiconductor switch is turned on. Off, turning on the third semiconductor switch; turning off the third semiconductor switch when the resonance current flowing through the reactor becomes zero based on the reactor and the input capacitance of the voltage-controlled semiconductor device; When the semiconductor element is turned off, first, the second semiconductor switch and the third semiconductor switch are turned on, and the reactor and the voltage control type half are turned on. After resonant current flowing through the reactor based on the input capacitance of the body element to turn on the fourth semiconductor switch at the time of the maximum, predetermined period of time, the second
The semiconductor switch is turned off, and the first semiconductor switch is turned on.
【００１５】第６の発明は前記第１〜第３のいずれかの
発明において、前記第１乃至第３半導体スイッチそれぞ
れは、自己消弧形半導体素子とダイオードの逆並列回路
からなり、前記第４半導体スイッチはダイオードからな
り、前記電圧制御形半導体素子をターンオンさせるとき
には、先ず第１半導体スイッチと第３半導体スイッチと
を前記リアクトルと該電圧制御形半導体素子の入力容量
とに基づく共振動作の１／４周期以内の期間オンにした
後、第１半導体スイッチをオフ，第２半導体スイッチを
オンにし、前記リアクトルと該電圧制御形半導体素子の
入力容量とに基づき該リアクトルに流れる共振電流が零
になった時点で第３半導体スイッチをオフにし、前記電
圧制御形半導体素子をターンオフさせるときには、先ず
第２半導体スイッチと第３半導体スイッチとをオンし、
前記リアクトルと該電圧制御形半導体素子の入力容量と
に基づき該リアクトルに流れる共振電流が最大となった
時点より所定の期間が経過した後、第２半導体スイッチ
をオフ，第１半導体スイッチをオンにする。In a sixth aspect based on any one of the first to third aspects, each of the first to third semiconductor switches comprises an anti-parallel circuit of a self-extinguishing semiconductor element and a diode, and The semiconductor switch is composed of a diode. When turning on the voltage-controlled semiconductor device, first, the first semiconductor switch and the third semiconductor switch are connected to the reactor and the input / output capacitance of the voltage-controlled semiconductor device by one-half of the resonance operation. After turning on for a period of four cycles or less, the first semiconductor switch is turned off and the second semiconductor switch is turned on, and the resonance current flowing through the reactor becomes zero based on the reactor and the input capacitance of the voltage-controlled semiconductor device. When the third semiconductor switch is turned off at the time when the voltage-controlled semiconductor device is turned off, first, the second semiconductor switch is turned off. Turned on and the third semiconductor switch,
Based on the reactor and the input capacitance of the voltage-controlled semiconductor element, after a predetermined period has elapsed from the point in time when the resonance current flowing through the reactor has become maximum, the second semiconductor switch is turned off and the first semiconductor switch is turned on. I do.
【００１６】第７の発明は前記第１〜第３のいずれかの
発明において、前記第１乃至第４半導体スイッチそれぞ
れは自己消弧形半導体素子とダイオードの逆並列回路か
らなり、前記電圧制御形半導体素子をターンオンさせる
ときには、先ず第１半導体スイッチと第４半導体スイッ
チとを所定の期間オンにした後、第１半導体スイッチと
第４半導体スイッチとをオフ，第２半導体スイッチと第
３半導体スイッチをオンにし、前記リアクトルと該電圧
制御形半導体素子の入力容量とに基づき該リアクトルに
流れる共振電流が零になった時点で第３半導体スイッチ
をオフにし、前記電圧制御形半導体素子をターンオフさ
せるときには、先ず第２半導体スイッチと第３半導体ス
イッチをオンにし、前記リアクトルと該電圧制御形半導
体素子の入力容量とに基づき該リアクトルに流れる共振
電流が最大となった時点で第４半導体スイッチをオンに
し、所定の期間が経過した後、第２半導体スイッチをオ
フ，第１半導体スイッチをオンにする。According to a seventh aspect of the present invention, in any one of the first to third aspects, each of the first to fourth semiconductor switches comprises an anti-parallel circuit of a self-extinguishing semiconductor device and a diode. When turning on the semiconductor element, first, the first semiconductor switch and the fourth semiconductor switch are turned on for a predetermined period, then the first semiconductor switch and the fourth semiconductor switch are turned off, and the second semiconductor switch and the third semiconductor switch are turned on. Turning on, turning off the third semiconductor switch when the resonance current flowing through the reactor becomes zero based on the reactor and the input capacitance of the voltage-controlled semiconductor device, and turning off the voltage-controlled semiconductor device, First, the second semiconductor switch and the third semiconductor switch are turned on, and the reactor and the input capacitance of the voltage-controlled semiconductor device are turned on. Resonance current flowing through the reactor on the basis of the turns on the fourth semiconductor switch at the time of the maximum, after a predetermined period of time has elapsed, the second semiconductor switch off, to turn on the first semiconductor switch.
【００１７】第８の発明は前記第１〜第３のいずれかの
発明において、前記第１，第３，第４半導体スイッチそ
れぞれは自己消弧形半導体素子とダイオードの逆並列回
路からなり、前記第２半導体スイッチは省略し、前記電
圧制御形半導体素子をターンオフさせるときには、先ず
第１半導体スイッチと第４半導体スイッチとを所定の期
間オンした後、第４半導体スイッチをオフ，第３半導体
スイッチをオンにし、前記リアクトルと該電圧制御形半
導体素子の入力容量とに基づき該リアクトルに流れる共
振電流が零になった時点で第３半導体スイッチをオフに
し、前記電圧制御形半導体素子をターンオフさせるとき
には、先ず第１半導体スイッチと第３半導体スイッチと
をオンにし、該電圧制御形半導体素子のゲート端子とソ
ースまたはエミッタ端子間の電圧が所定の値となった時
点で第４半導体スイッチをオンにし、所定の期間が経過
した後、第１半導体スイッチをオンにする。In an eighth aspect based on any one of the first to third aspects, each of the first, third and fourth semiconductor switches comprises an anti-parallel circuit of a self-extinguishing semiconductor element and a diode. The second semiconductor switch is omitted, and when the voltage-controlled semiconductor device is turned off, first the first semiconductor switch and the fourth semiconductor switch are turned on for a predetermined period, then the fourth semiconductor switch is turned off, and the third semiconductor switch is turned off. Turning on, turning off the third semiconductor switch when the resonance current flowing through the reactor becomes zero based on the reactor and the input capacitance of the voltage-controlled semiconductor device, and turning off the voltage-controlled semiconductor device, First, the first semiconductor switch and the third semiconductor switch are turned on, and the gate terminal of the voltage controlled semiconductor device is connected to the source or the emitter. Voltage across the terminals turns on the fourth semiconductor switch when it reaches a predetermined value, after a predetermined period of time has elapsed, to turn on the first semiconductor switch.
【００１８】第９の発明は前記第１〜第３のいずれかの
発明において、前記第１，第３，第４半導体スイッチそ
れぞれは自己消弧形半導体素子とダイオードの逆並列回
路からなり、前記第２半導体スイッチはダイオードから
なり、前記電圧制御形半導体素子をターンオフさせると
きには、先ず第１半導体スイッチと第４半導体スイッチ
とを所定の期間オンした後、第４半導体スイッチをオ
フ，第３半導体スイッチをオンにし、前記リアクトルと
該電圧制御形半導体素子の入力容量とに基づき該リアク
トルに流れる共振電流が零になった時点で第３半導体ス
イッチをオフにし、前記電圧制御形半導体素子をターン
オフさせるときには、先ず第１半導体スイッチと第３半
導体スイッチとをオンにし、該電圧制御形半導体素子の
ゲート端子とソースまたはエミッタ端子間の電圧が所定
の値となった時点で第４半導体スイッチをオンにし、所
定の期間が経過した後、第１半導体スイッチをオンにす
る。In a ninth aspect based on any of the first to third aspects, each of the first, third and fourth semiconductor switches comprises an anti-parallel circuit of a self-extinguishing semiconductor element and a diode. The second semiconductor switch is composed of a diode. When turning off the voltage-controlled semiconductor device, first, the first semiconductor switch and the fourth semiconductor switch are turned on for a predetermined period, then the fourth semiconductor switch is turned off, and the third semiconductor switch is turned off. To turn on, turn off the third semiconductor switch when the resonance current flowing through the reactor becomes zero based on the reactor and the input capacitance of the voltage-controlled semiconductor device, and turn off the voltage-controlled semiconductor device. First, the first semiconductor switch and the third semiconductor switch are turned on, and the gate terminal and the source of the voltage controlled semiconductor device are turned on. Other turns on the fourth semiconductor switch when the voltage between the emitter terminal becomes a predetermined value, after a predetermined period of time has elapsed, to turn on the first semiconductor switch.
【００１９】第１０の発明は前記第５又は第７〜第９の
いずれかの発明において、前記電圧制御形半導体素子が
ターンオフを完了し、再度ターンオンする迄の期間は、
第１半導体スイッチをオフにし、第３，第４半導体スイ
ッチをオンにする。この発明によれば、後述の如く、ゲ
ート駆動回路に備えたリアクトルと前記電圧制御形半導
体素子の入力容量とに基づく共振動作を利用して、該入
力容量に蓄積したエネルギーを直流電源に回生すること
により、該ゲート駆動回路と電圧制御形半導体素子とを
含む電力変換装置全体の変換効率を向上させている。In a tenth aspect based on any one of the fifth or seventh to ninth aspects, the period from when the voltage-controlled semiconductor element has been turned off to when it is turned on again is:
The first semiconductor switch is turned off, and the third and fourth semiconductor switches are turned on. According to the present invention, as described later, energy stored in the input capacitance is regenerated to the DC power supply using a resonance operation based on the reactor provided in the gate drive circuit and the input capacitance of the voltage-controlled semiconductor element. Thereby, the conversion efficiency of the entire power conversion device including the gate drive circuit and the voltage control type semiconductor element is improved.
【００２０】[0020]
【発明の実施の形態】図１は、この発明の第１の実施の
形態を示すゲート駆動回路の構成図である。図１におい
て、１は電圧制御形半導体素子としてのＭＯＳＦＥＴ
１、４０はゲート駆動回路を示し、このゲート駆動回路
４０は直流電源１１と、第１半導体スイッチ２１と、第
２半導体スイッチ２２と、第３半導体スイッチ２３と、
第４半導体スイッチ２４と、リアクトル３１とから構成
されている。FIG. 1 is a configuration diagram of a gate drive circuit showing a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a MOSFET as a voltage control type semiconductor device.
Reference numerals 1 and 40 denote gate drive circuits. The gate drive circuit 40 includes a DC power supply 11, a first semiconductor switch 21, a second semiconductor switch 22, and a third semiconductor switch 23.
It comprises a fourth semiconductor switch 24 and a reactor 31.
【００２１】図２は、この発明の第２の実施の形態を示
すゲート駆動回路の構成図であり、図１に示した構成図
と同一機能を有するものには同一符号を付している。す
なわち図２に示すゲート駆動回路４１は第１直流電源と
しての直流電源１１と第２直流電源としての直流電源１
２とを直列接続した直流電源と、第１〜第４半導体スイ
ッチ２１〜２４と、リアクトル３１とから構成されてい
る。FIG. 2 is a configuration diagram of a gate drive circuit according to a second embodiment of the present invention. Components having the same functions as those of the configuration diagram shown in FIG. 1 are denoted by the same reference numerals. That is, the gate drive circuit 41 shown in FIG. 2 includes the DC power supply 11 as the first DC power supply and the DC power supply 1 as the second DC power supply.
2 are connected in series, a first to fourth semiconductor switches 21 to 24, and a reactor 31.
【００２２】図３は、この発明の第３の実施の形態を示
すゲート駆動回路の構成図であり、図１に示した構成図
と同一機能を有するものには同一符号を付している。す
なわち図３に示すゲート駆動回路４２は図１に示したゲ
ート駆動回路４０のリアクトル３１に代えて、第１リア
クトルとしてのリアクトル３２と第１ダイオードとして
のダイオード３３とからなる直列回路と、第２リアクト
ルとしてのリアクトル３４と第２ダイオードとしてのダ
イオード３５とからなる直列回路とを、図示の如く逆並
列接続した回路にしている。FIG. 3 is a configuration diagram of a gate drive circuit according to a third embodiment of the present invention. Components having the same functions as those of the configuration diagram shown in FIG. 1 are denoted by the same reference numerals. That is, the gate drive circuit 42 shown in FIG. 3 replaces the reactor 31 of the gate drive circuit 40 shown in FIG. 1 with a series circuit including a reactor 32 as a first reactor and a diode 33 as a first diode, and a second circuit. As shown, a series circuit including a reactor 34 as a reactor and a diode 35 as a second diode is connected in anti-parallel as shown in the figure.
【００２３】図４は、この発明の第４の実施の形態を示
すゲート駆動回路の構成図であり、図２，３に示した構
成図と同一機能を有するものには同一符号を付してい
る。すなわち図４に示すゲート駆動回路４３は図２に示
したゲート駆動回路４１のリアクトル３１に代えて、リ
アクトル３２とダイオード３３とリアクトル３４とダイ
オード３５とからなる回路にしている。FIG. 4 is a configuration diagram of a gate drive circuit according to a fourth embodiment of the present invention. Components having the same functions as those of the configuration diagrams shown in FIGS. I have. That is, the gate drive circuit 43 shown in FIG. 4 is a circuit including the reactor 32, the diode 33, the reactor 34, and the diode 35 instead of the reactor 31 of the gate drive circuit 41 shown in FIG.
【００２４】以下に記載するこの発明の実施例の動作波
形図において、各半導体スイッチの電流は、縦軸原点に
対し上（＋）方向は各半導体スイッチのいずれかを構成
する自己消弧形半導体素子に流れることを示し、また縦
軸原点に対し下（−）方向は前記自己消弧形半導体素子
に逆並列接続をしたダイオード（ＭＯＳＦＥＴの寄生ダ
イオードも含む）、または各半導体スイッチのいずれか
がダイオードのみからなるときの該ダイオードに流れる
ことを示している。In the operation waveform diagram of the embodiment of the present invention described below, the current of each semiconductor switch indicates a self-extinguishing type semiconductor constituting one of the semiconductor switches in an upward (+) direction with respect to the origin of the vertical axis. In this case, a diode (including a parasitic diode of a MOSFET) or a semiconductor switch connected in antiparallel to the self-extinguishing type semiconductor element is shown below (−) direction with respect to the origin of the vertical axis. This shows that the current flows through the diode when only the diode is used.
【００２５】図５はこの発明の第１の実施例を示す動作
波形図であり、図１に示した駆動回路４０の第１半導体
スイッチ２１としてソース端子を直流電源１１の正側端
子に接続したＰチャネルＭＯＳＦＥＴ（寄生ダイオード
を含む、以下同じ））２１ａを、第２半導体スイッチ２
２としてエミッタ端子を直流電源１１の負側端子に接続
したＮＰＮトランジスタ２２ｂを、第３半導体スイッチ
２３としてソース端子をＭＯＳＦＥＴ１のゲート端子に
接続したＰチャネルＭＯＳＦＥＴ（寄生ダイオードを含
む、以下同じ））２３ａを、第４半導体スイッチ２４と
してアノード端子を直流電源１１の負側端子に接続した
ダイオード２４ｃを備えた場合の動作波形図を示してい
る。FIG. 5 is an operation waveform diagram showing the first embodiment of the present invention. The source terminal is connected to the positive terminal of the DC power supply 11 as the first semiconductor switch 21 of the drive circuit 40 shown in FIG. A P-channel MOSFET (including a parasitic diode, hereinafter the same) 21a is connected to the second semiconductor switch 2
NPN transistor 22b having an emitter terminal connected to the negative terminal of DC power supply 11 as P2, and P-channel MOSFET (including a parasitic diode, the same applies hereinafter) 23a having a source terminal connected to the gate terminal of MOSFET 1 as third semiconductor switch 23 FIG. 9 shows an operation waveform diagram in the case where a diode 24c having an anode terminal connected to the negative terminal of the DC power supply 11 is provided as the fourth semiconductor switch 24.
【００２６】図５において、ＭＯＳＦＥＴ１をターンオ
ンさせるときには、先ずＭＯＳＦＥＴ２１ａとＭＯＳＦ
ＥＴ２３ａとをオンにすることにより、ＭＯＳＦＥＴ２
１ａ→リアクトル３１→ＭＯＳＦＥＴ２３ａの経路で、
期間に示すようなリアクトル３１とＭＯＳＦＥＴ１の
入力容量とに基づく共振電流が流れる。この共振電流が
零になった時点、すなわちＭＯＳＦＥＴ１のゲート・ソ
ース間電圧が最大となった時点でＭＯＳＦＥＴ２３ａを
オフにすることにより、ＭＯＳＦＥＴ１のゲート・ソー
ス間電圧は直流電源１１の電圧Ｖｄｃのほぼ２倍の値と
なる。In FIG. 5, when the MOSFET 1 is turned on, first, the MOSFET 21a and the MOSF
By turning on ET23a, MOSFET2
1a → reactor 31 → MOSFET 23a
A resonance current based on the reactor 31 and the input capacitance of the MOSFET 1 flows as shown in the period. By turning off the MOSFET 23a when the resonance current becomes zero, that is, when the voltage between the gate and source of the MOSFET 1 becomes the maximum, the voltage between the gate and source of the MOSFET 1 becomes approximately two times the voltage Vdc of the DC power supply 11. The value is doubled.
【００２７】また、ＭＯＳＦＥＴ１をターンオフさせる
ときには、先ずトランジスタ２２ｂとＭＯＳＦＥＴ２３
ａとをオンにすることにより、ＭＯＳＦＥＴ２３ａ→リ
アクトル３１→トランジスタ２２ｂの経路で、期間に
示すようなリアクトル３１とＭＯＳＦＥＴ１の入力容量
とに基づく共振電流が流れる。この共振電流が最大にな
った時点、すなわちＭＯＳＦＥＴ１のゲート・ソース間
電圧が零となった時点よりダイオード２４ｃがオンし、
期間に示すようにダイオード２４ｃ→リアクトル３１
→トランジスタ２２ｂの経路で前記電流が還流する。こ
の期間が所定の時間経過した後、トランジスタ２２ｂ
をオフ，ＭＯＳＦＥＴ２１ａをオンにすることにより、
期間に示すようにリアクトル３１に蓄積されたエネル
ギーがダイオード２４ｃ→リアクトル３１→ＭＯＳＦＥ
Ｔ２１ａの経路で、直流電源１１に回生される。When the MOSFET 1 is turned off, first, the transistor 22b and the MOSFET 23
By turning on a, a resonance current based on the reactor 31 and the input capacitance of the MOSFET 1 as shown in the period flows through the path of the MOSFET 23a → the reactor 31 → the transistor 22b. The diode 24c is turned on when the resonance current becomes maximum, that is, when the gate-source voltage of the MOSFET 1 becomes zero,
As shown in the period, the diode 24c → the reactor 31
→ The current flows through the path of the transistor 22b. After a lapse of a predetermined period of time, the transistor 22b
Is turned off and the MOSFET 21a is turned on,
As shown in the period, the energy stored in the reactor 31 is changed from the diode 24c to the reactor 31 to the MOSFE.
The power is regenerated to the DC power supply 11 through the path of T21a.
【００２８】図６はこの発明の第２の実施例を示す動作
波形図であり、図２に示した駆動回路４１の第１半導体
スイッチ２１としてソース端子を直流電源１１の正側端
子に接続したＰチャネルＭＯＳＦＥＴ２１ａを、第２半
導体スイッチ２２としてエミッタ端子を直流電源１２の
負側端子に接続したＮＰＮトランジスタ２２ｂを、第３
半導体スイッチ２３としてソース端子をＭＯＳＦＥＴ１
のゲート端子に接続したＰチャネルＭＯＳＦＥＴ２３ａ
を、第４半導体スイッチ２４としてアノード端子を直流
電源１２の負側端子に接続したダイオード２４ｃを備え
た場合の動作波形図を示している。FIG. 6 is an operation waveform diagram showing a second embodiment of the present invention. The source terminal is connected to the positive terminal of the DC power supply 11 as the first semiconductor switch 21 of the drive circuit 41 shown in FIG. An NPN transistor 22b having an emitter terminal connected to the negative terminal of the DC power supply 12 as a second semiconductor switch 22 as a second semiconductor switch 22
The source terminal is MOSFET1 as the semiconductor switch 23
P-channel MOSFET 23a connected to the gate terminal of
FIG. 9 shows an operation waveform diagram in the case where a diode 24c having an anode terminal connected to the negative terminal of the DC power supply 12 is provided as the fourth semiconductor switch 24.
【００２９】この第２の実施例に基づく期間〜の動
作は、図５に示した第１の実施例の期間〜の動作と
ほぼ同じであるが、直流電源１１の電圧をＶｄｃ1 ，直
流電源１２の電圧をＶｄｃ2 とすると、期間が終了時
点でＭＯＳＦＥＴ１のゲート・ソース間電圧はほぼ〔２
×Ｖｄｃ1 ＋Ｖｄｃ2 〕となり、また、期間の終了時
点でＭＯＳＦＥＴ１のゲート・ソース間電圧は〔−Ｖｄ
ｃ2 〕となる。The operation during the period 1 based on the second embodiment is substantially the same as the operation during the period 1 according to the first embodiment shown in FIG. 5, except that the voltage of the DC power supply 11 is Vdc 1 , When a voltage of 12 to Vdc 2, the gate-source voltage of the period at the end MOSFET1 almost [2
× Vdc 1 + Vdc 2 ], and at the end of the period, the gate-source voltage of the MOSFET 1 is [−Vd 1
c 2 ].
【００３０】図７はこの発明の第３の実施例を示す動作
波形図であり、図１に示した駆動回路４０の第１半導体
スイッチ２１としてソース端子を直流電源１１の正側端
子に接続したＰチャネルＭＯＳＦＥＴ２１ａを、第２半
導体スイッチ２２としてエミッタ端子を直流電源１１の
負側端子に接続したＮＰＮトランジスタ２２ｂを、第３
半導体スイッチ２３としてソース端子をＭＯＳＦＥＴ１
のゲート端子に接続したＰチャネルＭＯＳＦＥＴ２３ａ
を、第４半導体スイッチ２４としてソース端子を直流電
源１１の負側端子に接続したＮチャネルＭＯＳＦＥＴ
（寄生ダイオードを含む、以下同じ））２４ａを備えた
場合の動作波形図を示している。FIG. 7 is an operation waveform diagram showing a third embodiment of the present invention. The source terminal is connected to the positive terminal of the DC power supply 11 as the first semiconductor switch 21 of the drive circuit 40 shown in FIG. An NPN transistor 22b having a P-channel MOSFET 21a as a second semiconductor switch 22 and an emitter terminal connected to the negative terminal of the DC power supply 11,
The source terminal is MOSFET1 as the semiconductor switch 23
P-channel MOSFET 23a connected to the gate terminal of
Is an N-channel MOSFET having a source terminal connected to the negative terminal of the DC power supply 11 as the fourth semiconductor switch 24.
(Including a parasitic diode, the same applies hereinafter)) shows an operation waveform diagram in the case of including a 24a.
【００３１】図７において、ＭＯＳＦＥＴ１をターンオ
ンさせるときには、先ずＭＯＳＦＥＴ２１ａとＭＯＳＦ
ＥＴ２４ａとを所定の期間オンにすることにより、ＭＯ
ＳＦＥＴ２１ａ→リアクトル３１→ＭＯＳＦＥＴ２４ａ
の経路で、期間に示す如くリアクトル３１に充電電流
が流れる。次にＭＯＳＦＥＴ２４ａをオフ，ＭＯＳＦＥ
Ｔ２３ａをオンにすることにより、ＭＯＳＦＥＴ２１ａ
→リアクトル３１→ＭＯＳＦＥＴ２３ａの経路で、期間
に示すようなリアクトル３１とＭＯＳＦＥＴ１の入力
容量とに基づく共振電流が流れる。この共振電流が零に
なった時点、すなわちＭＯＳＦＥＴ１のゲート・ソース
間電圧が最大となった時点でＭＯＳＦＥＴ２３ａをオフ
にする。このとき期間の時間を調整することにより、
ＭＯＳＦＥＴ１のゲート・ソース間電圧は、直流電源１
１の電圧Ｖｄｃの２倍以上の値で任意の値にできる。In FIG. 7, when the MOSFET 1 is turned on, first, the MOSFET 21a and the MOSF
By turning on the ET 24a for a predetermined period, the MO
SFET 21a → reactor 31 → MOSFET 24a
The charging current flows through the reactor 31 through the route as shown in the period. Next, the MOSFET 24a is turned off,
By turning on T23a, MOSFET 21a
A resonance current based on the reactor 31 and the input capacitance of the MOSFET 1 flows as shown in a period through the path from the reactor 31 to the MOSFET 23a. When the resonance current becomes zero, that is, when the gate-source voltage of the MOSFET 1 becomes the maximum, the MOSFET 23a is turned off. By adjusting the time of the period at this time,
The gate-source voltage of MOSFET 1 is
The value can be set to an arbitrary value with a value that is twice or more the voltage Vdc of 1.
【００３２】また、ＭＯＳＦＥＴ１をターンオフさせる
ときには、先ずトランジスタ２２ｂとＭＯＳＦＥＴ２３
ａとをオンにすることにより、ＭＯＳＦＥＴ２３ａ→リ
アクトル３１→トランジスタ２２ｂの経路で、期間に
示すようなリアクトル３１とＭＯＳＦＥＴ１の入力容量
とに基づく共振電流が流れる。この共振電流が最大にな
った時点、すなわちＭＯＳＦＥＴ１のゲート・ソース間
電圧が零となった時点よりＭＯＳＦＥＴ２４ａをオンに
し、期間に示すようにＭＯＳＦＥＴ２４ａ→リアクト
ル３１→トランジスタ２２ｂの経路で前記電流が還流す
る。この期間が所定の時間経過した後、トランジスタ
２２ｂをオフ，ＭＯＳＦＥＴ２１ａをオンにすることに
より、期間に示すようにリアクトル３１に蓄積された
エネルギーがＭＯＳＦＥＴ２４ａ→リアクトル３１→Ｍ
ＯＳＦＥＴ２１ａの経路で、直流電源１１に回生され
る。When the MOSFET 1 is turned off, first, the transistor 22b and the MOSFET 23
By turning on a, a resonance current based on the reactor 31 and the input capacitance of the MOSFET 1 as shown in the period flows through the path of the MOSFET 23a → the reactor 31 → the transistor 22b. The MOSFET 24a is turned on when the resonance current becomes maximum, that is, when the gate-source voltage of the MOSFET 1 becomes zero, and as shown in the period, the current recirculates through the path of the MOSFET 24a → the reactor 31 → the transistor 22b. . After a predetermined time has elapsed in this period, the transistor 22b is turned off and the MOSFET 21a is turned on, so that the energy stored in the reactor 31 is changed from the MOSFET 24a to the reactor 31 to the M as shown in the period.
It is regenerated by the DC power supply 11 through the path of the OSFET 21a.
【００３３】図８はこの発明の第４の実施例を示す動作
波形図であり、図２に示した駆動回路４１の第１半導体
スイッチ２１としてソース端子を直流電源１１の正側端
子に接続したＰチャネルＭＯＳＦＥＴ２１ａを、第２半
導体スイッチ２２としてエミッタ端子を直流電源１２の
負側端子に接続したＮＰＮトランジスタ２２ｂを、第３
半導体スイッチ２３としてソース端子をＭＯＳＦＥＴ１
のゲート端子に接続したＰチャネルＭＯＳＦＥＴ２３ａ
を、第４半導体スイッチ２４としてソース端子を直流電
源１２の負側端子に接続したＮチャネルＭＯＳＦＥＴ２
４ａを備えた場合の動作波形図を示している。FIG. 8 is an operation waveform diagram showing a fourth embodiment of the present invention. The source terminal is connected to the positive terminal of the DC power supply 11 as the first semiconductor switch 21 of the drive circuit 41 shown in FIG. An NPN transistor 22b having an emitter terminal connected to the negative terminal of the DC power supply 12 as a second semiconductor switch 22 as a second semiconductor switch 22
The source terminal is MOSFET1 as the semiconductor switch 23
P-channel MOSFET 23a connected to the gate terminal of
An N-channel MOSFET 2 having a source terminal connected to the negative terminal of the DC power supply 12 as a fourth semiconductor switch 24.
FIG. 4 shows an operation waveform diagram in the case where 4a is provided.
【００３４】この第４の実施例に基づく期間〜の動
作は、図７に示した第３の実施例の期間〜の動作と
ほぼ同じであるが、直流電源１１の電圧をＶｄｃ1 ，直
流電源１２の電圧をＶｄｃ2 とすると、期間が終了時
点でＭＯＳＦＥＴ１のゲート・ソース間電圧は〔２×Ｖ
ｄｃ1 ＋Ｖｄｃ2 〕以上となり、また、期間の終了時
点でＭＯＳＦＥＴ１のゲート・ソース間電圧は〔−Ｖｄ
ｃ2 〕となる。The operation during the period of the fourth embodiment is substantially the same as the operation during the period of the third embodiment shown in FIG. 7, except that the voltage of the DC power supply 11 is Vdc 1 , When a voltage of 12 to Vdc 2, the gate-source voltage of the period at the end MOSFET1 the [2 × V
dc 1 + Vdc 2 ] or more, and at the end of the period, the voltage between the gate and the source of MOSFET 1 becomes [−Vd
c 2 ].
【００３５】図９はこの発明の第５の実施例を示す動作
波形図であり、図１に示した駆動回路４０の第１半導体
スイッチ２１としてソース端子を直流電源１１の正側端
子に接続したＰチャネルＭＯＳＦＥＴ（寄生ダイオード
を含む）２１ａを、第２半導体スイッチ２２としてソー
ス端子を直流電源１１の負側端子に接続したＮチャネル
ＭＯＳＦＥＴ（寄生ダイオードを含む）２２ａを、第３
半導体スイッチ２３としてソース端子をＭＯＳＦＥＴ１
のゲート端子に接続したＰチャネルＭＯＳＦＥＴ（寄生
ダイオードを含む）２３ａを、第４半導体スイッチ２４
としてアノード端子直流電源１１の負側端子に接続した
ダイオード２４ｃを備えた場合の動作波形図を示してい
る。FIG. 9 is an operation waveform diagram showing a fifth embodiment of the present invention. The source terminal is connected to the positive terminal of the DC power supply 11 as the first semiconductor switch 21 of the drive circuit 40 shown in FIG. A P-channel MOSFET (including a parasitic diode) 21a having a source terminal connected to the negative terminal of the DC power supply 11 as a second semiconductor switch 22;
The source terminal is MOSFET1 as the semiconductor switch 23
P-channel MOSFET (including a parasitic diode) 23a connected to the gate terminal of the fourth semiconductor switch 24
7 shows an operation waveform diagram in the case where a diode 24c connected to the negative terminal of the anode terminal DC power supply 11 is provided.
【００３６】図９において、ＭＯＳＦＥＴ１をターンオ
ンさせるときには、先ずＭＯＳＦＥＴ２１ａとＭＯＳＦ
ＥＴ２３ａとをオンにすることにより、ＭＯＳＦＥＴ２
１ａ→リアクトル３１→ＭＯＳＦＥＴ２３ａの経路で、
期間に示すようなリアクトル３１とＭＯＳＦＥＴ１の
入力容量とに基づく共振電流が流れる。このとき期間
がリアクトル３１とＭＯＳＦＥＴ１の入力容量とに基づ
く共振動作の１／４周期以内にＭＯＳＦＥＴ２１ａをオ
フ，ＭＯＳＦＥＴ２２ａをオンにすることにより、ＭＯ
ＳＦＥＴ２２ａ→リアクトル３１→ＭＯＳＦＥＴ２３ａ
の経路で、期間に示すようなリアクトル３１とＭＯＳ
ＦＥＴ１の入力容量とに基づく共振電流が流れる。この
共振電流が零になった時点、すなわちＭＯＳＦＥＴ１の
ゲート・ソース間電圧が最大となった時点でＭＯＳＦＥ
Ｔ２３ａをオフにする。このとき期間の時間を調整す
ることでＭＯＳＦＥＴ１のゲート・ソース間電圧は、直
流電源１１の電圧Ｖｄｃの２倍以下の任意の値にするこ
とができる。In FIG. 9, when the MOSFET 1 is turned on, first, the MOSFET 21a and the MOSF
By turning on ET23a, MOSFET2
1a → reactor 31 → MOSFET 23a
A resonance current based on the reactor 31 and the input capacitance of the MOSFET 1 flows as shown in the period. At this time, the MOSFET 21a is turned off and the MOSFET 22a is turned on within a quarter cycle of the resonance operation based on the reactor 31 and the input capacitance of the MOSFET 1, whereby the MO
SFET22a → reactor 31 → MOSFET23a
The reactor 31 and MOS as shown in the period
A resonance current based on the input capacitance of the FET 1 flows. When the resonance current becomes zero, that is, when the gate-source voltage of the MOSFET 1 becomes maximum, the MOSFE
Turn off T23a. At this time, by adjusting the time of the period, the voltage between the gate and the source of the MOSFET 1 can be set to an arbitrary value equal to or less than twice the voltage Vdc of the DC power supply 11.
【００３７】この第５の実施例において、ＭＯＳＦＥＴ
１をターンオフさせるとき（図９の期間〜）は、図
５に示した第１の実施例の期間〜の動作と同一であ
るので、その説明を省略する。図１０はこの発明の第６
の実施例を示す動作波形図であり、図２に示した駆動回
路４１の第１半導体スイッチ２１としてソース端子を直
流電源１１の正側端子に接続したＰチャネルＭＯＳＦＥ
Ｔ２１ａを、第２半導体スイッチ２２としてソース端子
を直流電源１２の負側端子に接続したＮチャネルＭＯＳ
ＦＥＴ（寄生ダイオードを含む、以下同じ）２２ａを、
第３半導体スイッチ２３としてソース端子をＭＯＳＦＥ
Ｔ１のゲート端子に接続したＰチャネルＭＯＳＦＥＴ２
３ａを、第４半導体スイッチ２４としてアノード端子直
流電源１２の負側端子に接続したダイオード２４ｃを備
えた場合の動作波形図を示している。In the fifth embodiment, the MOSFET
9 is turned off (period of FIG. 9), the operation is the same as that of period 1 of the first embodiment shown in FIG. 5, and the description thereof is omitted. FIG. 10 shows a sixth embodiment of the present invention.
FIG. 3 is an operation waveform diagram showing an embodiment of the present invention, and a P-channel MOSFET having a source terminal connected to the positive terminal of the DC power supply 11 as the first semiconductor switch 21 of the drive circuit 41 shown in FIG.
T21a is an N-channel MOS having a source terminal connected to the negative terminal of the DC power supply 12 as the second semiconductor switch 22
FET (including a parasitic diode, the same applies hereinafter) 22a
The source terminal is MOSFE as the third semiconductor switch 23
P-channel MOSFET2 connected to the gate terminal of T1
FIG. 3 shows an operation waveform diagram in the case where a diode 24c is connected to the negative terminal of the anode terminal DC power supply 12 as the fourth semiconductor switch 24.
【００３８】この第６の実施例に基づく期間〜の動
作は、図９に示した第５の実施例の期間〜の動作と
ほぼ同じであるが、直流電源１１の電圧をＶｄｃ1 ，直
流電源１２の電圧をＶｄｃ2 とすると、期間が終了時
点でＭＯＳＦＥＴ１のゲート・ソース間電圧は〔２×Ｖ
ｄｃ1 ＋Ｖｄｃ2 〕以下となり、また、期間の終了時
点でＭＯＳＦＥＴ１のゲート・ソース間電圧は〔−Ｖｄ
ｃ2 〕となる。The operation during the period from the sixth embodiment is substantially the same as the operation during the period from the fifth embodiment shown in FIG. 9, except that the voltage of the DC power supply 11 is Vdc 1 , When a voltage of 12 to Vdc 2, the gate-source voltage of the period at the end MOSFET1 the [2 × V
dc 1 + Vdc 2 ] or less, and at the end of the period, the gate-source voltage of the MOSFET 1 becomes [−Vd
c 2 ].
【００３９】図１１はこの発明の第７の実施例を示す動
作波形図であり、図１に示した駆動回路４０の第１半導
体スイッチ２１としてソース端子を直流電源１１の正側
端子に接続したＰチャネルＭＯＳＦＥＴ２１ａを、第２
半導体スイッチ２２としてソース端子を直流電源１１の
負側端子に接続したＮチャネルＭＯＳＦＥＴ２２ａを、
第３半導体スイッチ２３としてソース端子をＭＯＳＦＥ
Ｔ１のゲート端子に接続したＰチャネルＭＯＳＦＥＴ２
３ａを、第４半導体スイッチ２４としてソース端子を直
流電源１１の負側端子に接続したＮチャネルＭＯＳＦＥ
Ｔ２４ａを備えた場合の動作波形図を示している。FIG. 11 is an operation waveform diagram showing a seventh embodiment of the present invention. The source terminal is connected to the positive terminal of the DC power supply 11 as the first semiconductor switch 21 of the drive circuit 40 shown in FIG. The P-channel MOSFET 21a is connected to the second
An N-channel MOSFET 22 a having a source terminal connected to the negative terminal of the DC power supply 11 as the semiconductor switch 22,
The source terminal is MOSFE as the third semiconductor switch 23
P-channel MOSFET2 connected to the gate terminal of T1
An N-channel MOSFET 3a having a source terminal connected to the negative terminal of the DC power supply 11 as a fourth semiconductor switch 24;
FIG. 9 shows an operation waveform diagram in a case where T24a is provided.
【００４０】図１１において、ＭＯＳＦＥＴ１をターン
オンさせるときには、先ずＭＯＳＦＥＴ２１ａとＭＯＳ
ＦＥＴ２４ａとを所定の期間オンにすることにより、Ｍ
ＯＳＦＥＴ２１ａ→リアクトル３１→ＭＯＳＦＥＴ２４
ａの経路で、期間に示す如くリアクトル３１に充電電
流が流れる。次にＭＯＳＦＥＴ２１ａをオフ，ＭＯＳＦ
ＥＴ２４ａをオフ，ＭＯＳＦＥＴ２２ａをオン，ＭＯＳ
ＦＥＴ２３ａをオンにすることにより、ＭＯＳＦＥＴ２
２ａ→リアクトル３１→ＭＯＳＦＥＴ２３ａの経路で、
期間に示すようなリアクトル３１とＭＯＳＦＥＴ１の
入力容量とに基づく共振電流が流れる。この共振電流が
零になった時点、すなわちＭＯＳＦＥＴ１のゲート・ソ
ース間電圧が最大となった時点でＭＯＳＦＥＴ２３ａを
オフにする。このとき期間の時間を調整することによ
り、ＭＯＳＦＥＴ１のゲート・ソース間電圧は、直流電
源１１の電圧Ｖｄｃによらず任意の値にできる。In FIG. 11, when the MOSFET 1 is turned on, first, the MOSFET 21a and the MOS
By turning on the FET 24a for a predetermined period, M
OSFET 21a → reactor 31 → MOSFET 24
In the path a, a charging current flows through the reactor 31 as shown in the period. Next, the MOSFET 21a is turned off, and the MOSF
ET24a off, MOSFET22a on, MOS
By turning on the FET 23a, the MOSFET 2
2a → reactor 31 → MOSFET 23a
A resonance current based on the reactor 31 and the input capacitance of the MOSFET 1 flows as shown in the period. When the resonance current becomes zero, that is, when the gate-source voltage of the MOSFET 1 becomes the maximum, the MOSFET 23a is turned off. At this time, by adjusting the period, the gate-source voltage of the MOSFET 1 can be set to an arbitrary value regardless of the voltage Vdc of the DC power supply 11.
【００４１】この第７の実施例において、ＭＯＳＦＥＴ
１をターンオフさせるときには、図７に示した第３の実
施例の動作と同一であるので、その説明を省略する。図
１２はこの発明の第８の実施例を示す動作波形図であ
り、図２に示した駆動回路４１の第１半導体スイッチ２
１としてソース端子を直流電源１１の正側端子に接続し
たＰチャネルＭＯＳＦＥＴ２１ａを、第２半導体スイッ
チ２２としてソース端子を直流電源１２の負側端子に接
続したＮチャネルＭＯＳＦＥＴ２２ａを、第３半導体ス
イッチ２３としてソース端子をＭＯＳＦＥＴ１のゲート
端子に接続したＰチャネルＭＯＳＦＥＴ２３ａを、第４
半導体スイッチ２４としてソース端子を直流電源１２の
負側端子に接続したＮチャネルＭＯＳＦＥＴ２４ａを備
えた場合の動作波形図を示している。In the seventh embodiment, the MOSFET
The operation of turning off 1 is the same as the operation of the third embodiment shown in FIG. FIG. 12 is an operation waveform diagram showing an eighth embodiment of the present invention, wherein the first semiconductor switch 2 of the drive circuit 41 shown in FIG.
A P-channel MOSFET 21a having a source terminal connected to the positive terminal of the DC power supply 11 as 1; an N-channel MOSFET 22a having a source terminal connected to the negative terminal of the DC power supply 12 as the second semiconductor switch 22; A P-channel MOSFET 23a having a source terminal connected to the gate terminal of MOSFET 1 is connected to a fourth
FIG. 3 shows an operation waveform diagram in a case where an N-channel MOSFET 24 a having a source terminal connected to the negative terminal of the DC power supply 12 is provided as the semiconductor switch 24.
【００４２】この第８の実施例に基づく期間〜の動
作は、図１１に示した第７の実施例の期間〜の動作
とほぼ同じであるが、直流電源１１の電圧をＶｄｃ1 ，
直流電源１２の電圧をＶｄｃ2 とすると、期間が終了
時点でＭＯＳＦＥＴ１のゲート・ソース間電圧はＶｄｃ
1 やＶｄｃ2 によらず任意の値にでき、また、期間の
終了時点でＭＯＳＦＥＴ１のゲート・ソース間電圧は
〔−Ｖｄｃ2 〕となる。The operation during the period from the eighth embodiment is substantially the same as the operation during the period from the seventh embodiment shown in FIG. 11, except that the voltage of the DC power supply 11 is Vdc 1 ,
Assuming that the voltage of the DC power supply 12 is Vdc 2 , the gate-source voltage of the MOSFET 1 becomes Vdc at the end of the period.
Can be any value regardless of the 1 and Vdc 2, also the gate-source voltage of MOSFET1 at the end of the period is [-Vdc 2].
【００４３】図１３はこの発明の第９の実施例を示す動
作波形図であり、図１に示した駆動回路４０の第１半導
体スイッチ２１としてソース端子を直流電源１１の正側
端子に接続したＰチャネルＭＯＳＦＥＴ２１ａを、第３
半導体スイッチ２３としてソース端子をＭＯＳＦＥＴ１
のゲート端子に接続したＰチャネルＭＯＳＦＥＴ２３ａ
を、第４半導体スイッチ２４としてソース端子を直流電
源１１の負側端子に接続したＮチャネルＭＯＳＦＥＴ２
４ａを備え、第２半導体スイッチ２２を省略した場合の
動作波形図を示している。FIG. 13 is an operation waveform diagram showing a ninth embodiment of the present invention. The source terminal is connected to the positive terminal of the DC power supply 11 as the first semiconductor switch 21 of the drive circuit 40 shown in FIG. The P-channel MOSFET 21a is connected to the third
The source terminal is MOSFET1 as the semiconductor switch 23
P-channel MOSFET 23a connected to the gate terminal of
An N-channel MOSFET 2 having a source terminal connected to the negative terminal of the DC power supply 11 as a fourth semiconductor switch 24.
4A shows an operation waveform diagram when the second semiconductor switch 22 is omitted.
【００４４】この第９の実施例において、ＭＯＳＦＥＴ
１をターンオンさせるときには、図７に示した第３の実
施例の動作と同一であるので、その説明を省略する。図
１３において、ＭＯＳＦＥＴ１をターンオフさせるとき
には、先ずＭＯＳＦＥＴ２１ａとＭＯＳＦＥＴ２３ａと
をオンにすることにより、ＭＯＳＦＥＴ２３ａ→リアク
トル３１→ＭＯＳＦＥＴ２１ａの経路で、期間に示す
ようなリアクトル３１とＭＯＳＦＥＴ１の入力容量とに
基づく共振電流が流れる。次にＭＯＳＦＥＴ１のゲート
・ソース間電圧が零となった時点よりＭＯＳＦＥＴ２４
ａをオンにし、期間に示すようにＭＯＳＦＥＴ２４ａ
→リアクトル３１→ＭＯＳＦＥＴ２１ａの経路で、リア
クトル３１に蓄積されたエネルギーが直流電源１１に回
生される。In the ninth embodiment, the MOSFET
1 is turned on, the operation is the same as that of the third embodiment shown in FIG. In FIG. 13, when the MOSFET 1 is turned off, first, the MOSFET 21a and the MOSFET 23a are turned on, so that a resonance current based on the reactor 31 and the input capacitance of the MOSFET 1 as shown in a period is shown in a path of the MOSFET 23a → the reactor 31 → the MOSFET 21a. Flows. Next, when the voltage between the gate and the source of the MOSFET 1 becomes zero, the MOSFET 24
a to turn on the MOSFET 24a as shown in the period.
The energy stored in the reactor 31 is regenerated to the DC power supply 11 via the path from the reactor 31 to the MOSFET 21a.
【００４５】図１４はこの発明の第１０の実施例を示す
動作波形図であり、図２に示した駆動回路４１の第１半
導体スイッチ２１としてソース端子を直流電源１１の正
側端子に接続したＰチャネルＭＯＳＦＥＴ２１ａを、第
３半導体スイッチ２３としてソース端子をＭＯＳＦＥＴ
１のゲート端子に接続したＰチャネルＭＯＳＦＥＴ２３
ａを、第４半導体スイッチ２４としてソース端子を直流
電源１２の負側端子に接続したＮチャネルＭＯＳＦＥＴ
２４ａを備え、第２半導体スイッチ２２を省略した場合
の動作波形図を示している。FIG. 14 is an operation waveform diagram showing a tenth embodiment of the present invention. The source terminal is connected to the positive terminal of the DC power supply 11 as the first semiconductor switch 21 of the drive circuit 41 shown in FIG. The P-channel MOSFET 21a is used as the third semiconductor switch 23, and the source terminal is MOSFET.
P-channel MOSFET 23 connected to the gate terminal 1
a is an N-channel MOSFET having a source terminal connected to the negative terminal of the DC power supply 12 as the fourth semiconductor switch 24
24A shows an operation waveform diagram when the second semiconductor switch 22 is omitted and the second semiconductor switch 22 is omitted.
【００４６】この第１０の実施例に基づく期間〜の
動作は、図１３に示した第９の実施例の期間〜の動
作とほぼ同じであるが、直流電源１１の電圧をＶｄ
ｃ1 ，直流電源１２の電圧をＶｄｃ2 とすると、期間
が終了時点でＭＯＳＦＥＴ１のゲート・ソース間電圧
は、〔２×Ｖｄｃ1 ＋Ｖｄｃ2 〕以上となり、また、期
間の終了時点でＭＯＳＦＥＴ１のゲート・ソース間電
圧は〔−Ｖｄｃ2 〕となる。The operation during the period from the tenth embodiment is substantially the same as the operation during the period from the ninth embodiment shown in FIG. 13 except that the voltage of the DC power supply 11 is
Assuming that c 1 and the voltage of the DC power supply 12 are Vdc 2 , the gate-source voltage of the MOSFET 1 at the end of the period becomes [2 × Vdc 1 + Vdc 2 ] or more, and the gate / source voltage of the MOSFET 1 at the end of the period. The source-to-source voltage becomes [−Vdc 2 ].
【００４７】図１５はこの発明の第１１の実施例を示す
動作波形図であり、図１に示した駆動回路４０の第１半
導体スイッチ２１としてソース端子を直流電源１１の正
側端子に接続したＰチャネルＭＯＳＦＥＴ２１ａを、第
２半導体スイッチ２２としてアノード端子を直流電源１
１の負側端子に接続したダイオード２２ｃを、第３半導
体スイッチ２３としてソース端子をＭＯＳＦＥＴ１のゲ
ート端子に接続したＰチャネルＭＯＳＦＥＴ２３ａを、
第４半導体スイッチ２４としてソース端子を直流電源１
１の負側端子に接続したＮチャネルＭＯＳＦＥＴ２４ａ
を備えた場合の動作波形図を示している。FIG. 15 is an operation waveform diagram showing an eleventh embodiment of the present invention. The source terminal is connected to the positive terminal of the DC power supply 11 as the first semiconductor switch 21 of the drive circuit 40 shown in FIG. The P-channel MOSFET 21a is used as the second semiconductor switch 22 and the anode terminal is connected to the DC power supply 1
1, a P-channel MOSFET 23a having a source terminal connected to the gate terminal of the MOSFET 1 as a third semiconductor switch 23;
As the fourth semiconductor switch 24, the source terminal is the DC power supply 1
N-channel MOSFET 24a connected to the negative terminal of 1
FIG. 5 shows an operation waveform diagram in the case where the device is provided.
【００４８】この第１１の実施例において、ＭＯＳＦＥ
Ｔ１をターンオンさせるときには、図１１に示した第７
の実施例の動作と同一であるので、その説明を省略す
る。また、ＭＯＳＦＥＴ１をターンオフさせるときに
は、図１３に示した第９の実施例の動作と同一であるの
で、その説明を省略する。図１６はこの発明の第１２の
実施例を示す動作波形図であり、図２に示した駆動回路
４１の第１半導体スイッチ２１としてソース端子を直流
電源１１の正側端子に接続したＰチャネルＭＯＳＦＥＴ
２１ａを、第２半導体スイッチ２２としてアノード端子
を直流電源１２の負側端子に接続したダイオード２２ｃ
を、第３半導体スイッチ２３としてソース端子をＭＯＳ
ＦＥＴ１のゲート端子に接続したＰチャネルＭＯＳＦＥ
Ｔ２３ａを、第４半導体スイッチ２４としてソース端子
を直流電源１２の負側端子に接続したＮチャネルＭＯＳ
ＦＥＴ２４ａを備えた場合の動作波形図を示している。In the eleventh embodiment, the MOSFE
When turning on T1, the seventh switch shown in FIG.
Since the operation is the same as that of the embodiment, its description is omitted. When the MOSFET 1 is turned off, the operation is the same as that of the ninth embodiment shown in FIG. FIG. 16 is an operation waveform diagram showing a twelfth embodiment of the present invention, wherein a P-channel MOSFET having a source terminal connected to the positive terminal of the DC power supply 11 as the first semiconductor switch 21 of the drive circuit 41 shown in FIG.
A diode 22c having an anode terminal connected to the negative terminal of the DC power supply 12 as a second semiconductor switch 22;
And the source terminal is MOS as the third semiconductor switch 23.
P-channel MOSFET connected to the gate terminal of FET1
T23a is an N-channel MOS having a source terminal connected to the negative terminal of the DC power supply 12 as a fourth semiconductor switch 24;
FIG. 4 shows an operation waveform diagram when the FET 24a is provided.
【００４９】この第１２の実施例において、ＭＯＳＦＥ
Ｔ１をターンオンさせるときには、図１２に示した第８
の実施例の動作と同一であり、またＭＯＳＦＥＴ１をタ
ーンオフさせるときには、図１４に示した第１０の実施
例の動作と同一であるので、その説明を省略する。な
お、上述したこの発明の実施例においては、例えば、第
１半導体スイッチ２１と第３半導体スイッチとはＰチャ
ネルＭＯＳＦＥＴ（寄生ダイオードを含む）を使用した
例について述べたが、ＮチャネルＭＯＳＦＥＴ（寄生ダ
イオードを含む）やバイポーラトランジスタとダイオー
ドの逆並列回路も使用してもよい。In the twelfth embodiment, the MOSFE
When turning T1 on, the eighth switch shown in FIG.
The operation of this embodiment is the same as that of the tenth embodiment, and when the MOSFET 1 is turned off, the operation is the same as that of the tenth embodiment shown in FIG. In the embodiment of the present invention described above, for example, an example in which the first semiconductor switch 21 and the third semiconductor switch use P-channel MOSFETs (including a parasitic diode) has been described. And an anti-parallel circuit of a bipolar transistor and a diode.
【００５０】また、上述した第３，第４，第７〜第１２
の実施例において、ＭＯＳＦＥＴ１がターンオフを完了
し、再度ターンオンする迄の期間は、ＭＯＳＦＥＴ２１
ａをオフにし、ＭＯＳＦＥＴ２３ａとＭＯＳＦＥＴ２４
ａとをオンにすることにより、ＭＯＳＦＥＴ１のゲート
・ソース間電圧を０または−Ｖｄｃ2 に固定できるの
で、この間のＭＯＳＦＥＴ１の誤オンが防止できる。Further, the third, fourth, seventh to twelfth described above
In the embodiment of the present invention, the period from the time when the MOSFET 1 completes the turn-off to the time when the MOSFET 1 is turned on again is the MOSFET 21.
a is turned off, and the MOSFETs 23a and 24
By turning on the a, since the gate-source voltage of the MOSFET 1 can be secured to 0 or -Vdc 2, prevents erroneous ON during this time MOSFET 1.
【００５１】さらに、上述の実施例の動作を図３に示し
たゲート駆動回路４２又は図４に示したゲート駆動回路
４３に適用した場合には、ＭＯＦＥＴ１がターンオンす
るときにはリアクトル３２とダイオード３３の経路を利
用し、ＭＯＦＥＴ１がターンオフするときにはリアクト
ル３４とダイオード３５の経路を利用することにより、
ＭＯＦＥＴ１のゲート・ソース間電圧の立ち上がり時間
と立ち下がり時間とを個別且つ任意に設定することがで
きる。Further, when the operation of the above-described embodiment is applied to the gate drive circuit 42 shown in FIG. 3 or the gate drive circuit 43 shown in FIG. 4, the path between the reactor 32 and the diode 33 when the MOSFET 1 is turned on. By using the path of the reactor 34 and the diode 35 when the MOSFET 1 is turned off,
The rise time and fall time of the gate-source voltage of the MOSFET 1 can be set individually and arbitrarily.
【００５２】[0052]
【発明の効果】この発明によれば、前記電圧制御形半導
体素子のターンオン時にリアクトルと該素子の入力容量
とによる共振を利用して該入力容量を充電するため、タ
ーンオン時のゲート駆動回路での損失を少なくでき、ま
た、該素子のターンオフ時に該素子の入力容量がターン
オン時に蓄積したエネルギーを直流電源に回生するの
で、該素子のターンオフ時のゲート駆動回路での損失が
少なくなる。その結果、ゲート駆動回路が小型化し、こ
のゲート駆動回路とＭＯＳＦＥＴ，ＩＧＢＴなどの電圧
制御形半導体素子を含む電力変換装置全体の変換効率が
改善されるため、例えば携帯用機器などで１個の小型蓄
電池より数種類の直流電圧を必要とする電力変換装置に
適している。According to the present invention, when the voltage-controlled semiconductor device is turned on, the input capacitance is charged by utilizing the resonance between the reactor and the input capacitance of the device. The loss can be reduced, and the input capacitance of the element regenerates the energy accumulated at the time of turn-on to the DC power supply when the element is turned off. Therefore, the loss in the gate drive circuit when the element is turned off is reduced. As a result, the size of the gate drive circuit is reduced, and the conversion efficiency of the entire power conversion device including the gate drive circuit and a voltage-controlled semiconductor element such as MOSFET, IGBT, etc. is improved. It is suitable for power converters that require several types of DC voltage than storage batteries.
【００５３】さらに、ＭＯＳＦＥＴ，ＩＧＢＴなどの入
力容量の充電電圧は任意に設定できるので、例えば、前
記蓄電池のように電圧が変動する直流電源を用いたとき
にも該充電電圧をほぼ一定値にでき、電力変換装置の制
御回路用の低電圧の直流電源を用いて該充電電圧を該直
流電源より高い値にでき、電力変換装置の主回路用の高
電圧の直流電源を用いて該充電電圧を該直流電源より低
い値にできる。Further, since the charging voltage of the input capacitance of the MOSFET, IGBT and the like can be set arbitrarily, the charging voltage can be set to a substantially constant value even when a DC power supply whose voltage fluctuates as in the storage battery, for example. The charging voltage can be set to a higher value than the DC power supply using a low-voltage DC power supply for a control circuit of the power conversion device, and the charging voltage can be changed using a high-voltage DC power supply for the main circuit of the power conversion device. It can be lower than the DC power supply.
【図１】この発明の第１の実施の形態を示すゲート駆動
回路の構成図FIG. 1 is a configuration diagram of a gate drive circuit according to a first embodiment of the present invention;
【図２】この発明の第２の実施の形態を示すゲート駆動
回路の構成図FIG. 2 is a configuration diagram of a gate drive circuit according to a second embodiment of the present invention;
【図３】この発明の第３の実施の形態を示すゲート駆動
回路の構成図FIG. 3 is a configuration diagram of a gate drive circuit according to a third embodiment of the present invention;
【図４】この発明の第４の実施の形態を示すゲート駆動
回路の構成図FIG. 4 is a configuration diagram of a gate drive circuit according to a fourth embodiment of the present invention;
【図５】この発明の第１の実施例を示すゲート駆動回路
の動作波形図FIG. 5 is an operation waveform diagram of the gate drive circuit according to the first embodiment of the present invention;
【図６】この発明の第２の実施例を示すゲート駆動回路
の動作波形図FIG. 6 is an operation waveform diagram of a gate drive circuit showing a second embodiment of the present invention.
【図７】この発明の第３の実施例を示すゲート駆動回路
の動作波形図FIG. 7 is an operation waveform diagram of a gate drive circuit showing a third embodiment of the present invention.
【図８】この発明の第４の実施例を示すゲート駆動回路
の動作波形図FIG. 8 is an operation waveform diagram of a gate drive circuit showing a fourth embodiment of the present invention.
【図９】この発明の第５の実施例を示すゲート駆動回路
の動作波形図FIG. 9 is an operation waveform diagram of a gate drive circuit according to a fifth embodiment of the present invention.
【図１０】この発明の第６の実施例を示すゲート駆動回
路の動作波形図FIG. 10 is an operation waveform diagram of a gate drive circuit showing a sixth embodiment of the present invention.
【図１１】この発明の第７の実施例を示すゲート駆動回
路の動作波形図FIG. 11 is an operation waveform diagram of a gate drive circuit according to a seventh embodiment of the present invention.
【図１２】この発明の第８の実施例を示すゲート駆動回
路の動作波形図FIG. 12 is an operation waveform diagram of a gate drive circuit showing an eighth embodiment of the present invention.
【図１３】この発明の第９の実施例を示すゲート駆動回
路の動作波形図FIG. 13 is an operation waveform diagram of a gate drive circuit showing a ninth embodiment of the present invention.
【図１４】この発明の第１０の実施例を示すゲート駆動
回路の動作波形図FIG. 14 is an operation waveform diagram of a gate drive circuit according to a tenth embodiment of the present invention.
【図１５】この発明の第１１の実施例を示すゲート駆動
回路の動作波形図FIG. 15 is an operation waveform diagram of a gate drive circuit showing an eleventh embodiment of the present invention.
【図１６】この発明の第１２の実施例を示すゲート駆動
回路の動作波形図FIG. 16 is an operation waveform diagram of a gate drive circuit showing a twelfth embodiment of the present invention.
【図１７】従来例を示すゲート駆動回路の構成図FIG. 17 is a configuration diagram of a gate drive circuit showing a conventional example.
【図１８】図１７に示したゲート駆動回路の動作波形図18 is an operation waveform diagram of the gate drive circuit shown in FIG.
１…ＭＯＳＦＥＴ、１１，１２…直流電源、２１…第１
半導体スイッチ、２１ａ…ＭＯＳＦＥＴ、２２…第２半
導体スイッチ、２２ａ…ＭＯＳＦＥＴ、２２ｂ…トラン
ジスタ、２２ｃ…ダイオード、２３…第１半導体スイッ
チ、２３ａ…ＭＯＳＦＥＴ、２４…第４半導体スイッ
チ、２４ａ…ＭＯＳＦＥＴ、２４ｃ…ダイオード、３
１，３２，３４…リアクトル、３３，３５…ダイオー
ド、４０〜４３，５０…ゲート駆動回路、５１…直流電
源、５２，５３…トランジスタ。1: MOSFET, 11, 12: DC power supply, 21: First
Semiconductor switch, 21a MOSFET, 22 second semiconductor switch, 22a MOSFET, 22b transistor, 22c diode, 23 first semiconductor switch, 23a MOSFET, 24 fourth semiconductor switch, 24a MOSFET, 24c Diode, 3
1, 32, 34: reactor, 33, 35: diode, 40 to 43, 50: gate drive circuit, 51: DC power supply, 52, 53: transistor.
Claims (10)
の一端とを接続し、直流電源の負側端子と第２半導体ス
イッチの一端とを接続し、 第１半導体スイッチの他端と第２半導体スイッチの他端
とリアクトルの一端とを接続し、 電圧制御形半導体素子のゲート端子と第３半導体スイッ
チの一端とを接続し、 電圧制御形半導体素子のソースまたはエミッタ端子と第
４半導体スイッチの一端と直流電源の負側端子とを接続
し、 第３半導体スイッチの他端と第４半導体スイッチの他端
とリアクトルの他端とを接続したことを特徴とするゲー
ト駆動回路。A first terminal connected to the positive terminal of the DC power supply and one end of the first semiconductor switch; a negative terminal connected to the one end of the second semiconductor switch connected to the negative terminal of the DC power supply; (2) connecting the other end of the semiconductor switch to one end of the reactor, connecting the gate terminal of the voltage-controlled semiconductor device to one end of the third semiconductor switch, and connecting the source or emitter terminal of the voltage-controlled semiconductor device to the fourth semiconductor switch And a negative terminal of the DC power supply, and the other end of the third semiconductor switch, the other end of the fourth semiconductor switch, and the other end of the reactor are connected.
し、 前記第１直流電源の正側端子と第１半導体スイッチの一
端とを接続し、 前記第２直流電源の負側端子と第２半導体スイッチの一
端とを接続し、 第１半導体スイッチの他端と第２半導体スイッチの他端
とリアクトルの一端とを接続し、 電圧制御形半導体素子のゲート端子と第３半導体スイッ
チの一端とを接続し、 電圧制御形半導体素子のソースまたはエミッタ端子と前
記第１，第２直流電源の中間接続点とを接続し、 第３半導体スイッチの他端とリアクトルの他端と第４半
導体スイッチの一端とを接続し、 第４半導体スイッチの他端と前記第２直流電源の負側端
子とを接続したことを特徴とするゲート駆動回路。2. A first DC power supply and a second DC power supply are connected in series, a positive terminal of the first DC power supply is connected to one end of a first semiconductor switch, and a negative terminal of the second DC power supply is connected. And the other end of the second semiconductor switch, the other end of the first semiconductor switch, the other end of the second semiconductor switch, and one end of the reactor, and the gate terminal of the voltage-controlled semiconductor device and the third semiconductor switch. One end of the third semiconductor switch, the other end of the reactor, the fourth semiconductor, and the other end of the third semiconductor switch. A gate drive circuit, wherein one end of the switch is connected, and the other end of the fourth semiconductor switch is connected to the negative terminal of the second DC power supply.
回路において、 前記リアクトルに代えて、第１リアクトルと第１ダイオ
ードの直列回路と、第２リアクトルと第２ダイオードの
直列回路とを逆並列接続してなる回路としたことを特徴
とするゲート駆動回路。3. The gate drive circuit according to claim 1, wherein a series circuit of a first reactor and a first diode, and a series circuit of a second reactor and a second diode are used instead of the reactor. A gate drive circuit, wherein the gate drive circuit is connected in anti-parallel.
ゲート駆動回路において、 前記第１，第３半導体スイッチそれぞれは自己消弧形半
導体素子とダイオードの逆並列回路からなり、 前記第２半導体スイッチは自己消弧形半導体素子からな
り、 前記第４半導体スイッチはダイオードからなり、 前記電圧制御形半導体素子をターンオンさせるときに
は、先ず第１半導体スイッチと第３半導体スイッチとを
オンにし、前記リアクトルと該電圧制御形半導体素子の
入力容量とに基づき該リアクトルに流れる共振電流が零
になった時点で第３半導体スイッチをオフにし、 前記電圧制御形半導体素子をターンオフさせるときに
は、先ず第２半導体スイッチと第３半導体スイッチとを
オンにし、前記リアクトルと該電圧制御形半導体素子の
入力容量とに基づき該リアクトルに流れる共振電流が最
大となった時点より所定の期間が経過した後、第２半導
体スイッチをオフ，第１半導体スイッチをオンにするこ
とを特徴とするゲート駆動回路。4. The gate drive circuit according to claim 1, wherein each of the first and third semiconductor switches comprises an anti-parallel circuit of a self-extinguishing semiconductor device and a diode. The second semiconductor switch is composed of a self-extinguishing semiconductor element, the fourth semiconductor switch is composed of a diode, and when turning on the voltage-controlled semiconductor element, first, the first semiconductor switch and the third semiconductor switch are turned on. When the resonance current flowing through the reactor becomes zero based on the reactor and the input capacitance of the voltage-controlled semiconductor device, the third semiconductor switch is turned off. A switch and a third semiconductor switch are turned on, and the reactor and the input capacitance of the voltage-controlled semiconductor device are turned on. After resonant current flowing through the reactor has elapsed a predetermined time period from the time when the maximum based on, off the second semiconductor switch, the gate drive circuit, characterized in that to turn on the first semiconductor switch.
ゲート駆動回路において、 前記第１，第３，第４半導体スイッチそれぞれは自己消
弧形半導体素子とダイオードの逆並列回路からなり、 前記第２半導体スイッチは自己消弧形半導体素子からな
り、 前記電圧制御形半導体素子をターンオンさせるときに
は、先ず第１半導体スイッチと第４半導体スイッチとを
所定の期間オンにした後、第４半導体スイッチをオフ，
第３半導体スイッチをオンにし、前記リアクトルと該電
圧制御形半導体素子の入力容量とに基づき該リアクトル
に流れる共振電流が零になった時点で第３半導体スイッ
チをオフにし、 前記電圧制御形半導体素子をターンオフさせるときに
は、先ず第２半導体スイッチと第３半導体スイッチとを
オンにし、前記リアクトルと該電圧制御形半導体素子の
入力容量とに基づき該リアクトルに流れる共振電流が最
大となった時点で第４半導体スイッチをオンにし、所定
の期間が経過した後、第２半導体スイッチをオフ，第１
半導体スイッチをオンにすることを特徴とするゲート駆
動回路。5. The gate drive circuit according to claim 1, wherein each of said first, third, and fourth semiconductor switches comprises an anti-parallel circuit of a self-extinguishing semiconductor element and a diode. The second semiconductor switch comprises a self-extinguishing semiconductor device. When turning on the voltage-controlled semiconductor device, first, the first semiconductor switch and the fourth semiconductor switch are turned on for a predetermined period, and then the fourth semiconductor switch is turned on. Switch off,
Turning on a third semiconductor switch, turning off the third semiconductor switch when the resonance current flowing through the reactor becomes zero based on the reactor and the input capacitance of the voltage-controlled semiconductor device, Is turned off, first, the second semiconductor switch and the third semiconductor switch are turned on, and when the resonance current flowing through the reactor becomes maximum based on the reactor and the input capacitance of the voltage-controlled semiconductor device, the fourth semiconductor switch is turned on. After the semiconductor switch is turned on and a predetermined period has elapsed, the second semiconductor switch is turned off and the first semiconductor switch is turned off.
A gate drive circuit characterized by turning on a semiconductor switch.
ゲート駆動回路において、 前記第１乃至第３半導体スイッチそれぞれは、自己消弧
形半導体素子とダイオードの逆並列回路からなり、 前記第４半導体スイッチはダイオードからなり、 前記電圧制御形半導体素子をターンオンさせるときに
は、先ず第１半導体スイッチと第３半導体スイッチとを
前記リアクトルと該電圧制御形半導体素子の入力容量と
に基づく共振動作の１／４周期以内の期間オンにした
後、第１半導体スイッチをオフ，第２半導体スイッチを
オンにし、前記リアクトルと該電圧制御形半導体素子の
入力容量とに基づき該リアクトルに流れる共振電流が零
になった時点で第３半導体スイッチをオフにし、 前記電圧制御形半導体素子をターンオフさせるときに
は、先ず第２半導体スイッチと第３半導体スイッチとを
オンし、前記リアクトルと該電圧制御形半導体素子の入
力容量とに基づき該リアクトルに流れる共振電流が最大
となった時点より所定の期間が経過した後、第２半導体
スイッチをオフ，第１半導体スイッチをオンにすること
を特徴とするゲート駆動回路。6. The gate drive circuit according to claim 1, wherein each of said first to third semiconductor switches comprises an anti-parallel circuit of a self-turn-off semiconductor element and a diode. The fourth semiconductor switch is composed of a diode. When turning on the voltage-controlled semiconductor device, first, the first semiconductor switch and the third semiconductor switch are turned on and off in a resonance operation based on the reactor and the input capacitance of the voltage-controlled semiconductor device. After the first semiconductor switch is turned off and the second semiconductor switch is turned on after being turned on for a period of less than 1/4 cycle, the resonance current flowing through the reactor becomes zero based on the reactor and the input capacitance of the voltage controlled semiconductor device. When the third semiconductor switch is turned off at the time when the voltage control type semiconductor device is turned off, A semiconductor switch and a third semiconductor switch are turned on, and after a predetermined period elapses from a point in time when a resonance current flowing through the reactor becomes maximum based on the reactor and an input capacitance of the voltage-controlled semiconductor element, a second switch is turned on. A gate drive circuit characterized by turning off a semiconductor switch and turning on a first semiconductor switch.
ゲート駆動回路において、 前記第１乃至第４半導体スイッチそれぞれは自己消弧形
半導体素子とダイオードの逆並列回路からなり、 前記電圧制御形半導体素子をターンオンさせるときに
は、先ず第１半導体スイッチと第４半導体スイッチとを
所定の期間オンにした後、第１半導体スイッチと第４半
導体スイッチとをオフ，第２半導体スイッチと第３半導
体スイッチをオンにし、前記リアクトルと該電圧制御形
半導体素子の入力容量とに基づき該リアクトルに流れる
共振電流が零になった時点で第３半導体スイッチをオフ
にし、 前記電圧制御形半導体素子をターンオフさせるときに
は、先ず第２半導体スイッチと第３半導体スイッチをオ
ンにし、前記リアクトルと該電圧制御形半導体素子の入
力容量とに基づき該リアクトルに流れる共振電流が最大
となった時点で第４半導体スイッチをオンにし、所定の
期間が経過した後、第２半導体スイッチをオフ，第１半
導体スイッチをオンにすること特徴とするゲート駆動回
路。7. The gate drive circuit according to claim 1, wherein each of said first to fourth semiconductor switches comprises an anti-parallel circuit of a self-extinguishing semiconductor device and a diode, and When turning on the control-type semiconductor device, first, the first semiconductor switch and the fourth semiconductor switch are turned on for a predetermined period, then the first semiconductor switch and the fourth semiconductor switch are turned off, and the second semiconductor switch and the third semiconductor switch are turned on. Turning on the switch, turning off the third semiconductor switch when the resonance current flowing through the reactor becomes zero based on the reactor and the input capacitance of the voltage-controlled semiconductor device, and turning off the voltage-controlled semiconductor device Sometimes, first, the second semiconductor switch and the third semiconductor switch are turned on, and the reactor and the voltage-controlled semiconductor element are turned on. The fourth semiconductor switch is turned on when the resonance current flowing through the reactor becomes maximum based on the input capacitance of the first semiconductor switch, and after a predetermined period has elapsed, the second semiconductor switch is turned off and the first semiconductor switch is turned on. A gate drive circuit, characterized by:
ゲート駆動回路において、 前記第１，第３，第４半導体スイッチそれぞれは自己消
弧形半導体素子とダイオードの逆並列回路からなり、 前記第２半導体スイッチは省略し、 前記電圧制御形半導体素子をターンオフさせるときに
は、先ず第１半導体スイッチと第４半導体スイッチとを
所定の期間オンした後、第４半導体スイッチをオフ，第
３半導体スイッチをオンにし、前記リアクトルと該電圧
制御形半導体素子の入力容量とに基づき該リアクトルに
流れる共振電流が零になった時点で第３半導体スイッチ
をオフにし、 前記電圧制御形半導体素子をターンオフさせるときに
は、先ず第１半導体スイッチと第３半導体スイッチとを
オンにし、該電圧制御形半導体素子のゲート端子とソー
スまたはエミッタ端子間の電圧が所定の値となった時点
で第４半導体スイッチをオンにし、所定の期間が経過し
た後、第１半導体スイッチをオンにすること特徴とする
ゲート駆動回路。8. The gate drive circuit according to claim 1, wherein each of said first, third and fourth semiconductor switches comprises an anti-parallel circuit of a self-extinguishing semiconductor element and a diode. The second semiconductor switch is omitted, and when the voltage-controlled semiconductor device is turned off, first the first semiconductor switch and the fourth semiconductor switch are turned on for a predetermined period, then the fourth semiconductor switch is turned off, and the third semiconductor switch is turned off. Turning on the switch, turning off the third semiconductor switch when the resonance current flowing through the reactor becomes zero based on the reactor and the input capacitance of the voltage-controlled semiconductor device, and turning off the voltage-controlled semiconductor device Sometimes, first, the first semiconductor switch and the third semiconductor switch are turned on, and the gate terminal and the source of the voltage-controlled semiconductor device are turned on. Alternatively, the gate drive circuit turns on the fourth semiconductor switch when the voltage between the emitter terminals reaches a predetermined value, and turns on the first semiconductor switch after a predetermined period has elapsed.
ゲート駆動回路において、 前記第１，第３，第４半導体スイッチそれぞれは自己消
弧形半導体素子とダイオードの逆並列回路からなり、 前記第２半導体スイッチはダイオードからなり、 前記電圧制御形半導体素子をターンオフさせるときに
は、先ず第１半導体スイッチと第４半導体スイッチとを
所定の期間オンした後、第４半導体スイッチをオフ，第
３半導体スイッチをオンにし、前記リアクトルと該電圧
制御形半導体素子の入力容量とに基づき該リアクトルに
流れる共振電流が零になった時点で第３半導体スイッチ
をオフにし、 前記電圧制御形半導体素子をターンオフさせるときに
は、先ず第１半導体スイッチと第３半導体スイッチとを
オンにし、該電圧制御形半導体素子のゲート端子とソー
スまたはエミッタ端子間の電圧が所定の値となった時点
で第４半導体スイッチをオンにし、所定の期間が経過し
た後、第１半導体スイッチをオンにすること特徴とする
ゲート駆動回路。9. The gate drive circuit according to claim 1, wherein each of said first, third and fourth semiconductor switches comprises an anti-parallel circuit of a self-turn-off semiconductor element and a diode. The second semiconductor switch is composed of a diode. When turning off the voltage-controlled semiconductor device, first, the first semiconductor switch and the fourth semiconductor switch are turned on for a predetermined period, and then the fourth semiconductor switch is turned off. Turning on the semiconductor switch, turning off the third semiconductor switch when the resonance current flowing through the reactor becomes zero based on the reactor and the input capacitance of the voltage-controlled semiconductor device, and turning off the voltage-controlled semiconductor device First, the first semiconductor switch and the third semiconductor switch are turned on, and the gate of the voltage-controlled semiconductor device is turned on. A gate drive circuit comprising: turning on a fourth semiconductor switch when a voltage between a terminal and a source or emitter terminal reaches a predetermined value; and turning on the first semiconductor switch after a predetermined period has elapsed.
ずれかに記載のゲート駆動回路において、 前記電圧制御形半導体素子がターンオフを完了し、再度
ターンオンする迄の期間は、第１半導体スイッチをオフ
にし、第３，第４半導体スイッチをオンにすることを特
徴とするゲート駆動回路。10. The gate drive circuit according to claim 5, wherein the voltage-controlled semiconductor device completes turn-off, and turns on the first semiconductor during a period until it is turned on again. A gate drive circuit, wherein the switch is turned off and the third and fourth semiconductor switches are turned on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14400097A JPH10337000A (en) | 1997-06-02 | 1997-06-02 | Gate drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14400097A JPH10337000A (en) | 1997-06-02 | 1997-06-02 | Gate drive circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10337000A true JPH10337000A (en) | 1998-12-18 |
Family
ID=15351992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14400097A Pending JPH10337000A (en) | 1997-06-02 | 1997-06-02 | Gate drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10337000A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006230166A (en) * | 2005-02-21 | 2006-08-31 | Denso Corp | Gate drive circuit |
| KR100977912B1 (en) | 2001-10-01 | 2010-08-24 | 에스티 에릭슨 에스에이 | Gate driver apparatus having an energy recovering circuit |
| JP2014075694A (en) * | 2012-10-04 | 2014-04-24 | Renesas Electronics Corp | Gate driver and switching method |
| WO2016132630A1 (en) * | 2015-02-16 | 2016-08-25 | アイシン・エィ・ダブリュ株式会社 | Switching element driving circuit |
| CN106877635A (en) * | 2017-03-07 | 2017-06-20 | 浙江大学 | The low damage drive circuit of isolated form high frequency |
| WO2018203422A1 (en) * | 2017-05-01 | 2018-11-08 | 三菱電機株式会社 | Semiconductor element drive device and power conversion device |
-
1997
- 1997-06-02 JP JP14400097A patent/JPH10337000A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100977912B1 (en) | 2001-10-01 | 2010-08-24 | 에스티 에릭슨 에스에이 | Gate driver apparatus having an energy recovering circuit |
| JP2006230166A (en) * | 2005-02-21 | 2006-08-31 | Denso Corp | Gate drive circuit |
| JP4496988B2 (en) * | 2005-02-21 | 2010-07-07 | 株式会社デンソー | Gate drive circuit |
| JP2014075694A (en) * | 2012-10-04 | 2014-04-24 | Renesas Electronics Corp | Gate driver and switching method |
| WO2016132630A1 (en) * | 2015-02-16 | 2016-08-25 | アイシン・エィ・ダブリュ株式会社 | Switching element driving circuit |
| JPWO2016132630A1 (en) * | 2015-02-16 | 2017-08-31 | アイシン・エィ・ダブリュ株式会社 | Switching element drive circuit |
| US10298220B2 (en) | 2015-02-16 | 2019-05-21 | Aisin Aw Co., Ltd. | Switching element drive circuit |
| CN106877635A (en) * | 2017-03-07 | 2017-06-20 | 浙江大学 | The low damage drive circuit of isolated form high frequency |
| CN106877635B (en) * | 2017-03-07 | 2019-05-24 | 浙江大学 | The low damage driving circuit of isolated form high frequency |
| WO2018203422A1 (en) * | 2017-05-01 | 2018-11-08 | 三菱電機株式会社 | Semiconductor element drive device and power conversion device |
| JPWO2018203422A1 (en) * | 2017-05-01 | 2019-11-07 | 三菱電機株式会社 | Semiconductor device driving apparatus and power conversion apparatus |
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