JPH1056771A - Gate drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a gate drive circuit by which the conversion efficiency of an apparatus is enhanced by a method wherein a pulse generator which generates a command to turn on/off a semiconductor device is connected across the parallel connection point of base or gate terminals of a first transistor, a second transistor and a third transistor and the negative-pole-side terminal of a DC power supply. SOLUTION: A first transistor 21 is connected across the positive-pole-side terminal of a DC power supply 11 and the gate terminal of a MOSFET 1, and a second transistor 23 is connected across the positive-pole-side terminal of the DC power supply 11 and the cathode of a first diode 22. In addition, a third transistor 26 is connected across the other end of a reactor 25 and the negative-pole-side terminal of the DC power supply 11. Then, a pulse generator 14 which generates a command to turn on/off the MOSFET 1 is connected across the parallel connection point of base or gate terminals of the transistors 21, 23, 26 and the negative-pole-side terminal of the DC power supply 11. Thereby, the conversion efficiency of an apparatus which contains a gate drive circuit 20, the MOSFET 1 and the like can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOSFET,
The present invention relates to a gate drive circuit for turning on / off a voltage-driven semiconductor device such as an IGBT.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional example of this type of gate drive circuit.
FET and 10 are gate drive circuits. The gate drive circuit 10 includes a DC power supply 1 which is a gate power supply of the MOSFET 1.
1, a transistor 12, a transistor 13, and a pulse generator 14.

Here, the pulse generator 14 is a MOSFET
1 such as pulse width modulation (PW
M) It outputs a signal or the like. The operation of the gate drive circuit 10 will be described with reference to the operation waveform diagram shown in FIG.
This will be described below. 8, when the output of the pulse generator 14 switches from zero potential to a positive voltage (see FIG. 8A), the transistor 12 is turned on (see FIG. 8C).
In the period shown in FIG.
DC power source 1 via a transistor 12
1 is performed, and the MOSFET 1 is turned on (see FIG. 8B). In the period shown in FIG. 8A, the output of the pulse generator 14 keeps a positive voltage.
FET1 keeps on state.

Next, when the output of the pulse generator 14 switches from the positive voltage to the zero potential (see FIG. 8A), the transistor 12 is turned off and the transistor 13 is turned on (see FIG. 8D). In the period shown in FIG.
The electric charge stored in the capacitance between the gate and the source of the SFET 1 is discharged via the transistor 13 (see FIG. 8B), and when this electric charge becomes zero, the MOSFET 1 is turned off. In the period shown in FIG. 8A, the output of the pulse generator 14 keeps the zero potential, so that the MOSFET 1 keeps the off state.

[0005]

In the above conventional gate drive circuit, when the MOSFET 1 is turned on from off, M
The transistor 13 consumes the charge stored in the capacitance between the gate and the source of the OSFET 1. At this time, MOSF
Q is the accumulated charge between the gate and source of ET1, DC power supply 1
Assuming that the voltage of 1 is E and the repetition frequency of ON / OFF of the MOSFET 1 is f, the energy P consumed by the transistor 13 is expressed by the following equation (1).

[0006]

P∝ (1/2) × Q × E × f (1) That is, in equation (1), when the accumulated charge Q increases or the repetition frequency f increases, the energy consumed by the transistor 13 is increased. P becomes large, the conversion efficiency of the device including the gate drive circuit and the MOSFET decreases, and the transistor 13 requires a cooling structure such as a cooling fin, and the gate drive circuit becomes large. Was.

An object of the present invention is to improve the conversion efficiency of the device without increasing the size of the gate drive circuit.

[0008]

According to the first invention, a first transistor is connected between a positive terminal of a DC power supply and a gate terminal of a voltage-driven semiconductor device, and a first transistor is connected to a negative terminal of the DC power supply. A source or emitter terminal of the semiconductor device is connected, an anode of a first diode is connected to a gate terminal of the semiconductor device, and a second transistor is connected between a positive terminal of the DC power supply and a cathode of the first diode. A cathode of the second diode and one end of the reactor are connected to a connection point between the first diode and the second transistor, respectively, and a third transistor is connected between the other end of the reactor and a negative terminal of the DC power supply. And the anode of the second diode is connected to the negative terminal of the DC power supply, and the anode of the third diode is connected to the connection point between the reactor and the third transistor. A cathode of a third diode is connected to the positive terminal of the DC power supply, and a connection is made between the parallel connection point of the base or gate terminal of each of the first, second, and third transistors and the negative terminal of the DC power supply. And a pulse generator for generating a command to turn on and off the semiconductor device.

According to a second aspect of the present invention, the semiconductor device is turned on between the parallel connection point of the base or gate terminal of each of the first and second transistors in the first aspect of the invention and the negative terminal of the DC power supply. A pulse generator for generating an instruction to turn off is connected, and an off-delay timer is connected between the parallel connection point and the base or gate terminal of the third transistor.

The third invention is characterized in that the first power supply is connected between the positive terminal of the DC power supply and the gate terminal of the voltage-driven semiconductor device.
Connecting a transistor, connecting a source or emitter terminal of the semiconductor device to a negative terminal of the DC power supply,
A cathode of a first diode and one end of a reactor are connected to a gate terminal of the semiconductor device, respectively, and a second terminal is connected between the other end of the reactor and a negative terminal of the DC power supply.
A transistor is connected, an anode of a first diode is connected to a negative terminal of the DC power supply, an anode of a second diode is connected to a connection point between the reactor and the second transistor, and a positive terminal of the DC power supply is connected to a positive terminal of the DC power supply. A command for connecting the cathode of the second diode and for turning on / off the semiconductor device is generated between the parallel connection point of the base or gate terminal of each of the first and second transistors and the negative terminal of the DC power supply. A gate drive circuit to which a pulse generator is connected.

According to a fourth aspect, in the third aspect, the semiconductor device is turned on between the base or gate terminal of the first transistor and the negative terminal of the DC power supply.
A pulse generator for generating an instruction to turn off is connected, and a gate drive circuit is provided in which an off-delay timer is connected between a connection point between the first transistor and the pulse generator and a base or gate terminal of the second transistor. .

According to the present invention, the charge accumulated between the gate and the source when the voltage-driven semiconductor device is turned off can be regenerated to the DC power supply. According to the second and fourth aspects of the present invention, even when the period during which the voltage-driven semiconductor device is turned on is short, the accumulated charge between the gate and the source when the semiconductor device is turned off can be regenerated to the DC power supply. .

[0013]

FIG. 1 is a circuit diagram of a gate drive circuit according to a first embodiment of the present invention, which corresponds to claim 1 of the present invention and corresponds to the conventional gate drive circuit shown in FIG. Those having the same functions as the circuits are denoted by the same reference numerals. That is, in FIG. 1, the gate drive circuit 20
1, a pulse generator 14, a transistor 21 as a first transistor, a diode 22 as a first diode, and a transistor 23 as a second transistor
, A diode 24 as a second diode, a reactor 25, and a transistor 2 as a third transistor
6, a diode 27 as a third diode, and a resistor 28.

The operation of the gate drive circuit 20 will be described below with reference to the operation waveform diagram shown in FIG. In FIG. 2, first, when the output of the pulse generator 14 switches from zero potential to a positive voltage (see FIG. 2A), the transistor 21 is turned on (see FIG. 2C), and at the same time, the transistors 23 and 26 are turned on. Also turns on.

In the period shown in FIG.
The capacitance between the gate and source of T1 is charged by the DC power supply 11 via the transistor 21 (see FIG. 2B), and the MOSFET 1 is turned on. In the period shown in FIG. 2A, the output of the pulse generator 14 keeps the positive voltage, so that the MOSFET 1 keeps on.

In the period shown in FIG.
Since the transistors 23 and 26 are on, a current flows through the path of the DC power supply 11 → the transistor 23 → the reactor 25 → the transistor 26, and energy is stored in the reactor 25 as shown in FIG. Next, when the output of the pulse generator 14 switches from the positive voltage to the zero potential (FIG. 2).
(See (a)), the transistor 21 is turned off, and the transistors 23 and 26 are also turned off.

In the period shown in FIG. 2A, the diode 27 side of the reactor 25 has a positive high potential, and the energy stored in the reactor 25 and the gate of the MOSFET 1
The charge stored in the capacitance between the sources is
→ Diode 27 → DC power supply 11 → Source terminal of MOSFET 1 → Gate terminal of MOSFET 1 → Diode 2
The power is regenerated by the DC power supply 11 through the path 2 (see FIG. 2E), and when the charge becomes zero, the MOSFET 1 is turned off (see FIG. 2B).

In the period shown in FIG. 2A, since the output of the pulse generator 14 keeps zero potential, the MOSFE
When T1 continues to be in the OFF state and there is energy remaining in the reactor 25, the power is regenerated to the DC power supply 11 through a path of the reactor 25 → the diode 27 → the DC power supply 11 → the diode 24 (FIG. 2 (D), (D)). E)). FIG.
FIG. 5 is a circuit diagram of a gate drive circuit showing a second embodiment of the present invention. Corresponding to claim 2 of the present invention, those having the same functions as those of the first embodiment shown in FIG. The same reference numerals are given.

That is, the gate drive circuit 30 differs from the gate drive circuit 20 shown in FIG. 1 in that an off-delay timer 31 is inserted between the output of the pulse generator 14 and the base or gate terminal of the transistor 26. It is. The off-delay timer 31 includes the pulse generator 14
Is switched from zero potential to positive potential, and at the same time, the output of the off-delay timer 31 is switched from zero potential to positive potential. Also has the function of maintaining the positive potential.

Further, when the output of the pulse generator 14 switches from the positive potential to the zero potential, the off-delay timer 31 switches the output from the positive potential to the zero potential after continuing the positive potential for a predetermined period. On the other hand, during the remaining zero potential period of the output of the pulse generator 14, the output of the off-delay timer 31 has the function of becoming zero potential. The operation of the gate drive circuit 30 will be described below with reference to the operation waveform diagram shown in FIG.

In FIG. 4, the gate drive circuit 30 operates as shown in FIG. 4A in a section after the output of the pulse generator 14 switches from zero potential to positive voltage, as shown in FIG. The same operation as in the section of the operation waveform of the drive circuit 20 is performed. Next, when the output of the pulse generator 14 switches from the positive voltage to the zero potential (see FIG. 4A), the transistors 21 and 23 are turned off and the transistor 2 is turned off.
6 is an off-delay timer 31 as shown in FIG.
Keeps on by the output of.

In the period shown in FIG.
The charge stored in the gate-source capacitance of T1 is M
Discharge occurs in the path of the gate terminal of the OSFET1, the diode 22, the reactor 25, the transistor 26, and the source terminal of the MOSFET 1. When the charge becomes zero, the MOSFET is discharged.
1 is turned off (see FIG. 4 (c)), and the energy due to this discharge current is stored in the reactor 25 (FIG. 4 (e)).
reference).

In the section shown in FIG. 4A, the transistor 26 operates as shown in FIG.
Since the output of 1 keeps on, the reactor 2
With the energy stored in 5, the current continues to flow through the reactor 25 → the transistor 26 → the diode 24 (see FIGS. 4 (e) and 4 (f)). Further, during the period shown in FIG. 4A, the output of the pulse generator 14 keeps the zero potential, so that the MOSFET 1 continues to be in the off state, and the energy stored in the reactor 25 is changed from the reactor 25 to the diode 27 to the direct current. The power is regenerated to the DC power supply 11 through the path from the power supply 11 to the diode 24 (see FIGS. 4E and 4F).

As described above, the provision of the off-delay timer 31 makes it possible to turn off the MOSFET 1 even if the duration of the ON command in the case of the pulse generator 14 that generates a command subjected to pulse width modulation (PWM) is shortened. The accumulated charge between the gate and the source of the MOSFET 1 at the time can be regenerated to the DC power supply 1. FIG. 5 is a circuit diagram showing a gate drive circuit according to a third embodiment of the present invention.
Corresponding to claim 4 of the present invention, components having the same functions as those of the conventional gate drive circuit shown in FIG.

That is, in FIG. 5, the gate drive circuit 4
0 denotes a DC power supply 11, a pulse generator 14, a transistor 41 as a first transistor, a diode 42 as a first diode, a reactor 43, a transistor 44 as a second transistor, and a diode as a second diode. 45 and a resistor 46.

The operation of the gate drive circuit 40 will be described below. While the output of the pulse generator 14 is a positive voltage, the transistors 41 and 44 are turned on, the capacitance between the gate and the source terminal of the MOSFET 1 is charged to the voltage of the DC power supply 11 via the transistor 41, and the MOSFET 1 is turned on. At the same time, when the transistor 44 is turned on, the DC power supply 1
A current flows through the path of 1 → transistor 41 → reactor 43 → transistor 44, and energy is stored in reactor 44.

During the period when the output of the pulse generator 14 is at zero voltage, the transistors 41 and 44 are turned off and the reactor 4 is turned off.
3 stored energy and the gate of MOSFET 1-
The accumulated charge of the capacitance between the source terminals is transferred to the DC power source 1 via the route of the reactor 43 → the diode 45 → the DC power source 11 → the source terminal of the MOSFET 1 → the gate terminal of the MOSFET 1.
Regenerate to 1. Further, when the accumulated charge of the capacitance between the gate and the source terminal of the MOSFET 1 is discharged through the above-mentioned path and becomes zero, the MOSFET 1 is turned off.

Thereafter, if there is energy remaining in the reactor 43, the reactor 43 → the diode 4
A current flows through the path of 5 → DC power supply 11 → diode 42 to regenerate to DC power supply 11. FIG. 6 shows a fourth embodiment of the present invention.
FIG. 10 is a circuit configuration diagram of a gate drive circuit showing an embodiment of the present invention. Corresponding to claim 4 of the present invention, components having the same functions as those of the third embodiment shown in FIG. .

That is, the gate drive circuit 50 differs from the gate drive circuit 40 shown in FIG. 5 in that an off-delay timer 51 is inserted between the output of the pulse generator 14 and the base or gate terminal of the transistor 44. It is. The off-delay timer 51 has the same function as the off-delay timer 31 of the second embodiment.

The operation of the gate drive circuit 50 will be described below. While the output of the pulse generator 14 is a positive voltage, the transistors 41 and 44 are turned on, the capacitance between the gate and source terminals of the MOSFET 1 is charged to the voltage of the DC power supply 11 via the transistor 41, and the MOSFET 1 is turned on. At the same time, when the transistor 44 is turned on, the DC power supply 1
A current flows through the path of 1 → transistor 41 → reactor 43 → transistor 44, and energy is stored in reactor 44.

During the period when the output of the pulse generator 14 is zero voltage, the transistor 41 is turned off and the transistor 44 is turned off.
Is ON, the accumulated charge of MOSFET 1 is
The charge is stored in the reactor 43 through the route of the gate terminal of the ETT1, the reactor 43, the transistor 44, and the gate terminal of the MOSFET T1, and the accumulated charge is reduced to zero.
Turns off. Due to the energy stored at this time, a current continues to flow in a path from the reactor 43 → the transistor 44 → the diode 42.

Next, when the output of the pulse generator 14 is in a zero voltage period and the transistors 41 and 44 are both turned off, the energy of the reactor 43 causes the reactor 43 → the diode 45 → the DC power supply 11 → the diode 4
The current flows through the path 2 and is regenerated to the DC power supply 11. As described above, by providing the off-delay timer 51,
For example, even if the duration of the ON command in the case of the pulse generator 14 that generates a command subjected to pulse width modulation (PWM) is shortened, the MOSFET 1 is turned off when the MOSFET 1 is turned off.
The charge stored between the gate and the source can be regenerated to the DC power supply 11.

[0033]

According to the present invention, the charge stored between the gate and the source when the voltage-driven semiconductor device is turned off is regenerated to the DC power supply, so that the loss in the gate drive circuit is reduced and the drive circuit is small. Since the conversion efficiency of the device including the gate drive circuit and the IGBT is improved, it is most suitable for use in a portable device or the like that requires several types of DC voltages from one small storage battery.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a gate drive circuit according to a first embodiment of the present invention;

FIG. 2 is a waveform chart illustrating the operation of FIG.

FIG. 3 is a circuit diagram showing a gate drive circuit according to a second embodiment of the present invention;

FIG. 4 is a waveform chart for explaining the operation of FIG. 3;

FIG. 5 is a circuit diagram showing a gate drive circuit according to a third embodiment of the present invention;

FIG. 6 is a circuit diagram showing a gate drive circuit according to a fourth embodiment of the present invention;

FIG. 7 is a circuit configuration diagram of a gate drive circuit showing a conventional example.

FIG. 8 is a waveform chart for explaining the operation of FIG. 7;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... MOSFET, 10 ... gate drive circuit, 11 ... DC power supply, 12, 13 ... transistor, 14 ... pulse generator, 20 ... gate drive circuit, 21 ... transistor, 22
... Diode, 23 ... Transistor, 24 ... Diode, 25 ... Reactor, 26 ... Transistor, 27 ... Diode, 28 ... Resistance, 30 ... Gate drive circuit, 31 ...
Off-delay timer, 40 gate drive circuit, 41 transistor, 42 diode, 43 reactor
4 transistor, 45 diode, 46 resistor, 5
0: gate drive circuit, 51: off-delay timer.

Claims (4)

[Claims] A first transistor is connected between a positive terminal of a DC power supply and a gate terminal of a voltage-driven semiconductor device, and a source or emitter terminal of the semiconductor device is connected to a negative terminal of the DC power supply. An anode of a first diode is connected to a gate terminal of the semiconductor device; a second transistor is connected between a positive terminal of the DC power supply and a cathode of the first diode; At the connection point, the second
A cathode of the diode is connected to one end of the reactor, a third transistor is connected between the other end of the reactor and a negative terminal of the DC power supply, and an anode of a second diode is connected to the negative terminal of the DC power supply. The anode of a third diode is connected to a connection point between the reactor and the third transistor; the cathode of a third diode is connected to the positive terminal of the DC power supply; A gate drive circuit, comprising: a pulse generator for generating a command to turn on / off the semiconductor device between a parallel connection point of a base or a gate terminal of each transistor and a negative terminal of the DC power supply. 2. A first transistor is connected between a positive terminal of a DC power supply and a gate terminal of a voltage-driven semiconductor device, and a source or emitter terminal of the semiconductor device is connected to a negative terminal of the DC power supply. An anode of a first diode is connected to a gate terminal of the semiconductor device; a second transistor is connected between a positive terminal of the DC power supply and a cathode of the first diode; At the connection point, the second
A cathode of the diode is connected to one end of the reactor, a third transistor is connected between the other end of the reactor and a negative terminal of the DC power supply, and an anode of a second diode is connected to the negative terminal of the DC power supply. The anode of the third diode is connected to the connection point between the reactor and the third transistor, the cathode of the third diode is connected to the positive terminal of the DC power supply, and the first and second transistors are respectively connected. A pulse generator for generating a command to turn on / off the semiconductor device is connected between a parallel connection point of a base or a gate terminal and a negative terminal of the DC power supply; and the parallel connection point and a base of the third transistor. Alternatively, an off-delay timer is connected between the gate drive circuit and the gate terminal. 3. A first transistor is connected between a positive terminal of the DC power supply and a gate terminal of the voltage-driven semiconductor device, and a source or emitter terminal of the semiconductor device is connected to a negative terminal of the DC power supply. Connecting a cathode of a first diode and one end of a reactor to a gate terminal of the semiconductor device; connecting a second transistor between the other end of the reactor and a negative terminal of the DC power supply; The anode of the first diode is connected to the negative terminal of the power supply, the anode of the second diode is connected to the connection point between the reactor and the second transistor, and the cathode of the second diode is connected to the positive terminal of the DC power supply And connecting the semiconductor device between a parallel connection point of a base or a gate terminal of each of the first and second transistors and a negative terminal of the DC power supply. A gate drive circuit to which a pulse generator for generating an ON / OFF command is connected. 4. A first transistor is connected between a positive terminal of the DC power supply and a gate terminal of the voltage-driven semiconductor device, and a source or emitter terminal of the semiconductor device is connected to a negative terminal of the DC power supply. Connecting a cathode of a first diode and one end of a reactor to a gate terminal of the semiconductor device; connecting a second transistor between the other end of the reactor and a negative terminal of the DC power supply; The anode of the first diode is connected to the negative terminal of the power supply, the anode of the second diode is connected to the connection point between the reactor and the second transistor, and the cathode of the second diode is connected to the positive terminal of the DC power supply And generating a command to turn on / off the semiconductor device between the base or gate terminal of the first transistor and the negative terminal of the DC power supply. A pulse generator, and a connection point between the first transistor and the pulse generator and a second pulse generator.
An off-delay timer is connected between a base and a gate terminal of a transistor.