WO2018203422A1

WO2018203422A1 - Semiconductor element drive device and power conversion device

Info

Publication number: WO2018203422A1
Application number: PCT/JP2017/037323
Authority: WO
Inventors: 航平恩田; 亮太近藤; 陽平丹; 岩蕗　寛康
Original assignee: 三菱電機株式会社
Priority date: 2017-05-01
Filing date: 2017-10-16
Publication date: 2018-11-08
Also published as: JP6758486B2; JPWO2018203422A1

Abstract

This semiconductor element drive device, by means of a power recovery function, reduces energy necessary for driving a gate, and prevents generation of a large current associated with arm short-circuiting, etc. A control circuit (150) executes short-circuiting protection control when generation of a short-circuit path associated with turning-on of a semiconductor element (10) is detected by a short-circuiting detection unit (160) during an on-period of a switching element (SW1) for turning the semiconductor element (10) on. In the short-circuiting protection control, periods for turning a switching element (SW4) on and for turning the switching element (SW1) off for cutting off the gate of the semiconductor element (10) and a DC power source (110), are provided. By turning the switching element (SW4) on, a current path through which the current flowing through a reactor (Lr) bypasses the gate, and a second path for discharging the gate, are formed.

Description

Semiconductor device driving apparatus and power conversion apparatus

The present invention relates to a semiconductor device drive device and a power conversion device, and more particularly to a drive device having a power regeneration function and a power conversion device including the drive device.

Power converters such as inverters achieve power conversion by turning on and off power semiconductor elements. Typical examples of power semiconductor elements include voltage-driven semiconductor elements represented by MOS-FETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors). In order to control on / off of these semiconductor elements, a driving device for controlling the gate voltage in accordance with the on / off control signal is provided.

In recent years, with the aim of increasing the power density of power conversion devices, there is a tendency to increase the frequency of switching semiconductor elements in order to reduce the size of capacitors and inductors. As the frequency increases, the number of times (per unit time) that the driving device charges and discharges the gate of the semiconductor element increases, so that power consumption increases. In connection with this, when the power supply capacity of the drive device is increased, there is a concern that it may hinder downsizing of the device.

For this reason, a power regeneration type drive device has been proposed to suppress an increase in power source capacity, that is, an increase in the size of the device by regenerating energy stored in the gate to the power source when the semiconductor element is turned off. Yes. For example, in Japanese Patent Application Laid-Open No. 5-207773 (Patent Document 1), the energy stored in the gate parasitic capacitance of a semiconductor element is calculated using a driving device including a half-bridge type inverter circuit and wiring inductance. A control for regenerating to a DC power source via a wiring inductance is described.

Further, it is general that a driving device for a semiconductor element has a short-circuit protection function. For example, when the semiconductor element to be driven constitutes one of the upper and lower arms with an inverter or the like, when an arm short circuit occurs due to erroneous conduction of the opposing element of the same arm, the short circuit is detected, and the semiconductor element is This is a function to shut off (off) for protection.

Japanese Patent Laid-Open No. 2014-11701 (Patent Document 2) discloses, as an example of a short circuit protection function, when detecting a short circuit, in order to avoid element destruction due to an off surge voltage due to a large current interruption, a gate resistance value is higher than that during normal turn-off. It is described that the semiconductor element is softly cut off by increasing the value of.

JP-A-5-207731 JP 2014-11701 A

In the power regeneration type driving device described in Patent Document 1, a current for gate charging is supplied via an inductance when the semiconductor element is turned on. Therefore, when a short circuit as in Patent Document 2 is detected during turn-on, charging of the gate is continued by forming a reactor current return path even if the power source of the driving device and the gate are shut off. There is concern. In this case, the semiconductor element cannot be shut off, and a large short-circuit current may flow through the semiconductor element.

Furthermore, in the power regeneration type driving device of Patent Document 1, as described in Patent Document 2, even if the gate resistance value is increased at the time of short circuit detection, the phenomenon that the gate charging is continued by the reactor current is solved. I can't.

The present invention has been made to solve such problems, and an object of the present invention is to reduce energy required for gate driving by a power regeneration function in a semiconductor device driving apparatus, and to short-circuit an arm or the like. This is to prevent the generation of a large current accompanying the.

In one aspect of the present disclosure, a semiconductor element driving apparatus is a semiconductor element driving apparatus in which conduction between a first main electrode and a second main electrode is interrupted according to a voltage of a control electrode. 2 power supply nodes, a plurality of switching elements, a reactor, a control circuit, and a short-circuit detection unit. The first power supply node supplies a first potential for charging the control electrode. The second power supply node supplies a second potential that is lower than the first potential. The plurality of switching elements are connected between the first and second power supply nodes and the control electrode to control charging and discharging of the control electrode. The reactor is disposed between the first node and the second node, and the second node is electrically connected to the control electrode. The control circuit controls on / off of the plurality of switching elements according to the on / off command signal of the semiconductor element. The short circuit detection unit detects the occurrence of a short circuit path including the semiconductor element when the semiconductor element is turned on. Each of the plurality of switching elements includes a diode for forming a reflux path when OFF. When the occurrence of a short circuit path is detected by the short circuit detection unit during a period in which the control electrode is electrically connected to the first power supply node according to the on / off command signal, the control circuit sets the control electrode to the first power supply node. In order to turn off the connected switching elements and to provide a period in which a first path through which the current flowing through the reactor flows avoiding the control electrode and a second path for discharging the charge of the control electrode are formed, Controls a plurality of switching elements. The first path is formed including a diode of an off-state switching element among the plurality of switching elements, and the second path is formed including an on-state switching element among the plurality of switching elements. .

According to the present invention, in a semiconductor device driving apparatus, energy required for gate driving can be reduced by the power regeneration function, and generation of a large current due to an arm short circuit or the like can be prevented.

FIG. 3 is a circuit diagram illustrating a configuration of a semiconductor element driving device according to the first embodiment. FIG. 2 is an operation waveform diagram for explaining on / off control of a semiconductor element by the control circuit shown in FIG. 1. FIG. 7 is a circuit diagram for illustrating a current path in a normal turn-on operation of the drive device according to the first embodiment. FIG. 7 is a circuit diagram for illustrating a current path in a normal turn-off operation of the drive device according to the first embodiment. FIG. 7 is a circuit diagram for illustrating a current path during short-circuit protection control of the drive device according to the first embodiment. FIG. 10 is a circuit diagram illustrating a configuration of a semiconductor element drive device according to a first modification of the first embodiment. FIG. 11 is a circuit diagram illustrating a configuration of a semiconductor element drive device according to a second modification of the first embodiment. FIG. 6 is a circuit diagram illustrating a configuration of a semiconductor element drive device according to a second embodiment. FIG. 10 is an operation waveform diagram of the semiconductor element drive device according to the second embodiment. FIG. 11 is a circuit diagram for illustrating a current path during short-circuit protection control of the driving device according to the second embodiment. FIG. 11 is a block diagram illustrating a first example of a short circuit detection unit according to the third embodiment. FIG. 12 is a block diagram illustrating a second example of a short circuit detection unit according to the third embodiment. FIG. 11 is a block diagram illustrating a third example of a short circuit detection unit according to the third embodiment. It is a block diagram explaining the 4th example of the short circuit detection part according to Embodiment 3. FIG. FIG. 10 is a circuit diagram showing a configuration of a power conversion device according to a first example of a fourth embodiment. FIG. 11 is a circuit diagram showing a configuration of a power conversion device according to a second example of the fourth embodiment. FIG. 11 is a circuit diagram illustrating a configuration of a semiconductor element drive device according to a third modification of the first embodiment. FIG. 11 is a circuit diagram illustrating a configuration of a semiconductor element driving device according to a combination of the second embodiment and the third modification of the first embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated in principle.

Embodiment 1 FIG.
FIG. 1 is a circuit diagram illustrating a configuration of a driving apparatus 100 for a semiconductor device according to the first embodiment.

Referring to FIG. 1, semiconductor element 10 that is turned on / off by drive device 100 according to the first embodiment includes gate (G) that is a control electrode, drain (D) and source (S) that are main electrodes, and a gate. It has a terminal 11 and a control source terminal 12. The semiconductor element 10 is a voltage-driven element in which the amount of current between the main electrodes (between the drain D and the source S) is controlled according to the voltage between the gate and the source. In the present embodiment, the semiconductor element 10 is turned on when the gate-source voltage (hereinafter also simply referred to as “gate voltage”) Vgs is higher than the gate-on threshold voltage Vth, and turned off otherwise.

The driving apparatus 100 turns on and off the semiconductor element 10 according to the on / off command signal Sin by controlling the gate voltage of the semiconductor element 10. Specifically, the driving device 100 includes a DC power supply 110 that outputs a DC voltage Vgp, and turns on the semiconductor element 10 by making the gate voltage Vgs equal to the DC voltage Vgp. On the other hand, the driving device 100 turns off the semiconductor element 10 by setting the gate (G) to the same potential as the source (S), that is, by setting the gate voltage Vgs = 0.

The driving device 100 includes

power supply nodes

111 and 112, switching elements SW1 to SW4 constituting a full bridge circuit, a reactor Lr, a control circuit 150, and a short circuit detection unit 160 in addition to the DC power supply 110.

The power supply node 111 is electrically connected to the positive terminal of the DC power supply 110, and the power supply node 112 is electrically connected to the negative terminal of the DC power supply 110. A voltage Vgp is output from DC power supply 110 between

power supply nodes

112 and 111. The power supply node 112 is connected to the control source terminal 12 of the semiconductor element 10 and has the same potential as the source (S) of the semiconductor element 10. The power supply node 111 corresponds to a “first power supply node”, and the power supply node 112 corresponds to a “second power supply node”.

The switching elements SW1 to SW4 are configured to be turned on / off according to control signals GSW1 to GSW4 from the control circuit 150 and to have a reflux diode for securing a reflux path when turned off.

For example, the switching elements SW1 to SW4 can be constituted by transistors Q1 to Q4 such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and diodes D1 to D4 for reflux. In this case, the diodes D1 to D4 can be configured by MOSFET parasitic diodes (body diodes). As the transistors Q1 to Q4, either voltage-driven or current-driven elements can be used, and other transistors such as bipolar transistors can be used. The diodes D1 to D4 may be configured by connecting diode elements in antiparallel to the transistors Q1 to Q4.

Hereinafter, in the switching elements SW1 to SW4, the transistors Q1 to Q4 will be described as n-type transistors. That is, in each of the switching elements SW1 to SW4, the transistors Q1 to Q4 conduct when the control signals GSW1 to GSW4 are at a logic high level (hereinafter also simply referred to as “H level”), while the control signals GSW1 to GSW4 Transistors Q1-Q4 are cut off at a logic low level (hereinafter also simply referred to as "L level").

Thus, the switching elements SW1 to SW4 are turned on according to the conduction of the transistors Q1 to Q4 when the control signals GSW1 to GSW4 from the control circuit 150 are at the H level, while the control signals GSW1 to GSW4 are L Turned off when level. However, the switching elements SW1 to SW4 can form a current path in the regeneration direction to the DC power supply 110 by the diodes D1 to D4 even when the switching elements SW1 to SW4 are off.

It should be noted that in some or all of the switching elements SW1 to SW4, the transistors can be configured by P-type transistors. In this case, the level (H / L) may be inverted for some or all of the control signals GSW1 to GSW4 input to the P-type transistor with respect to the embodiment described below.

Switching element SW1 is electrically connected between power supply node 111 and node N1. Diode D1 is arranged with the direction from node N1 to power supply node 111 as the forward direction. Switching element SW3 is electrically connected between power supply node 111 and node N2. Diode D3 is arranged with the direction from node N2 to power supply node 111 as the forward direction.

Reactor Lr is arranged between nodes N1 and N2. Reactor Lr may connect a reactor element between nodes N1 and N2, and can also be constituted by a parasitic reactor. Node N2 is electrically connected to gate terminal 11 of semiconductor element 10. Hereinafter, the polarity of the reactor current ILr passing through the reactor Lr is defined as ILr> 0 when flowing from the node N1 to N2, and on the contrary, ILr <0 when flowing from the node N2 to N1.

Switching element SW2 is electrically connected between node N1 and power supply node 112. Diode D2 is arranged with the direction from power supply node 112 to node N1 as the forward direction. Switching element SW4 is electrically connected between node N2 and power supply node 112. Diode D4 is arranged with the direction from power supply node 112 to node N2 as the forward direction.

The short circuit detection unit 160 detects the occurrence of a short circuit path including the semiconductor element 10 in the circuit to which the semiconductor element 10 is connected when the semiconductor element 10 is turned on. That is, when the semiconductor element 10 itself has not failed, but there is a possibility that an excessive short-circuit current may pass through the semiconductor element 10 when the semiconductor element 10 is turned on, the short-circuit detection unit 160 may turn on the semiconductor element 10. The occurrence of a short circuit path is detected based on

For example, as described later in the fourth embodiment, when the semiconductor element 10 is applied to an inverter, a chopper, or the like to form an arm with another semiconductor element, if a short circuit failure occurs in the opposing element of the same arm, the semiconductor element 10 When the element 10 is turned on, a short circuit path for the power supply is formed. Alternatively, when the semiconductor element 10 is erroneously turned on due to noise or the like when the opposing element of the same arm is turned on, a power supply short-circuit path is formed in response to the semiconductor element 10 being turned on. When the current in the short-circuit path passes through the semiconductor element 10, there is a concern that the semiconductor element 10 will fail.

When the short-circuit detection unit 160 detects the occurrence of the short-circuit path as described above when the semiconductor element 10 is turned on (hereinafter, also simply referred to as “short-circuit detection”), the short-circuit detection signal Ssc is changed from the L level (default) to the H level. To be changed.

The short-circuit detection method as described above is known, and for example, the short-circuit detection unit 160 can detect a short-circuit based on the drain-source voltage (Vds) of the semiconductor element 10. Specifically, the short circuit detection unit 160 sets the short circuit detection signal Ssc to the H level when the drain-source voltage Vds is in a high state despite the semiconductor element 10 being in the on state.

The short-circuit detection unit 160 may be configured by an electronic circuit (hardware) that receives a drain-source voltage (Vds) as input, and a program process (based on an A / D conversion value of the drain-source voltage (Vds) ( Software). Alternatively, the function of the short-circuit detection unit 160 can be realized by a combination of hardware and software.

The control circuit 150 generates control signals GSW1 to GSW4 for the switching elements SW1 to SW4 in order to turn on and off the semiconductor element 10 in accordance with the on / off command signal Sin. Furthermore, the control circuit 150 executes short-circuit protection control (described later) for avoiding a failure of the semiconductor element 10 when detecting a short circuit in which the short circuit detection signal Ssc is set to H level.

In the configuration example of FIG. 1, the control circuit 150 and the short-circuit detection unit 160 are described as separate elements for each function. However, both the control circuit 150 and the short-circuit detection unit 160 are configured by the same module using an integrated circuit or the like. A function may be realized.

FIG. 2 is an operation waveform diagram for explaining on / off control of the semiconductor element 10 by the control circuit 150.

Referring to FIG. 2, in the period t1, the on / off command signal Sin is at the L level, the gate voltage Vgs = 0 is controlled, and the semiconductor element 10 is in the off state. While the switching elements SW1 to SW3 are kept off, the switching element SW4 is turned on. Thereby, in the period t1, the gate of the semiconductor element 10 is clamped to the same potential as the power supply node 112 connected to the source (S).

During the period t2, the on / off command signal Sin is changed from L level to H level. In response to this, the turn-on operation is started, and the control signal GSW1 is set to the H level in order to turn on the switching element SW1. In the period t2, the switching elements SW2 and SW3 are turned off, while the switching elements SW1 and SW4 are turned on. Thereby, in the period t2, the current path 201 indicated by the dotted line in FIG. 3 is formed, and thus the reactor current ILr increases (ILr> 0).

When the reactor current ILr reaches a predetermined determination value (positive), the period t3 is started. In the period t3, the control signal GSW1 is maintained at the H level, while the control signal GSW4 is changed to the L level. As a result, the switching element SW1 is maintained in the on state, and the switching elements SW2 to SW4 are turned off.

Therefore, in the period t3, the gate G is charged via the reactor Lr by the output voltage Vgp of the DC power supply 110 through the current path 202 shown by the solid line in FIG. Thereby, reactor current ILr decreases while gate voltage Vgs gradually increases.

When the gate voltage Vgs reaches the gate-on threshold voltage Vth, the semiconductor element 10 is turned on. Thereafter, in the period t4, the control signal GSW1 is set to the L level while the control signal GSW3 is set to the H level. Thereby, the switching element SW3 is turned on, and the switching elements SW1, SW2, SW4 are turned off.

In the period t4, the gate (G) of the semiconductor element 10 is connected to the power supply node 111 by turning on the switching element SW3 (transistor Q3), whereby the gate voltage Vgs = Vgp is clamped. As described above, the semiconductor element 10 is turned on in the periods t2 and t3 and maintained in the on state in the period t4 as the on / off command signal Sin changes from the L level to the H level.

Further, at the start of the period t4, the reactor current ILr (ILr> 0) is regenerated to the DC power source 110 by the diodes D2 and D3 of the switching elements SW2 and SW3 in the off state, and the current indicated by the one-dot chain line in FIG. A path 203 can be formed.

In the turn-on operation illustrated in FIG. 2, the example in which the reactor Lr is excited in the period t2 and the gate is charged in the period t3 is shown. However, the turn-on operation is performed by increasing the gate current for gate charging. Can be speeded up. However, the provision of the period t2 is not essential, and the semiconductor element 10 can be turned on by an operation that makes a direct transition from the period t1 to t3.

Next, the turn-off operation will be described. When the on / off command signal Sin changes from the H level to the L level, a turn-off period t5 is started.

In the period t5, the control signal GSW3 is maintained at the H level, and the control signal GSW2 is set at the H level. As a result, the switching elements SW2 and SW3 are turned on, and a current path 204 indicated by a dotted line in FIG. 4 is formed. Thereby, the reactor Lr is excited in the direction of ILr <0.

When the reactor current ILr reaches a predetermined determination value (negative), the period t6 is started. In the period t3, the control signal GSW2 is maintained at the H level, while the control signal GSW3 is changed to the L level. Thereby, the switching element SW2 is maintained in the on state, and the switching elements SW1, SW3, SW4 are turned off.

Therefore, in the period t6, the gate G is discharged via the reactor Lr by the current path 205 shown by the solid line in FIG. As a result, the absolute value of the reactor current (ILr <0) decreases while the gate voltage Vgs gradually decreases.

When the gate voltage Vgs is lower than the gate-on threshold voltage Vth, the semiconductor element 10 is turned off. Thereafter, in the period t7, the control signal GSW3 is set to the L level while the control signal GSW4 is set to the H level. As a result, the switching element SW4 is turned on and the switching elements SW1 to SW3 are turned off. As described above, the semiconductor element 10 is turned on in the periods t5 and t6 and maintained in the on state in the period t7 as the on / off command signal Sin changes from the H level to the L level.

Further, at the start of period t7, reactor current ILr (ILr <0) is regenerated to DC power supply 110 by diodes D1 and D4 of switching elements SW1 and SW4 in the off state, and the current path shown by the one-dot chain line in FIG. 206 can be formed.

Even in the turn-on operation, the turn-off can be speeded up by exciting the reactor Lr during the period t5 and then discharging the gate during the period t6. However, it is not essential to provide the period t5, and the semiconductor element 10 can be turned off by directly transitioning from the period t4 to t6.

As described above, the driving device 100 according to the first embodiment can reduce the energy consumption at the turn-on and turn-off by the power regeneration at the start of the periods t4 and t7. As a result, an increase in the power supply capacity of the DC power supply 110 can be suppressed even if the switching of the semiconductor element 10 is performed at a high frequency, so that an increase in size of the apparatus can be avoided.

Here, consider the operation in the case where a short circuit is detected by the short circuit detector 160 when the semiconductor element 10 is turned on again. For example, it is assumed that voltage breakdown has occurred in the opposing element that constitutes the same arm as the semiconductor element 10 during the period t7 in which the semiconductor element 10 is in the OFF state.

When the on / off command signal Sin changes from the L level to the H level, the period t8 is started. In the period t8, the reactor Lr is excited by turning on the switching elements SW1 and SW4 as in the period t2. Then, the period t9 is started in accordance with the increase in the reactor current ILr, and when the gate voltage Vgs reaches the gate-on threshold voltage Vth, the semiconductor element 10 is turned on to generate a short circuit path. At this time, in the power regeneration type driving apparatus 100 using the reactor Lr, the reactor Lr becomes a current source, and the charging current of the gate (G) of the semiconductor element 10 is continuously supplied. For this reason, when the gate voltage Vgs continues to rise, a short-circuit current exceeding the withstand current is generated, and there is a concern that a large current passing through the semiconductor element 10 may be generated.

In the driving device 100 according to the present embodiment, when the period t9 is started and the gate voltage Vgs rises, a large current flows without sufficiently decreasing the drain-source voltage. The short circuit is detected, and the short circuit detection signal Ssc is changed from the L level to the H level.

When the short circuit detection signal Ssc is set to H level, a period t10 for short circuit protection control is started.

In the period t10, the control circuit 150 changes the control signal GSW1 from the H level to the L level to turn off the switching element SW1 that connects the gate (G) to the DC power supply 110. Thereby, the gate (G) of the semiconductor element 10 is disconnected from the power supply node 111, that is, the positive terminal of the DC power supply 110 by the transistor Q <b> 1 turned off. Thereby, the current supply for gate charging from the DC power supply 110 is stopped.

However, even when the switching element SW1 is turned off, the reactor Lr acts as a current source, so that a current path 207 indicated by a dotted line in FIG. 5 is formed. Therefore, the control circuit 150 sets the control signal GSW4 to H level and provides a period for turning on the switching element SW4.

In the ON period of the switching element SW4,

current paths

208 and 209 indicated by solid lines in FIG. 5 are formed. That is, the current path 208 through which the reactor current ILr flows while avoiding the gate and the current path 209 that discharges the charge of the gate (G) can be formed. Thereby, the gate voltage Vgs can be reduced in the ON period of the switching element SW4. That is, the current path 208 corresponds to an example of “first path”, and the current path 209 corresponds to an example of “second path”.

By providing the ON period of the switching element SW4, it is possible to eliminate the phenomenon that the short-circuit current passing through the semiconductor element 10 increases due to the gate voltage Vgs continuing to rise due to the reactor current. On the other hand, if the gate voltage Vgs is drastically reduced in a state where a relatively large current flows through the semiconductor element 10 through the short circuit path, there is a concern that a large current passing through the semiconductor element 10 is generated due to the generation of the off-surge voltage. .

Therefore, as shown in FIG. 2, the control circuit 150 sets the control signal GSW4 in a pulse shape that periodically repeats the H level and the L level in order to intermittently turn on and off the switching element SW4.

In the H level period of the control signal GSW4, the switching element SW4 is turned on to form the

current paths

208 and 209 in FIG. 5, and the gate voltage Vgs is lowered. On the other hand, during the L level period of the control signal GSW4, the switching element SW4 is turned off to form the current path 207 in FIG. 5 and the gate (G) is charged, so that the gate voltage Vgs is gradually recovered.

Therefore, in the period t10, the gate voltage Vgs can be gradually lowered by intermittently turning on / off the switching element SW4. As a result, the short-circuit protection control in the period t10 suppresses the increase in the short-circuit current due to the increase in the gate voltage Vgs and prevents the generation of the off-surge voltage due to the rapid decrease in the gate voltage Vgs. Can be cut off softly.

In particular, the decrease rate of the gate voltage Vgs in the period t10 can be adjusted by the on-duty defined by the ratio of the H level period to the sum (one cycle) of the H level period and the L level period of the control signal GSW4.

For example, the average decrease rate of the gate voltage Vgs in the period t10 is smaller than the decrease rate of the gate voltage Vgs in the period t6 during normal time (when no short circuit is detected) (for example, about 1/10). The on-duty can be adjusted in advance.

When the gate voltage Vgs is lowered to a predetermined voltage by the short-circuit protection control in the period t10, the control signal GSW4 is maintained at the H level. As a result, the gate voltage Vgs = 0 is clamped, and the reactor current ILr is consumed by the heat generated by the parasitic resistance on the continuously formed current path 208 and disappears.

Thus, according to drive device 100 according to the first embodiment, the power regeneration type configuration having a reactor suppresses energy consumption in turn-on and turn-off operations, and the occurrence of a short-circuit path is detected during the turn-off operation. In some cases, the semiconductor element can be turned off by short circuit protection control without increasing the short circuit current by the action of the reactor.

Further, in the short-circuit protection control, the switching element SW4 is intermittently turned on / off, so that the semiconductor element 10 is softly cut off while gently decreasing the gate voltage, thereby suppressing the off-surge voltage.

Modification 1 of Embodiment 1
FIG. 6 is a circuit diagram showing a configuration of drive device 100a according to the first modification of the first embodiment.

6 is different from FIG. 1 in that drive device 100a according to the first modification of the first embodiment is different from drive device 100 (FIG. 1) in that

load resistors

181 and 182 are further provided. Load resistor 181 is connected in series with switching element SW3 between power supply node 111 and node N2. Similarly, load resistor 182 is connected in series with switching element SW4 between node N2 and power supply node 112. Since the configuration of other parts of drive device 100a is similar to that of drive device 100 (FIG. 1), detailed description will not be repeated.

In the driving device 100a, by arranging the load resistor 181, inrush current and voltage oscillation when the switching element SW3 is turned on can be suppressed during the period t4 when the semiconductor element 10 is turned on. Similarly, by arranging the load resistor 182, inrush current and voltage oscillation when the switching element SW4 is turned on can be suppressed during the period t7 when the semiconductor element 10 is turned off.

In the driving device 100a as well, the switching elements SW1 to SW4 are controlled to be turned on / off in the same manner as in FIG. Protection control (soft shut-off) can be realized.

Particularly, in the driving device 100a, the current of the switching element SW4 in the period t10 during the short circuit protection control is smaller than that of the driving device 100 in which the

load resistors

181 and 182 are not arranged. Therefore, in the driving device 100a, it is preferable to increase the on-duty of the switching element SW4 in the period t10 as compared with the driving device 100.

Modification 2 of Embodiment 1
FIG. 7 is a circuit diagram illustrating a configuration of drive device 100b according to the second modification of the first embodiment.

7, drive device 100b according to the second modification of the first embodiment is different from drive device 100 shown in FIG. 1 in that it has a plurality of

DC power sources

110 and 115.

DC power supplies

110 and 115 are connected between

power supply nodes

111 and 112 via power supply node 113. That is, the power supply node 113 corresponds to a “third power supply node”.

The power supply node 113 is connected to the control source terminal 12 of the semiconductor element 10. The DC power supply 115 outputs a DC voltage Vgm. Therefore, the power supply node 112 has a negative potential with respect to the source (S) of the semiconductor element 10. For this reason, when the semiconductor element 10 in which the switching element SW4 is turned on is turned off, the gate voltage Vgs can be set to a negative voltage.

Also in the driving device 100b according to the second modification of the first embodiment, the normal turn-on and turn-off of the semiconductor element 10 (when no short-circuit is detected), and the short-circuit protection control (soft cutoff) when the short-circuit is detected at the time of turn-on. This can be realized by generating control signals GSW1 to GSW4 in the same manner as shown in FIG.

Modification 3 of Embodiment 1
FIG. 17 is a circuit diagram illustrating a configuration of drive device 100c according to the third modification of the first embodiment.

Referring to FIG. 17, drive device 100 c according to the third modification of the first embodiment is different from drive device 100 shown in FIG. 1 in that instead of reactor Lr, on-reactor Lron and off-reactor Lroff, In addition, the ON diode DLon and the OFF diode DLoff are different.

The on-reactor Lron and the off-reactor Lroff are electrically connected in parallel between the nodes N1 and N2. On diode DLon is connected in series with on reactor Lron between nodes N1 and N2, with the direction from node N1 toward node N2 as the forward direction. The off-diode DLoff is connected in series with the off-reactor Loff between the nodes N1 and N2, with the direction from the node N2 toward the node N1 as the forward direction.

Therefore, when the semiconductor element 10 is turned on (periods t2 and t8 in FIG. 2), the reactor current ILron for charging the gate G flows through the series circuit of the on reactor Lron and the on diode DLon. On the other hand, when the semiconductor element 10 is turned off (period t5 in FIG. 2), the reactor current ILroff for discharging the gate G flows through the series circuit of the off reactor Lroff and the off diode DLoff.

17 is the same as that shown in FIG. Further, also in the driving device 100c according to the third modification of the first embodiment, the operation according to the short circuit detection signal Ssc from the short circuit detection unit 161, that is, the operation after the short circuit detection is the first embodiment described with reference to FIG. The detailed description will not be repeated.

Since drive apparatus 100c according to the third modification of the first embodiment can independently determine the inductance values of on-reactor Lron and off-reactor Lloff, the turn-on speed and the turn-off speed of semiconductor element 10 are independently adjusted. can do. As a result, in addition to the effect of drive device 100 according to the first embodiment, the period in which the semiconductor element 10 excites the reactor before starting the turn-on and turn-off operations, that is, one of periods t2, t8 and t5 in FIG. Alternatively, both lengths can be shortened without complicating the control.

Embodiment 2. FIG.
FIG. 8 is a circuit diagram illustrating a configuration of drive device 101 according to the second embodiment.

8 is compared with FIG. 1, driving device 101 according to the second embodiment has switching elements SW <b> 5 and SW <b> 6 and soft-blocking resistance elements as compared with driving device 100 according to the first embodiment (FIG. 1). 185 and 185. The control circuit 150 further generates control signals GSW5 and GSW6 for turning on and off the switching elements SW5 and SW6 in addition to the control signals GSW1 to GSW4.

The switching elements SW5 and SW6 are configured to have a free-wheeling diode for securing a free-wheeling path at the time of turning off, similarly to the switching elements SW1 to SW4. For example, switching elements SW5 and SW6 can be configured by transistors Q5 and Q6 similar to transistors Q1 to Q4 and diodes D5 and D6 similar to diodes D1 to D4. Hereinafter, as for the switching elements SW5 and SW6, as in the switching elements SW1 to SW4, the transistors Q5 and Q6 are described as n-type transistors.

For each of the switching elements SW5 and SW6, it is possible to configure the transistors as P-type transistors. In this case, the level (H / L) of the control signals GSW5 and / or GSW6 input to the P-type transistor may be inverted with respect to the control signals GSW5 and GSW6 described below.

The switching element SW5 is connected between the node N2 and the node N3 connected to the gate terminal 11. Diode D5 is arranged with the direction from node N3 to node N2 as the forward direction. Switching element SW6 is electrically connected between node N3 and power supply node 112. Diode D6 is arranged with the direction from power supply node 112 toward node N3 as the forward direction. Resistance element 185 is connected in series with switching element SW6 between node N3 and power supply node 112.

Since the configuration of other parts of drive device 101 is the same as that of drive device 100 (FIG. 1) according to the first embodiment, detailed description will not be repeated. In the driving device 101, “a plurality of switching elements” are configured by the switching elements SW1 to SW6.

FIG. 9 is an operation waveform diagram of drive device 101 according to the second embodiment.
Referring to FIG. 9, control circuit 150 sets control signal GSW5 to H level and normalizes control signal GSW6 to L level at the normal time (when short circuit is not detected) when short circuit detection signal Ssc is set to L level. Set to.

In the driving device 101, the switching element SW5 is turned on and the switching element SW6 is turned off, so that the connection relationship between the gate (G) of the semiconductor element 10 and the node N2 is the driving device 100 (FIG. 1). It will be the same.

Therefore, at the normal time (when no short circuit is detected), the control signals GSW1 to GSW4 are set in the same manner as in FIG. 2, so that the turn-on operation and the turn-off operation of the semiconductor element 10 can be performed as in the first embodiment. it can. That is, the operation of drive device 101 during periods t1 to t7 is the same as that of drive device 100, and thus detailed description will not be repeated.

On the other hand, the driving device 101 is different from the driving device 100 (FIG. 2) in the period t10 when a short circuit is detected at the time of turn-on.

When the short circuit detection signal Ssc changes to H level during the turn-on operation, the control circuit 150 sets the control signal GSW1 to L level in the period t10 as in FIG. Thereby, supply of the gate current from the DC power supply 110 is stopped.

Further, the control circuit 150 sets the control signal GSW6 to H level and sets the control signal GSW5 to L level. Thereby, switching elements SW5 and SW6 are turned on and off until the period t9.

FIG. 10 shows a current path during protection control (period t10) of drive device 101 according to the second embodiment.

Referring to FIG. 10, node N2 is disconnected from gate (G) when switching element SW5 is turned off. Reactor current ILr (ILr> 0) flows away from gate (G) by current path 211 including diodes D2 and D3 of switching elements SW2 and SW3. Thereby, the reactor current ILr is regenerated in the DC power supply 110 without charging the gate (G). The current path 211 corresponds to an example of a “first path”.

On the other hand, the gate (G) is connected to the power supply node 112 via the resistance element 185 by the switching element SW6 (transistor Q6) in the on state. Thereby, a current path 212 for discharging the charge of the gate (G) is formed. That is, the current path 212 corresponds to an example of a “second path”. As a result, when the short circuit occurs, the phenomenon that the short circuit current passing through the semiconductor element 10 increases due to the continued charging of the gate (G) by the reactor current ILr can be solved.

Furthermore, since the resistance element 185 is included in the current path 212, a rapid decrease in the gate voltage Vgs can be avoided. That is, it is possible to suppress an off-surge voltage when the semiconductor element 10 is turned off from a state in which a relatively large current flows through the semiconductor element 10 through the short-circuit path. Note that the discharge current through the current path 212, that is, the rate of decrease in the gate voltage can be adjusted by the electric resistance value of the resistance element 185.

As described above, in drive device 101 according to the second embodiment, switching element SW5 and SW6 can be further arranged to execute the same soft cutoff control at the time of short circuit detection as in the first embodiment. In particular, since the switching element SW6 can be kept on during the short-circuit protection control, the control operation for soft cutoff can be simplified compared to the first embodiment in which the switching element SW4 is intermittently turned on / off. The point is advantageous.

Note that the driving device according to the second embodiment can also be configured to connect

load resistors

181 and 182 in series with switching elements SW3 and SW4, as in Modification 1 (FIG. 6) of the first embodiment. It is.

Alternatively, in the drive device 101, as in the second modification of the first embodiment (FIG. 7), in addition to the DC power supply 110, a DC power supply 115 and a power supply node 113 may be further arranged. In this case, the power supply node 113 is connected to the control source terminal 12 of the semiconductor element 10 as in FIG. Note that the switching element SW6 can be connected between the node N3 and the

power supply node

112 or 113. In particular, by connecting the switching element SW6 between the node N3 and the power supply node 113, it is possible to prevent the semiconductor element 10 from being turned on again due to noise or the like after the short circuit is cut off.

Also, like the driving device 101x shown in FIG. 18, the third modification (FIG. 17) of the first embodiment can be combined with the driving device 101 according to the second embodiment. Specifically, in drive device 110x, in the configuration of drive device 101 (FIG. 8), in place of reactor Lr, a series circuit including an on-reactor Lron and an on-diode DLon, and an off-reactor, as in FIG. A series circuit including Lloff and an off diode DLoff is connected in parallel between nodes N1 and N2.

Embodiment 3 FIG.
In the third embodiment, variations of the short circuit detection unit will be described.

FIG. 11 is a block diagram for explaining a short-circuit detection unit 161 according to the first example of the third embodiment.

Referring to FIG. 11, in drive device 100 (FIG. 1) according to the first embodiment, short circuit detection unit 161 is arranged instead of short circuit detection unit 160.

The short-circuit detector 161 detects the occurrence of a short-circuit path based on the detected value of the drain-source current of the semiconductor element 10. Specifically, the short circuit is detected based on the passing current of the current detection element 191 connected in parallel with the semiconductor element 10.

For example, the current detection element 191 can be configured by a transistor having a control electrode (gate) connected to the gate (G) of the semiconductor element 10. The current detection element 191 is controlled to be turned on and off in the same manner as the semiconductor element 10 and allows a current proportional to the drain-source current of the semiconductor element 10 to pass therethrough. The current detection resistor 192 is arranged so that the current of the current detection element 191 passes through.

The short-circuit detection unit 161 is configured to receive the electromotive voltage generated in the current detection resistor 192 and set the short-circuit detection signal Ssc to the H level when the electromotive voltage exceeds a predetermined determination voltage.

Since the current ratio between the semiconductor element 10 and the current detection element 191 depends on the ratio of the transistor sizes of the two, the determination voltage can be set using the ratio and the withstand current of the semiconductor element 10. In addition, the short circuit detection unit 161 can detect a short circuit by using the drain-source current differential value or the integral value in addition to the drain-source current value itself.

By using the short circuit detection unit 161, it is possible to improve the detection accuracy of the short circuit by making the determination directly based on the current. Further, since it is not necessary to connect the short-circuit detection unit 161 to a high-voltage part (the drain of the semiconductor element 10), it is possible to suppress the failure of the drive device 100 and to reduce the insulating region of the circuit board. .

11 is the same as that of FIG. 1 and the details will not be repeated. Further, the operation of the control circuit 150 according to the short circuit detection signal Ssc from the short circuit detection unit 161 can be the same as that of the first embodiment.

As described above, even when the occurrence of the short circuit is detected by the short circuit detection unit 161, the operation of the driving device 100 at the time of the L level and the H level of the short circuit detection signal Ssc (normal time / short circuit protection control) is described in the embodiment. Since it is the same as 1, detailed description will not be repeated.

FIG. 12 is a block diagram for explaining a short-circuit detection unit 162 according to the second example of the third embodiment.

Referring to FIG. 12, in drive device 100 (FIG. 1) according to the first embodiment, short circuit detection unit 162 is arranged instead of short circuit detection unit 160.

The short circuit detection unit 162 detects the occurrence of a short circuit path based on the detected value of the gate current of the semiconductor element 10. Specifically, a short circuit is detected based on an electromotive voltage generated in the current detection resistor 193 connected between the node N2 and the gate (G) of the semiconductor element 10.

The short circuit detection unit 162 is configured to receive the electromotive voltage generated in the current detection resistor 193 and to set the short circuit detection signal Ssc to the H level when the electromotive voltage exceeds a predetermined determination voltage.

Generally, in a semiconductor device, when a short circuit occurs during a turn-on operation, the gate current increases compared to a normal turn-on operation. Therefore, the threshold value of the gate current for detecting such a phenomenon is determined from the element characteristics, and the determination voltage can be set using the electric resistance value Rgs of the current detection resistor 193. In addition, the short circuit detection unit 162 can detect a short circuit using a differential value or an integral value of the gate current in addition to the current value of the gate current itself.

By using the short circuit detection unit 162, the circuit configuration can be simplified by reducing the number of additional arrangement elements (current detection resistors 193) for short circuit detection as compared with the short circuit detection unit 161. Further, as with the short-circuit detection unit 161, it is not necessary to connect to a high-voltage part (the drain of the semiconductor element 10), so that the failure of the driving device 100 can be suppressed and the insulation area of the circuit board can be reduced. Can do.

12 is the same as that of FIG. 1 and the details will not be repeated. Furthermore, the operation of the control circuit 150 according to the short circuit detection signal Ssc from the short circuit detection unit 162 can be the same as that of the first embodiment.

As described above, even when the short circuit detection unit 162 detects the short circuit, the operation of the driving device 100 (normal time / short circuit protection control) when the short circuit detection signal Ssc is at the L level and the H level is the same as that of the first embodiment. Since they are similar, detailed description will not be repeated.

FIG. 13 is a block diagram for explaining a short-circuit detection unit 163 according to the third example of the third embodiment.

Referring to FIG. 13, in drive device 100 (FIG. 1) according to the first embodiment, short circuit detection unit 163 is arranged instead of short circuit detection unit 160.

The short circuit detection unit 163 detects the occurrence of a short circuit path based on the voltage between the gate terminal 11 of the semiconductor element 10 and the control source terminal 12, that is, the behavior of the gate voltage Vgs of the semiconductor element 10.

In general, in a voltage-driven semiconductor element, a period in which the rise is stagnated during a voltage rise (so-called mirror period) occurs as a behavior of the gate voltage at the time of normal turn-on. During the mirror period, as the drain-source voltage of the semiconductor element 10 decreases, the parasitic capacitance between the gate and the drain increases, so that the gate current is used for charging the parasitic capacitance, so that the gate voltage rises temporarily. It is a phenomenon that stops automatically.

On the other hand, if a short circuit occurs during turn-on operation, the drain-source voltage does not decrease sufficiently, and a short-circuit current flows. Therefore, the gate voltage behavior is different from that during normal turn-on, and the above mirror period does not appear. It becomes.

Therefore, the short-circuit detection unit 163 has the gate voltage Vgs at a timing when a predetermined time has elapsed after the turn-on operation is started (for example, from the start timing of the period t3 in FIG. 2) in the mirror period at the time of normal turn-on. When the voltage is higher than the determination voltage corresponding to the voltage, the short circuit detection signal Ssc is set to the H level. This predetermined time can be determined in advance in correspondence with the timing at which the mirror period occurs if the turn-on operation is normal. In addition, the short circuit detection unit 163 can detect a short circuit using a differential value or an integral value of the gate current in addition to the voltage value itself of the gate voltage.

By using the short-circuit detection unit 163, compared to the short-

circuit detection units

161 and 162, an additional arrangement element for short-circuit detection is unnecessary, and thus the circuit configuration can be simplified. Further, similarly to the short-

circuit detection units

161 and 162, it is not necessary to connect the driving device 100 to the high voltage portion (the drain of the semiconductor element 10).

13 is the same as that of FIG. 1 and the details will not be repeated. Furthermore, the operation of the control circuit 150 according to the short circuit detection signal Ssc from the short circuit detection unit 163 can be the same as that of the first embodiment.

As described above, even when the short circuit detection unit 163 detects the short circuit, the operation of the driving device 100 at the time of L level and H level of the short circuit detection signal Ssc (during normal time / short circuit protection control) is the same as that of the first embodiment. Since they are similar, detailed description will not be repeated.

FIG. 14 is a block diagram for explaining the short-circuit detection unit 164 of the third embodiment.
Referring to FIG. 14, short-circuit detection unit 164 is arranged in place of short-circuit detection unit 160 in drive device 100 (FIG. 1) according to the first embodiment.

The short-circuit detection unit 164 detects the occurrence of a short-circuit path based on the voltage generated at both ends of the parasitic inductance 194 on the source terminal side of the semiconductor element 10. As the parasitic inductance 194, for example, the inductance of the internal wiring of the semiconductor element module incorporating the semiconductor element 10 can be used. The parasitic inductance 194 generates Le · (dIds / dt), which is the product of the inductance value Le and the rate of change of the drain-source current Ids.

The short circuit detection unit 164 receives the induced voltage generated at both ends of the parasitic inductance 194, and sets the short circuit detection signal Ssc to the H level when the induced voltage exceeds a predetermined determination voltage for a predetermined time or more. Composed. This is based on the phenomenon that the generation period of the induced voltage at both ends of the parasitic inductance 194 is longer in turn-on at the time of short circuit than in normal turn-on. Alternatively, in the turn-on at the time of a short circuit, it is possible to detect a short circuit based on the level of the induced voltage using the feature that the induced voltage at both ends of the parasitic inductance 194 is larger than that in the normal turn-on. In addition, the short circuit detection unit 164 can detect a short circuit using a differential value or an integral value of the induced voltage generated in the parasitic inductance 194.

By using the short circuit detection unit 164, it is possible to detect a short circuit with high noise resistance at high speed. Further, similarly to the short-circuit detection units 161 to 162, it is not necessary to connect the driving device 100 to the high voltage portion (the drain of the semiconductor element 10).

14 is the same as that of FIG. 1 and the details will not be repeated. Further, the operation of the control circuit 150 in response to the short circuit detection signal Ssc from the short circuit detection unit 164 can be the same as in the first embodiment.

As described above, even when the short circuit detection unit 164 detects a short circuit, the operation of the driving device 100 (normal time / short circuit protection control) when the short circuit detection signal Ssc is at the L level and the H level is the same as that of the first embodiment. Since they are similar, detailed description will not be repeated.

The functions of the short-circuit detection units 161 to 164 described in the third embodiment can also be realized by hardware processing using an electronic circuit or the like and / or software processing by program execution, like the short-circuit detection unit 160. is there.

Also, in the modified example of the first embodiment and the second embodiment and the modified example described above, it is possible to apply the short circuit detecting units 161 to 164 in place of the short circuit detecting unit 160. That is, even when the short circuit detection units 161 to 164 generate the short circuit detection signal Ssc, the control operation (normal time / short circuit protection control) corresponding to the short circuit detection signal Ssc can be performed in the same manner.

Embodiment 4 FIG.
In the fourth embodiment, a configuration of a power conversion device to which the drive device according to the present embodiment is applied will be described.

FIG. 15 is a circuit diagram showing a configuration of power conversion device 500 according to the first example of the fourth embodiment.

Referring to FIG. 15, power conversion device 500 has a so-called three-phase inverter configuration, converts DC voltage Vdc of DC power supply 510 into a three-phase AC voltage, and supplies it to motor 501 that is an AC load.

The power converter 500 includes

power supply lines

511 and 512, a smoothing capacitor 515, semiconductor elements 10Ux, 10Uy, 10Vx, 10Vy, 10Wx, 10Wy, and an inverter control circuit 505.

The power supply line 511 is connected to the positive terminal of the DC power supply 510, and the power supply line 512 is connected to the negative terminal of the DC power supply 510. Smoothing capacitor 515 is connected between

power supply lines

511 and 512.

Semiconductor elements 10Ux and 10Uy are connected in series via

power supply lines

511 and 512 via node Nu to form a U-phase arm. In the U-phase arm, the semiconductor element 10Ux corresponds to an opposing element of the semiconductor element 10Uy, and conversely, the semiconductor element 10Uy corresponds to an opposing element of the semiconductor element 10Ux.

Similarly, the semiconductor elements 10Vx and 10Vy are connected in series via the node Nv between the

power supply lines

511 and 512 to form a V-phase arm. Further, semiconductor elements 10Wx and 10Wy are connected in series via

power supply lines

511 and 512 via node Nw to form a W-phase arm.

The inverter control circuit 505 controls on / off command signals Sin1 to Sin1 for controlling the semiconductor elements 10Ux, 10Uy, 10Vx, 10Vy, 10Wx, and 10Wy so that each phase arm operation for DC / AC voltage conversion by the three-phase inverter is performed. Sin6 is generated. For example, the on / off command signals Sin1 to Sin6 are generated according to pulse width modulation (PWM) control for making a pulse voltage having a peak value of the DC voltage Vdc a pseudo sine wave voltage.

The driving devices GDUx, GDUy, GDVx, GDVy, GDWx, GDWy are connected to the semiconductor elements 10Ux, 10Uy, 10Vx, 10Vy, 10Wx, 10Wy. The semiconductor elements 10Ux, 10Uy, 10Vx, 10Vy, 10Wx, 10Wy and the driving devices GDUx, GDUy, GDVx, GDVy, GDWx, GDWy constitute a “main conversion circuit” that performs DC / AC power conversion by a three-phase inverter. . The inverter control circuit 505 corresponds to an example of a “control device” of the power conversion device.

In the U-phase arm, the drive device GDUx turns on and off the semiconductor element 10Ux by controlling the gate voltage of the semiconductor element 10Ux according to the on / off command signal Sin1. The driving device GDUy turns on and off the semiconductor element 10Uy by controlling the gate voltage of the semiconductor element 10Uy in accordance with the on / off command signal Sin2.

In the V-phase arm, the driving device GDVx turns on and off the semiconductor element 10Vx by controlling the gate voltage of the semiconductor element 10Vx according to the on / off command signal Sin3. The driving device GDVy turns on and off the semiconductor element 10Vy by controlling the gate voltage of the semiconductor element 10Vy in accordance with the on / off command signal Sin4. Similarly, in the W-phase arm, the driving device GDWx turns on and off the semiconductor element 10Wx by controlling the gate voltage of the semiconductor element 10Wx in accordance with the on / off command signal Sin5. The driving device GDWy turns on and off the semiconductor element 10Wy by controlling the gate voltage of the semiconductor element 10Wy in accordance with the on / off command signal Sin6.

The driving devices GDUx, GDUy, GDVx, GDVy, GDWx, and GDWy are configured according to the first to third embodiments and their modifications. That is, each of the driving devices GDUx, GDUy, GDVx, GDVy, GDWx, and GDWy receives the on / off command signals Sin1 to Sin6 from the inverter control circuit 505 as the on / off command signal Sin, and the operation of FIG. The gate voltages of the semiconductor elements 10Ux, 10Uy, 10Vx, 10Vy, 10Wx, and 10Wy are controlled.

Thereby, in the power conversion device 500, the energy consumption of each driving device at the time of turn-on and turn-off of each semiconductor element constituting the three-phase inverter can be suppressed. Further, when a short-circuit current path is generated in the power conversion device 500 due to turn-on of the corresponding semiconductor element, each drive device detects the occurrence of a short-circuit by the short-circuit detection units 160 to 164 during the turn-on operation, The short circuit protection control described in the first and second embodiments and the modifications thereof can be executed.

As a result, in power conversion device 500, even if switching of each semiconductor element is performed at a high frequency, it is possible to suppress an increase in the size of the driving device, and a large current is generated in each semiconductor element due to a short circuit current caused by an arm short circuit or the like. Can be prevented.

FIG. 16 is a circuit diagram illustrating an exemplary configuration of power conversion device 600 according to the second example of the fourth embodiment.

Referring to FIG. 16, power conversion device 600 has a so-called boost chopper configuration, converts DC voltage Vdc from DC power supply 610 to DC voltage, and connects between

power lines

611 and 612 connected to DC load 601. Output to. Power conversion device 600 includes a reactor element Lcnv,

semiconductor elements

10x and 10y, and a smoothing capacitor 615.

The

semiconductor elements

10x and 10y are connected between the

power lines

611 and 612 via the node Nc. A smoothing capacitor 615 is connected between

power lines

611 and 612. The smoothing capacitor 615 removes a ripple component from the output voltage Vout of the power conversion device 600.

That is, the

semiconductor elements

10x and 10y constitute the same arm. The semiconductor element 10x corresponds to a counter element of the semiconductor element 10y, and conversely, the semiconductor element 10y corresponds to a counter element of the semiconductor element 10x.

Boost converter control circuit 605 generates on / off command signals Sin1, Sin2 for

semiconductor elements

10x, 10y in order to control the boost ratio (Vout / Vdc) by the boost converter.

Specifically, the semiconductor element 10x and the semiconductor element 10y are turned on and off alternately and periodically. At this time, the step-up ratio is controlled according to the ON period ratio (duty ratio) of the semiconductor element 10y (lower arm element) with respect to the switching period. That is, boost converter control circuit 605 generates on / off command signals Sin1, Sin2 in accordance with a duty ratio that provides a boost ratio for setting output voltage Vout to a desired voltage. Basically, the on / off command signals Sin1 and Sin2 are complementary signals.

In the power converter 600, the driving devices GDx and GDy are connected to the

semiconductor elements

10x and 10y, respectively. The driving device GDx turns on and off the semiconductor element 10x by controlling the gate voltage of the semiconductor element 10x according to the on / off command signal Sin1. The driving device GDy turns on and off the semiconductor element 10y by controlling the gate voltage of the semiconductor element 10y according to the on / off command signal Sin2. The

semiconductor elements

10x and 10y, the driving devices GDx and GDy, and the reactor element Lcnv constitute a “main conversion circuit” that performs DC / DC power conversion by the boost chopper. Boost converter control circuit 605 corresponds to an example of a “control device” of a power conversion device.

The driving devices GDx, GDy are configured according to the above-described first to third embodiments and their modifications. That is, each of the driving devices GDx and GDy receives the on / off command signals Sin1 and Sin2 from the boost converter control circuit 605 as the on / off command signal Sin, and the gates of the

semiconductor elements

10x and 10y are operated by the operation of FIG. Control the voltage.

Thereby, in the power conversion device 600, the energy consumption of each driving device at the time of turn-on and turn-off of each semiconductor element constituting the boost chopper can be suppressed. Further, when a short-circuit current path is generated in the power conversion device 600 by turning on the corresponding semiconductor element, each driving device detects the occurrence of a short circuit by the short-circuit detection units 160 to 164 during the turn-on operation, The short circuit protection control described in the first and second embodiments and the modifications thereof can be executed.

As a result, even in the power conversion device 600, even if switching of each semiconductor element is performed at a high frequency, it is possible to suppress an increase in size of the driving device, and a large current is generated in each semiconductor element due to a short circuit current caused by an arm short circuit or the like. Can be prevented.

The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

10, 10Ux, 10Uy, 10Vx, 10Vy, 10Wx, 10Wy, 10x, 10y Semiconductor element (driving target), 11 Gate terminal (semiconductor element), 12 Control source terminal (semiconductor element), 100, 100a, 100b, 101, GDUx , GDUy, GDVx, GDVy, GDWx, GDWy, GDx, GDy driving device, 110, 115, 510, 610 DC power supply, 111-113 power supply node, 150 control circuit, 160-164 short circuit detection unit, 181, 182 load resistance, 185 resistance element, 191 current detection element, 192, 193 current detection resistance, 194 parasitic inductance, 201-209, 211, 212 current path, 500,600 power converter, 501 motor, 505 inverter control circuit, 511, 51 Power line, 515,615 smoothing capacitor, 601 DC load, 605 boost converter control circuit, 611,612 power line, D drain (semiconductor element), D1 to D6 diode, G gate (semiconductor element), GSW1 to GSW6 control signal, Lcnv Reactor element, Lr reactor, N1 to N3, Nc, Nu, Nv, Nw node, Q1 to Q6 transistor, S source (semiconductor element), SW1 to SW6 switching element, Sin, Sin1 to Sin6 ON / OFF command signal, Ssc short circuit detection signal , Vdc, Vgm, Vgp DC voltage, Vgs gate voltage.

Claims

A drive device for a semiconductor element in which electrical connection or disconnection is established between the first and second main electrodes according to the voltage of the control electrode,
A first power supply node for supplying a first potential for charging the control electrode;
A second power supply node for supplying a second potential lower than the first potential;
A plurality of switching elements connected between the first and second power supply nodes and the control electrode for controlling charging and discharging of the control electrode;
A reactor disposed between a first node and a second node electrically connected to the control electrode;
A control circuit for controlling on / off of the plurality of switching elements in response to an on / off command signal of the semiconductor element;
A short-circuit detecting unit that detects the occurrence of a short-circuit path including the semiconductor element when the semiconductor element is turned on;
Each of the plurality of switching elements includes a diode for forming a reflux path when off,
When the occurrence of the short circuit path is detected by the short circuit detector during a period in which the control electrode is electrically connected to the first power supply node according to the on / off command signal, the control circuit A first path through which the current flowing through the reactor flows away from the control electrode and a second path through which the electric charge of the control electrode is discharged And controlling the plurality of switching elements so as to provide a period during which
The first path is formed including the diode of an off-state switching element among the plurality of switching elements,
The semiconductor element driving device, wherein the second path is formed including an ON-state switching element among the plurality of switching elements.
The plurality of switching elements are:
A first switching element electrically connected between the first power supply node and the first node;
A second switching element electrically connected between the second power supply node and the first node;
A third switching element electrically connected between the first power supply node and the second node;
A fourth switching element electrically connected between the second power supply node and the second node;
The control circuit generates the short-circuit path during a period in which the first switching element is turned on and the second to fourth switching elements are turned off in order to turn on the semiconductor element in accordance with the on / off command signal. Is detected, the first switching element is turned off, and on / off of the first to fourth switching elements is controlled so as to provide a period during which the fourth switching element is turned on,
The first path includes the diode of the second switching element in an off state, the reactor, and the fourth switching element in an on state.
The semiconductor device driving apparatus according to claim 1, wherein the second path includes the fourth switching element in an on state.
3. The semiconductor according to claim 2, wherein when the occurrence of the short circuit path is detected during the period, the control circuit turns off the first switching element and intermittently turns on and off the fourth switching element. Device drive device.
4. The semiconductor element drive device according to claim 2, further comprising a resistance element connected in series with the fourth switching element between the second node and the second power supply node.
First and second DC power supplies connected in series between the first and second power supply nodes via a third power supply node,
4. The semiconductor device drive device according to claim 2, wherein one of the first and second main electrodes on the low voltage side is electrically connected to the third power supply node. 5.
The plurality of switching elements are:
A first switching element electrically connected between the first power supply node and the first node;
A second switching element electrically connected between the second power supply node and the first node;
A third switching element electrically connected between the first power supply node and the second node;
A fourth switching element electrically connected between the second power supply node and the second node;
A fifth switching element electrically connected between the second node and the control electrode;
A sixth switching element electrically connected between the control electrode and the second power supply node;
The control circuit turns on the first and fifth switching elements for turning on the semiconductor element according to the on / off command signal, and turns off the second, third, fourth and sixth switching elements. When the occurrence of the short circuit path is detected during a period of time, the first and fifth switching elements are turned off and the sixth switching element is turned on. Control on and off,
The first path includes the diode of each of the second and third switching elements in an off state, and the reactor,
The semiconductor device driving apparatus according to claim 1, wherein the second path includes the sixth switching element in an on state.
The semiconductor element drive device according to claim 6, further comprising a resistance element connected in series with the sixth switching element between the control electrode and the second power supply node.
First and second DC power supplies connected in series between the first and second power supply nodes via a third power supply node,
One of the first and second main electrodes on the low voltage side is electrically connected to the third power supply node,
8. The semiconductor element driving device according to claim 6, wherein the sixth switching element is disposed between the second node and the second or third power supply node.
The reactor is
An on-reactor and an off-reactor electrically connected in parallel between the first and second nodes;
The driving device includes:
An on diode connected in series with the on reactor between the first and second nodes, with the direction from the first node toward the second node as a forward direction;
2. An off-diode further connected in series with the off-reactor between the first and second nodes, with a direction from the second node toward the first node as a forward direction. 9. The semiconductor device driving apparatus according to any one of items 1 to 8.
The short-circuit detection unit is configured such that, during the period, the voltage between the main electrodes of the semiconductor element, the current flowing through the semiconductor element, the current of the control electrode, the behavior of the voltage of the control electrode, and the main of the electric semiconductor element The semiconductor element drive device according to any one of claims 1 to 9, wherein the occurrence of the short-circuit path is detected based on any one of induced voltages generated in a parasitic inductance of a wiring through which a current between the electrodes passes.
A main conversion circuit configured to include a plurality of the semiconductor elements, and to convert and output input power;
A control device that generates the on / off command signal of each of the semiconductor elements to control the main conversion circuit;
The drive circuit according to any one of claims 1 to 10, wherein the main conversion circuit is disposed corresponding to each of the semiconductor elements,
The drive device is a power conversion device that controls a voltage of the control electrode of the corresponding semiconductor element in accordance with the on / off command signal from the control circuit.