JP2001045740A - Drive circuit of power semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive circuit of a power semiconductor element which can adequately restrain a surge voltage generated by a parasitic inductance, with a comparatively simple circuit configuration. SOLUTION: When an input signal changing to a low level is supplied, an MOSFET (M1) 49 is turned off and an MOSFET (M2) 51 is turned on via a level shift circuit 47. A power semiconductor element 30 is to be driven to a low level. Gate charges of the element 30 starts discharge via a resistor 55. At the same time, an MOSFET (M4) 63 is turned on by an output of an MMV circuit 45. The gate charges of the element 30 starts discharge via a resistor 67, and the gate charges are discharged quickly. when drain voltage reaches a drain voltage which corresponding to the vicinity, where a drain current of the element 30 starts to decrease, the drain voltage is detected by an MOSFET (M3) 61, and the MOSFET (M4) 63 is made to turn off. The gate charges are discharged only through a resistor 55. The discharge becomes gentle, and di/dt is made small, so that a surge voltage is restrained within a small range.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device driving circuit for driving a power semiconductor device for switching a relatively large load current such as a load current flowing in an AC motor or the like. The present invention relates to a power semiconductor device driving circuit capable of suppressing a surge voltage generated by a parasitic inductance existing in a circuit wiring due to di / dt at the time of switching of a power semiconductor device.

[0002]

2. Description of the Related Art In a drive circuit for a power semiconductor device of this type, a drive circuit for suppressing a surge voltage generated due to di / dt at the time of switching is disclosed in, for example, Japanese Patent Application Laid-Open No. 11-18410. There is an arc-extinguishing element drive circuit.

In this conventional drive circuit, as shown in FIG. 10 and a timing chart in FIG. 11, an input current supplied to the photocoupler 5 ((a) in FIG. 11).
The output voltage output from the amplifier 11 in response to
(B)) serves as a current reference for the amplifier 17 that constitutes the operational amplifier together with the resistors 12 to 16 and is input to the amplifier 17 and the collectors of the series-connected transistors 3 and 4 for driving the power element 1. , That is, the voltage difference between both ends of the resistors 23 and 24, is input to the amplifier 17,
Using the output voltage of the amplifier 17 as a voltage reference,
9 and to an amplifier 22 constituting an operational amplifier. That is, the current at the time of positive output of the series-connected transistors 3 and 4 for driving the power element 1 is negatively fed back from the resistor 23 to the input of the amplifier 17 via the resistor 13, and the current at the time of negative output is fed from the resistor 24 to the resistor 14. Through the amplifier 17
Negative feedback to the input. Also, the output voltage of the amplifier 22 is controlled to be a voltage corresponding to the voltage reference, and the output voltage of the amplifier 22 controls the gate current of the power element 1 via the transistors 3 and 4 to control the power element 1 Is driving.

That is, in the conventional drive circuit shown in FIG. 10, a gate current according to the current reference flows into the power element 1, and the rise time of the main circuit current when the power element is turned on can be controlled. it can. Similarly,
The gate current at the time of turning off flows out of the power element 1 in accordance with the current reference, so that the rise time of the main circuit current at the time of turning off the power element can be controlled. Further, this current control is performed at the time of switching of the power element, and after the element is saturated or unsaturated, that is, after the complete switch operation, the constant current control is stopped by clamping the gate voltage. Therefore, as shown in FIG. 11, the surge voltage due to the main circuit current di / dt can be suppressed by suppressing di / dt.

[0005]

In the above-mentioned conventional circuit, the di / dt of the main circuit current is monitored by observing the current flowing through the mirror element having a large current ratio provided in parallel with the power element 1. , The di / dt of this main circuit current
Di / dt is controlled by feeding back information to the gate drive signal to suppress the surge voltage. However, in this conventional circuit, since the ratio between the main circuit current and the mirror current increases, the detection current becomes weak. Thus, there is a problem that high accuracy is required for detecting the mirror current.

[0006] The present invention has been made in view of the above,
An object of the present invention is to provide a drive circuit for a power semiconductor element that can appropriately suppress a surge voltage generated by a parasitic inductance with a relatively simple circuit configuration.

[0007]

According to a first aspect of the present invention, there is provided a driving circuit for a power semiconductor device which is switched by discharging or charging a charge to a gate capacitor. A time constant varying means for varying a time constant of discharging or charging of the charge to the gate capacitance; a monitoring means for monitoring an output voltage of the power semiconductor element; and a discharging or charging of the charge to the gate capacitance in the power semiconductor element. The gist of the invention is to have a time constant control means for controlling the time constant variable means to start with a small time constant and increasing the time constant when the output voltage reaches a predetermined voltage by the monitoring means.

[0008]

According to the present invention, when discharging or charging the charge to the gate capacitance of the power semiconductor element, the time constant variable means is controlled to start with a small time constant, and the output voltage of the power semiconductor element is reduced. When the voltage reaches a predetermined voltage corresponding to a sharp change point of di / dt, the time constant is increased. Therefore, the discharge of the gate charge becomes slow, di / dt decreases, and L due to the parasitic inductance L decreases. Surge voltage Vsg represented by di / dt can be accurately suppressed with a simple circuit configuration.
Since the time constant is small at the start of charging and discharging, the switching time can be shortened overall.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a drive circuit of a power semiconductor device according to one embodiment of the present invention. The drive circuit shown in the figure has a power semiconductor element 30 composed of a MOSFET that can be used as a switching element for driving an AC motor, for example, and the power semiconductor element 30 is driven and controlled by an input signal supplied to an input terminal 43. You. Such a drive circuit of a power semiconductor element is used for a motor control system for driving and controlling an AC motor or the like of a hybrid vehicle which is being put into practical use as having a power system configured by combining a gasoline engine and an electric motor, for example. be able to.

Before describing the drive circuit of the power semiconductor device shown in FIG. 1 in detail, a motor control system to which the drive circuit of the power semiconductor device is applied as an example will be described first. The motor control system controls the AC motor for powering or power generation / regeneration of the hybrid vehicle. It controls the voltage inverter that converts the DC voltage of the battery mounted on the vehicle into three-phase AC and the output torque of the AC motor. And a control unit.

As shown in detail in FIG. 3, the motor control system drives and controls an AC motor 31 composed of, for example, a synchronous motor or an induction motor, and a three-phase UVW-phase bridge for driving the AC motor 31. A plurality of power semiconductor elements 30 constituting the voltage inverter, a plurality of freewheel diodes 38 connected in parallel to each of the power semiconductor elements 30, and a control unit for controlling the driving of the plurality of power semiconductor elements 30 , A gate drive circuit 35, a complementary PWM generation circuit 36, and a motor controller 37. The plurality of power semiconductor elements 30 constitute a three-phase bridge voltage inverter by three sets of power semiconductor elements 30 connected in series two by two, and a battery 33 is provided at both ends of each set of power semiconductor elements 30 connected in series. DC voltage is applied,
An electrolytic capacitor 34 is connected in parallel to both ends of the battery 33. Further, a rotation sensor 32 for detecting the magnetic pole position of the rotor of the AC motor 31 is provided, and the magnetic pole position information of the AC motor 31 detected by the rotation sensor 32 is supplied to a motor controller 37.

The motor controller 37 calculates a drive signal of the AC motor 31 based on a torque command signal from a vehicle control controller (not shown) and magnetic pole position information from the rotation sensor 32, thereby obtaining a UVW phase signal for the complementary PWM generation circuit 36. A voltage control signal is output for each phase. The complementary PWM generation circuit 36 converts the voltage control signal from the motor controller 37 into a voltage PWM (pulse width modulation: Pulse Widt).
h Modulation) signal and supplies it to the gate drive circuit 35. The gate drive circuit 35 includes the complementary PWM generation circuit 3
6 is converted into a gate drive signal for driving a plurality of power semiconductor elements 30 constituting a three-phase bridge voltage inverter, and supplied to each power semiconductor element 30.

The plurality of power semiconductor elements 30 are driven by a gate drive signal supplied from a gate drive circuit 35, and drive the AC motor 31 by supplying a UVW-phase three-phase output signal. As described above, the plurality of power semiconductor elements 30 are three sets connected in series by two, ie, UVW
The three-phase power semiconductor device 30 is composed of three phases.
Of the three-phase power semiconductor elements 30 connected in series, each of the UVW-phase power semiconductor elements 30 connected to the positive electrode side of the battery 33 is connected to UP, UP as shown in FIG.
The VP, WP side power semiconductor element 30 is called a battery 3
3 are connected to the UN, VN and WN side power semiconductor elements 3 connected to the UVW phase
Let's call it 0.

FIG. 4 is a diagram showing a current waveform of a three-phase output signal from the power semiconductor element 30 for driving the AC motor 31. The U-phase driving currents Iu and V for driving the U-phase of the AC motor 31 are shown in FIG. The V-phase driving current Iv for driving and the W-phase driving current Iw for driving the W phase are sine waves having phases different from each other by 120 degrees in electrical angle. In order to supply such a sine-wave motor drive current to the AC motor 31, the complementary PWM generation circuit 36 generates a voltage PWM signal whose duty ratio changes in a sine wave shape, and outputs the voltage PWM signal via the gate drive circuit 35 to the AC motor 31. Is driving.

FIG. 5 shows a U-phase drive current waveform focusing only on the U-phase which is one of the three-phase drive currents and a change in the duty ratio of the UP-side voltage PWM signal for driving the UP-side power semiconductor element 30. FIG. As shown in the figure,
The duty ratio of the UP-side voltage PWM signal varies in a sine wave form from 0% (+ dead time) to 100% (-dead time), but the UN-side voltage PWM signal for driving the UN-side power semiconductor element 30 is UP. The change of the duty ratio on the side is inverted. When the duty control of the UP-side and UN-side power semiconductor elements 30 is performed in a sinusoidal manner, the average value becomes a sinusoidal wave, and a sinusoidal voltage signal is supplied to the AC motor 31. As a result, a sine-wave motor current as shown in FIG. Note that actually, there is a phase difference between the voltage and the current of the AC motor 31 and the phase is equal to the motor power factor cosφ, but this phase difference is omitted in FIG.

FIG. 6 is a waveform diagram showing the waveforms of a voltage PWM signal applied to the gates of the UP-side and UN-side power semiconductor elements 30, that is, the UP-side gate drive signal and the UN-side gate drive signal. They are complementary to each other. In the figure, one pulse period is a PWM carrier period, and usually uses a frequency such as 10 kHz. A dead time is provided between the edges of the UP-side gate drive signal and the UN-side gate drive signal to prevent a through current from flowing through the power semiconductor element 30.

FIG. 7 is a circuit diagram of the driving circuit shown in FIG.
FIG. 7 is a diagram illustrating a circuit operation of a phase and illustrating a parasitic inductance that causes a surge voltage to occur. As shown in the figure, when a current Iu flows through the AC motor 31 in the direction indicated by the arrow, the UP-side power semiconductor element 30
When a high-level UP-side gate drive signal is applied to the gate of the IGBT, a current Ip flows through the UP-side power semiconductor element 30 as shown in the figure, and a high-level UN-side gate drive signal is applied to the gate of the UN-side power semiconductor element 30. When a signal is applied, U
A current In flows through the free wheel diode 38 of the N-side power semiconductor element 30 as shown. As described above, the motor current flowing to the AC motor 31 continues to flow in one direction, but in this case, the UP-side and UN-side power semiconductor elements 3
The main current flowing through 0 is switched and commutated by the gate drive signal.

When the main current is commutated in this way, a parasitic inductance existing in the bus bar wiring and the like in the voltage inverter appears in the circuit as indicated by reference numeral 39 in FIG. 7, and a surge voltage is generated by the inductance 39. . Assuming that the parasitic inductance is L, the magnitude of the surge voltage is L · di / dt.

FIG. 8 is a diagram showing signal waveforms of various parts showing how a surge voltage is generated when the power semiconductor element 30 is turned off to cut off the current. As shown in FIG. 8A, when the on / off command signal is turned off, the gate drive signal of the power semiconductor element 30 does not turn off immediately as shown in FIG. As shown in FIG. 8C, the drive current of the power semiconductor element 30 does not immediately decrease to 0 as well, and the level of the gate drive signal is equal to or higher than a predetermined threshold value. And then becomes zero. Then, as shown in FIG. 8D, the collector voltage of the power semiconductor element 30 starts to increase gradually due to the decrease of the gate drive signal, but the surge voltage Vsg is generated due to the influence of the parasitic inductance 39 in this increase. Generally, when the current is cut off, the switching time tends to be short. However, as the switching time is shortened, di / dt increases and harmful surge voltage also increases.

The drive circuit of the power semiconductor device of this embodiment shown in FIG. 1 is intended to suppress di / dt in order to suppress the surge voltage generated by the parasitic inductance as described above. Hereinafter, returning to FIG. 1, the drive circuit of the power semiconductor device of the present embodiment will be described in detail. The embodiment shown in FIG. 1 shows only the configuration when the power semiconductor element is cut off for simplification.

In FIG. 1, an input terminal 43 is connected to a monostable multivibrator circuit (hereinafter abbreviated as MMV circuit) 45 and a level shift circuit 47, and an input signal from the input terminal 43 is supplied to the MMV circuit 45 and the level shift circuit 47. It is supplied to the shift circuit 47. Note that this input signal corresponds to the voltage PWM signal from the complementary PWM generation circuit 36 described with reference to FIG. Further, the power semiconductor element 30 in FIG. 1 corresponds to the power semiconductor element 30 in FIG. 3, and a circuit between the input terminal 43 and the power semiconductor element 30 is provided in the gate drive circuit 35 in FIG. However, the circuit of FIG. 1 shows only one circuit configuration of one of the three phases of the UVW phase, and the gate drive circuit 35 of FIG.
Includes a three-phase UVW-phase circuit configuration.

As described above, when the input signal is supplied, the MMV circuit 45 is driven at the falling edge at which the input signal becomes low, and generates an output pulse having a predetermined pulse width. The level shift circuit 47 outputs the 0-5 V voltage PWM signal from the complementary PWM generation circuit 36 to 0-VB.
(12V, which is the battery voltage), and the signal level is inverted. The output signal of the level shift circuit 47 is supplied to the battery voltage + via the current limiting resistors 53 and 55.
MOSF connected in series between VB (12V) and Vss
The signals are input to the gates of the ET (M1) 49 and the MOSFET (M2) 51. That is, the battery voltage + VB and V
A series circuit of the MOSFET (M1) 49, the current limiting resistors 53 and 55 and the MOSFET (M2) 51 is connected between the power semiconductor device 30 and the ss, and the connection point of the resistors 53 and 55 is connected to the gate of the power semiconductor element 30. . This series connection circuit forms a pre-driver circuit that charges and discharges the gate capacitance of the power semiconductor element 30.

Operationally, the level shift circuit 47
Is applied to the gates of MOSFET (M1) 49 and MOSFET (M2) 51,
MOSFET (M1) 49 is turned off and MOSFET
(M2) 51 is turned on, thereby turning off the power semiconductor element 30. When a low-level output signal is applied from the level shift circuit 47 to the gates of both MOSFETs 49, 51, the MOSFET (M1) 49 is turned on. And the MOSFET (M2) 51 is turned off, thereby turning on the power semiconductor element 30.

The drain of the power semiconductor element 30 is connected to the potential Vss via the resistors 57 and 59, and
The connection point between the transistors 7 and 59 is connected to the gate of the MOSFET (M3) 61, so that the voltage at the drain of the power semiconductor element 30, that is, the output voltage of the power semiconductor element 30 is connected to the MOSFET (M3) through the connection point between the resistors 57 and 59. M3)
It is fed back to the 61 gate. As a result,
When the output voltage of the power semiconductor element 30 becomes equal to or higher than a predetermined threshold, the MOSFET (M3) 61 is turned on. The drain of the MOSFET (M3) 61 is connected to the output of the MMV circuit 45 via the resistor 65 and to the gate of the MOSFET (M4) 63. The drain of the MOSFET (M4) 63 is a resistor 6
7 is connected to the gate of the power semiconductor element 30.

As a result of such a connection, the output pulse of the MMV circuit 45 is applied to the MOSFET (M4) 6 via the resistor 65.
3 is applied to the gate of MOSFET
(M4) 63 is turned on, thereby discharging the gate charge accumulated in the gate capacitance of the power semiconductor element 30 via the resistor 67. And MOSF
Even when the output pulse of the MMV circuit 45 is applied to the gate of the ET (M4) 63 via the resistor 65, if the output voltage of the power semiconductor element 30 becomes equal to or higher than a predetermined threshold,
The MOSFET (M3) 61 is turned on, and the MOS
The FET (M4) 63 is turned off, and the discharge of the gate capacitance of the power semiconductor element 30 via the resistor 67 is stopped.

Next, with reference to the timing chart shown in FIG. 2, the operation of the drive circuit of the power semiconductor device of the present embodiment configured as described above will be described.

First, when the voltage PWM signal from the complementary PWM generating circuit 36 which is an input signal to the input terminal 43 is at a high level, as shown in FIG. 2, both the level shift circuit 47 and the MMV circuit 45 The output is at low level,
MOSFET (M1) 49 is on, MOSFET
(M2) 51 is off. Also, MOSF
The gate voltage of ET (M4) 63 is at a low level,
The SFET (M4) 63 is turned off. Further, a power semiconductor element 3 described as a main circuit Tr in FIG.
The gate voltage of 0 is at a high level as shown in FIG. 2E, the power semiconductor element 30 is turned on, and an output current flows as shown in FIG. 2G, thereby driving the AC motor 31. I have. In this case, the drain voltage of the power semiconductor element 30 is at a low level as shown in FIG.

In this state, when the input signal to the input terminal 43 changes from the high level to the low level, the output of the level shift circuit 47 goes high as shown in FIG. Numeral 45 generates an output pulse having a predetermined pulse width as shown in FIG. When the output of the level shift circuit 47 becomes high level, the MOSFET
(M1) 49 is turned off, and the MOSFET (M2) 51 is turned on, so that the gate charge stored in the gate of the power semiconductor element 30 is reduced by the resistance 5 as shown in FIG.
5 and the MOSFET (M2) 51 starts discharging. On the other hand, the output pulse from the MMV circuit 45
2C is applied to the gate of the MOSFET (M4) 63 to turn on the MOSFET (M4) 63 as shown in FIG. 2C, so that the gate of the power semiconductor element 30 is connected via the resistor 67 and the MOSFET (M4) 63. Connected to the Vss potential to discharge the gate charge of the power semiconductor element 30. As a result, the gate charge stored in the gate of the power semiconductor element 30 is changed to the resistance 55 and the MOSFET.
(M2) First path through 51, resistor 67 and MO
In two systems of the second path through the SFET (M4) 63,
In other words, a large and steep discharge occurs as shown in FIG. In this state, the gate voltage of the power semiconductor element 30 rapidly decreases as shown in FIG.

In this state, the power semiconductor element 30
Is in an ON state, and its drain voltage is at a low level as shown in FIG. 2 (f). Therefore, a voltage obtained by dividing this drain voltage by the resistors 57 and 59 is a MOSFET (M3) 61
, The MOSFET (M3) 61 is off.

As described above, the gate charge of the power semiconductor device 30 is rapidly discharged, and the gate voltage is reduced as shown in FIG.
In the case of a rapid decrease as shown in (e),
When the gate voltage approaches the vicinity of the threshold value Vth of the power semiconductor element 30, the drain voltage of the power semiconductor element 30 starts increasing as shown in FIG. In this vicinity, the gate voltage is maintained near the threshold value Vth and the gate charge is discharged as shown in FIG. 2 (e), but the power semiconductor element 30 tries to maintain the drain current. The drain voltage of 30 is shown in FIG.
It increases monotonically as shown in FIG.

When the gate charge is further discharged and the gate voltage drops to a state where the power semiconductor element 30 cannot maintain the drain current, the drain current of the power semiconductor element 30 rapidly decreases as shown in FIG. Start. In this way, the vicinity where the drain current of the power semiconductor element 30 starts to decrease is detected by monitoring the drain voltage of the power semiconductor element 30 by the MOSFET (M3) 61. Power semiconductor element 30 at this time
2 (f), the drain voltage VTH0 is divided by the resistors 57 and 59 so that the voltage of the resistors 57 and 59 becomes equal to the threshold Vth of the MOSFET (M3) 61. Set the value.

By setting the resistors 57 and 59 in this manner, when the drain voltage of the power semiconductor element 30 reaches the drain voltage VTH0 corresponding to the vicinity where the drain current of the power semiconductor element 30 starts to decrease, the MOSFE
T (M3) 61 is turned on, and as a result, MOSFET
(M4) The gate of 63 goes low, which causes M
The OSFET (M4) 63 is turned off as shown in FIG. That is, at the start of the off operation of the power semiconductor element 30, the MO having a high level as shown in FIG.
At this point, the gate voltage of the SFET (M4) 63 becomes MMV.
It changes to low level regardless of the output pulse from the circuit 45. As described above, when the MOSFET (M4) 63 is turned off, the discharge of the gate charge of the power semiconductor element 30 is stopped by the resistance 5
Since only the first path through the gate 5 is used, the value of the discharge current of the gate charge is reduced as shown in FIG. 2D, and the discharge time constant of the gate charge is increased.

As a result, the discharge of the gate charge of the power semiconductor element 30 becomes slow, and the gate voltage gradually decreases, so that di / dt becomes small and is represented by L · di / dt due to the parasitic inductance L. Surge voltage Vsg can be suppressed to a small value. Thereafter, the gate charge is completely discharged by the resistor 55 and the MOSFET (M2) 51, the power semiconductor element 30 is completely cut off, and the drain current, which is the output current, becomes zero as shown in FIG. Become.

In the above embodiment, the resistors 53, 5
5, 65 have been described as individual resistors, but the MOSFET (M1) 49 and the MOSFET (M
2) The ON resistance of the MOSFET 51 (M4) 63 may be used.
It can also be realized by the on-resistance of the FET.

In the above embodiment, only the case where the power semiconductor element 30 is cut off, that is, the case where the current of the power semiconductor element 30 falls, the present invention is applied when the current of the power semiconductor element 30 rises. It is needless to say that the surge voltage can be suppressed by applying the same circuit configuration.

Next, a driving circuit of a power semiconductor device according to another embodiment of the present invention will be described with reference to FIG. The drive circuit of the power semiconductor device of the present embodiment monitors the drain voltage of the power semiconductor device 30 by the MOSFET (M3) 61 in the embodiment shown in FIG. 1, and detects the drain voltage V corresponding to the vicinity where the drain current starts to decrease.
MOSFE that turns off MOSFET (M4) 63 when the drain voltage of power semiconductor element 30 reaches TH0.
A voltage comparator 71, an AND circuit 77, and resistors 73 and 75 are used instead of the circuit including the T (M3) 61 and the resistor 65.
The only difference is the use of a circuit consisting of: and the other configuration and operation are the same as those of the embodiment of FIG.

That is, in the drive circuit of the power semiconductor device shown in FIG. 9, the drain voltage which is the output voltage of the power semiconductor device 30 is divided by the resistors 57 and 59 and the voltage comparator 7
1 and is compared with a reference voltage from a connection point of the resistors 73 and 75 supplied to the other input. This reference voltage is a drain voltage VTH0 corresponding to the vicinity where the drain current of the power semiconductor element 30 starts to decrease.
Is equivalent to Therefore, the voltage comparator 71 compares the drain voltage of the power semiconductor element 30 with the reference voltage, and corresponds to a case where the drain voltage becomes higher than the reference voltage, that is, a vicinity where the drain current of the power semiconductor element 30 starts to decrease. When the drain voltage reaches the drain voltage VTH0, the voltage comparator 71 supplies a low-level output signal to the AND circuit 77, and thereby the MMV circuit 45
Inhibit the output pulse from the MOSFET (M
4) 63 is turned off. As a result, the gate charge of the power semiconductor element 30 is discharged only through the first path via the resistor 55.
As shown in (d), the gate charge becomes smaller and the discharge time constant of the gate charge becomes larger.

Accordingly, the discharge of the gate charge of the power semiconductor element 30 becomes slow, and the gate voltage decreases gradually, so that di / dt becomes small and is represented by L · di / dt due to the parasitic inductance L. Surge voltage V
sg can be suppressed to a small value.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a drive circuit of a power semiconductor device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the drive circuit of the embodiment shown in FIG.

3 is a block diagram showing a configuration of a motor control system to which the drive circuit of the power semiconductor device shown in FIG. 1 is applied.

4 is a diagram showing a current waveform of a three-phase output signal output from a power semiconductor element driving an AC motor in the motor control system shown in FIG.

5 shows a U-phase drive current waveform focusing only on the U-phase which is one of the three-phase drive currents in the motor control system shown in FIG. 3, and an UP driving the UP-side power semiconductor element.
FIG. 7 is a diagram illustrating a change in a duty ratio of a side voltage PWM signal.

6 is a voltage PWM signal applied to the gates of the UP-side and UN-side power semiconductor elements in the motor control system shown in FIG. 3, that is, the UP-side gate drive signal and U
FIG. 4 is a waveform chart showing a waveform of an N-side gate drive signal.

FIG. 7 is a diagram illustrating a U-phase circuit operation in the drive circuit of the motor control system illustrated in FIG. 3 and illustrating a parasitic inductance that causes a surge voltage to occur.

8 is a diagram showing signal waveforms of respective parts showing a state in which a surge voltage occurs when a current is cut off by turning off a power semiconductor element in the motor control system shown in FIG. 3;

FIG. 9 is a circuit diagram showing a configuration of a drive circuit of a power semiconductor device according to another embodiment of the present invention.

FIG. 10 shows a conventional driving circuit of Japanese Patent Application No. 11-1841.
FIG. 2 is a circuit diagram showing a configuration of a self-extinguishing element driving circuit disclosed in No. 0.

FIG. 11 is a timing chart showing an operation of the conventional driving circuit shown in FIG.

[Explanation of symbols]

 Reference Signs List 30 power semiconductor element 43 input terminal 45 MMV circuit 47 level shift circuit 49 MOSFET (M1) 51 MOSFET (M2) 61 MOSFET (M3) 63 MOSFET (M4) 71 voltage comparator 77 AND circuit

Claims (1)

[Claims] 1. A drive circuit for a power semiconductor device which is switched by discharging or charging a charge to a gate capacitance, wherein a time constant variable means for varying a time constant of discharging or charging the charge to a gate capacitance in the power semiconductor device; Monitoring means for monitoring the output voltage of the power semiconductor element; and when discharging or charging the charge to the gate capacitance in the power semiconductor element, controlling the time constant variable means to start with a small time constant, And a time constant control means for increasing the time constant when the output voltage reaches a predetermined voltage.