200928659 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種功率轉換裝置及方法，特別是指 一種具有昇壓能力的功率轉換裝置及方法。 【先前技術】 在電源供應裝置的領域來說，類比控制晶片佔有重要 地位’其具有週邊保護電路及回授補償電路，主要是由運 算放大器、比較器及開關等元件組成，既然類比集成電路 主要由高電壓製程所製造，因此可在10伏到2〇伏的高電 壓環境運作，然而，由於電源供應裝置日益複雜化，包括 對於螢幕、通訊的電源管理，類比控制電源裝置已無法因 應此種需求，因此，具有可程式化邏輯閘陣列（FPGA)、數 位訊號處理器（DSP)、微處理器或特殊定義的ASIC的數位 1C的數位控制電源裝置供應成為近年來的趨勢。 但是數位1C的元件存在一些問題，也就是為了降低產 品價格’其電路變得小型化且工作電壓越來越小，直至今 曰’數位1C的工作電壓限制在3·3伏甚至更低，雖然減少 數位電源的工作電壓可降低功耗，但是對於MOSFET的閘 極驅動電壓則無法降低’例如，以3.3伏即無法驅動 MOSFET的閘極所需的5伏電壓。 除此之外，越多閘極驅動電壓倍降低則需要越多閘極 電容，因此也就越難以將MOSFET完全導通；另外，邏輯 電路及閘極驅動電路被分開，則需要使用二個工作電壓源 ’也就是當越多電路需要分別供電時，將難以實現整合高 200928659 - 密度的數位電路。 如圖1所示，目前切換式電源供應裝置的閘極驅動器9 具有一對功率開關91、92及一反相器93，且供應一脈波控 制訊號vin及一正電源Vs，閘極驅動器9只會產生一輸出 電壓V〇ut，且其輸出電壓v〇ut不高於電壓源Vs。 前述閘極驅動器9目前已有許多關於效能（Efficiency) 及改變準位（Level shift)的研究，但很少有研究如何將其電 泛壓源昇壓，既然電子產品内部的電路需要不同電源，則勢 必需要具有昇磨能力的功率轉換裝置。 【發明内容】 因此，本發明之目的，即在提供一種具有昇壓能力的 功率轉換裝置及方法。 於是’本發明具有昇壓輸出之功率轉換裝置包含一充 電驅動器及一昇壓模組，該充電驅動器接受一電源供電並 具有一對功率開關，該對功率開關共同接收一脈波控制訊 多號且二者輸出連接於一節點，該脈波控制訊號用以調控該 對功率開關的導通與否。 該昇壓模组柄接該節點’具有具有一充電迴路及一儲 能元件’該充電迴路係以雙倍之該電源電壓對該儲能元件 充電以使該儲能元件產生雙倍於該電源電壓之輸出電壓。 本發明具有具有昇壓能力的功率轉換方法係用於一功 率轉換裝置，該功率轉換裝置包括一具有功率開關之閘極 驅動器，及一耦接該充電驅動器之昇壓模組。 該方法包含下述步驟：（a)該充電驅動器接受一電源供 6 200928659 電，並接收一具有一第一模式及一第二模式的脈波控制訊 號以調控其功率開關的導通與否；（b)在該第—模式下，該 充電迴路以雙倍之該電源電壓對該儲能元件充電；（c)在該 第二模式下’該放電迴路對該儲能元件放電；及（d)該儲能 元件於該第一模式及該第二模式交替產生雙倍於該電源電 壓之輸出電壓及接地之輸出電壓。BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a power conversion apparatus and method, and more particularly to a power conversion apparatus and method having a boosting capability. [Prior Art] In the field of power supply devices, analog control chips occupy an important position. They have peripheral protection circuits and feedback compensation circuits, which are mainly composed of operational amplifiers, comparators, and switches, since analog ICs are mainly Manufactured by a high-voltage process, it can operate in a high-voltage environment of 10 volts to 2 volts. However, due to the increasing complexity of power supply devices, including power management for screens and communications, analog control power supplies have been unable to cope with this. Demand, therefore, the availability of digital 1C digitally controlled power supply units with programmable logic gate arrays (FPGAs), digital signal processors (DSPs), microprocessors or specially defined ASICs has become a trend in recent years. However, there are some problems with the digital 1C components, that is, in order to reduce the price of the product, the circuit becomes smaller and the operating voltage is getting smaller and smaller. Until now, the operating voltage of the digital 1C is limited to 3.3 volts or even lower, although Reducing the operating voltage of the digital power supply reduces power consumption, but the gate drive voltage of the MOSFET cannot be reduced 'for example, the voltage of 5 volts required to drive the gate of the MOSFET at 3.3 volts. In addition, the more the gate drive voltage is reduced, the more gate capacitance is needed, so the more difficult it is to turn the MOSFET fully on. In addition, the logic circuit and the gate drive circuit are separated, and two operating voltages are required. The source 'that is, when more circuits need to be separately powered, it will be difficult to achieve a digital circuit with a high integration of 200928659 - density. As shown in FIG. 1, the gate driver 9 of the switching power supply device has a pair of power switches 91, 92 and an inverter 93, and supplies a pulse control signal vin and a positive power supply Vs, and the gate driver 9 Only one output voltage V〇ut is generated, and its output voltage v〇ut is not higher than the voltage source Vs. The aforementioned gate driver 9 has a lot of research on efficiency and level shift, but few studies have tried to boost its electric voltage source. Since the circuits inside the electronic product require different power sources, It is therefore necessary to have a power conversion device with a grinding capability. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a power conversion apparatus and method having boosting capability. Therefore, the power conversion device with the boost output of the present invention comprises a charging driver and a boosting module, the charging driver receiving a power supply and having a pair of power switches, the pair of power switches receiving a pulse wave control signal number And the output of the two is connected to a node, and the pulse control signal is used to regulate the conduction of the pair of power switches. The boosting module handles the node 'having a charging circuit and an energy storage component'. The charging circuit charges the energy storage component by double the power voltage to cause the energy storage component to generate double the power The output voltage of the voltage. The power conversion method with boosting capability of the present invention is applied to a power conversion device comprising a gate driver having a power switch, and a boosting module coupled to the charging driver. The method comprises the following steps: (a) the charging driver receives a power source for 6 200928659, and receives a pulse wave control signal having a first mode and a second mode to regulate the conduction of the power switch; b) in the first mode, the charging circuit charges the energy storage element by double the power supply voltage; (c) in the second mode, the discharge circuit discharges the energy storage element; and (d) The energy storage device alternately generates an output voltage that is twice the output voltage of the power supply voltage and a grounded output voltage in the first mode and the second mode.
本發明具有昇壓能力的功率轉換裝置及方法可將原有 電源昇壓輸出，如此一來可供應複雜的數位控制系統所需 的多種不同電源，且可減少整個系統的體積。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之較佳實施例的詳細說明中將可清楚 的呈現。 參閱圖2，本發明具有昇壓輸出之功率 佳實施例包含-充電驅動器^及一昇廢模組二= 動器11 #受-電源Vcc供電’ i具有一反相器Βι及一對功 率開關，本較佳實施例中，該對功率開關是包括一第一電 晶體Qi及-第二電晶體Q2，第一電晶體^係一 p通道的 MOSFET元件及第二雷曰脚^此 乐一電日日體Q2係一 n通道的M〇SFET元件 〇 第電曰曰體Qi及第二電晶體&之閉極共同接收一脈波 控制訊二者輸出連接於—節點⑴，脈波控制訊號 g具有冑帛式及一第二模式以調控該對功率開關的導 通與否其中帛模式是一高準位電塵而第二模式是一 7 200928659 低準位電壓’而脈波控制訊號vg是由第一模式及第二模式 交替的一脈波，可以是波寬調變（PWM)或變頻調變（PFM)所 產生，功率開關導通與否之控制方式係當高準位電壓時， 功率開關導通（ON)，當低準位電壓時，功率開關不導通 (OFF)。 昇壓模組12耦接於該節點111，且具有一充電迴路121 、一放電迴路122、一電壓箝制電路123及一儲能元件Cgs ’其中，充電迴路121及放電迴路122分別具有一第三電 晶體Q3及一第四電晶體Q4，第三電晶體A係一 p通道的 M0SFET元件及第四電晶體&係一 n通道的M〇SFET元件 〇 本發明的運作原理在於：脈波控制訊號％經過反相器 供給第一電晶體Ql及第二電晶體Qz作為控制之用，除 此之外，電容6及二極體01被用來作為一箝制電壓的箝制 電路113，藉此控制輸出電壓vgs在一預定範圍。 參閲圖3，脈波控制訊號Vg之輸出為低準位時，放電 迴路m係對儲能元件Cgs放電；參閱圖4，脈波控制訊號 vg之輸出為高準位時，充電迴路121以雙倍電壓源Vcc對 儲能元件cgs充電，因此儲能元件Cgs可於第一模式及第二 模式交替產生雙倍電壓源及接地之輸出電壓v 。 gs 如圖3所示，脈波控制訊號vg為低準位時，第二電晶 ? q2導通’因此儲能元# Cgs充電i Vcc，且由於第三; 晶體Q3在閘極和源極的電壓為〇伏使第三電晶體^截止， 同時，由於第四電晶體q4在閘極和源極的電壓4 Vcc使第 200928659 四電晶體Q4導通，使得閘極驅動器u輸出電壓接地，為此 ，經過由第四電晶體Q4至第二電晶體&構成的放電路 徑使儲能元件Cgs放電，此時輸出電壓Vgs為接地電壓。 如圖4所示，脈波控制訊號Vg為高準位時，第一電晶 體Qi導通，除此之外，儲能元件cgs的負端電壓為電壓源 Vcc，且儲能兀件Cgs的正端電壓為2Vcc，使得二極體a 偏轉，同時，由於第三電晶體A在閘極和源極的為電壓_ Vcc使第二電晶體Q3導通，因此，閘極驅動器n的輸出電 壓為2VCC，為此，電流自第一電晶體Qi經過第三電晶體 Q3使儲能元件cgs充電，此時輸出電壓Vgs為雙倍電壓源之 電壓2VCC。 本實施例於模擬及實驗採用的電壓源Vcc為5伏特， 第一電晶體Q!及第二電晶體Q2採用型號MIC442〇的半橋 式開關（half-bridge switches)，第三電晶體q3及第四電晶體 Q4分別採用型號IRLML5103及NDS335N的開關元件。 如圖5所示’本實施例中所用的脈波控制訊號％為$ 伏特的脈波，其輸出電壓\^為1〇伏特，而分別以lkHz、 10kHz、100kHz及500kHz的開關頻率模擬及實驗的結果 ，在產生雙倍電壓源之輸出電壓方面都有良好效果。 歸納上述’本發明具有昇壓能力的功率轉換裝置1及 方法可將原有電壓源昇壓為雙倍輸出，如此一來可供應複 雜的數位控制系統’例如伺服系統，所需的多種不同電壓 源，且可減少整個系統的體積。 惟以上所述者’僅為本發明之較佳實施例而已，當不 200928659 . 能以此限定本發明實施之範圍，即大凡依本發明申請專利 - 範圍及發明說明内容所作之簡單的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一電路圖，說明目前切換式電源供應裝置的閘 極驅動器； 圖2是一電路圖，說明本發明具有正負輸出電壓之功 率轉換裝置的較佳實施例； " 圖3是一電路示意圖，說明該較佳實施例在第一模式 下，充電迴路以電壓源對儲能元件充電； 圖4是一電路示意圖，說明該較佳實施例在第二模式 下，放電迴路以電壓源對儲能元件放電；及 圖5是一波形圖，說明該較佳實施例中所用的脈波控 制訊號、為5伏特的脈波，其輸出電壓Vgs為1〇伏特。 ❹ 10 200928659 【主要元件符號說明】 〔習知〕 123 · ......箝制電壓電路 9 .......... •閘極驅動器 B!..· ……反相器 91、92 · •功率開關 Ci·· ……電容 93......... 反相器 Cgs- ……儲能元件 Vin........ 脈波控制訊號 Dr·· ......二極體 Vs ........ 正電源 Qi ·· ……第一電晶體 Vout…… 正輸出電壓 Q2… ……第二電晶體 〔本創作〕 q3··· 第二電日日體 1 .......... 功率轉換裝置 q4··· ......第四電晶體 11......... 閘極驅動器 Vcl··· ……電壓 111 ....... 節點 VCc " .....電源 12......... 充放電模組 vg…· ......脈波控制訊號 121 ....... 充電迴路 Vgs··· ••…輸出電壓 122....... 放電迴路 ❹ 11The power conversion device and method with the boosting capability of the present invention can boost the original power supply, thereby supplying a plurality of different power sources required for a complicated digital control system, and reducing the volume of the entire system. The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. Referring to FIG. 2, the present invention has a boosted output power. The preferred embodiment includes a charging driver and a liter module. The actuator 11 is powered by a power supply. The i has an inverter 及ι and a pair of power switches. In the preferred embodiment, the pair of power switches includes a first transistor Qi and a second transistor Q2. The first transistor is a p-channel MOSFET component and a second thunder pin. The electric Japanese body Q2 is an n-channel M〇SFET element, the second electric body Qi and the second transistor & the closed-pole together receive a pulse control signal. Both outputs are connected to the node (1), pulse wave control The signal g has a 胄帛 type and a second mode to regulate the conduction of the pair of power switches, wherein the 帛 mode is a high level electric dust and the second mode is a 7 200928659 low level voltage ' and the pulse wave control signal vg It is a pulse that is alternated between the first mode and the second mode, and may be generated by a bandwidth modulation (PWM) or a variable frequency modulation (PFM). When the power switch is turned on or off, the control mode is when the high level voltage is The power switch is turned ON (ON), and when the voltage is low, the power switch is not turned (OFF). The boosting module 12 is coupled to the node 111 and has a charging circuit 121, a discharging circuit 122, a voltage clamping circuit 123, and an energy storage component Cgs. The charging circuit 121 and the discharging circuit 122 respectively have a third The transistor Q3 and a fourth transistor Q4, the third transistor A is a p-channel MOSFET element and the fourth transistor & an n-channel M〇SFET element. The operation principle of the invention is: pulse wave control The signal % is supplied to the first transistor Q1 and the second transistor Qz via the inverter for control. In addition, the capacitor 6 and the diode 01 are used as a clamping circuit 113 for clamping voltage, thereby controlling The output voltage vgs is within a predetermined range. Referring to FIG. 3, when the output of the pulse wave control signal Vg is at a low level, the discharge circuit m discharges the energy storage element Cgs; referring to FIG. 4, when the output of the pulse wave control signal vg is at a high level, the charging circuit 121 The double voltage source Vcc charges the energy storage element cgs, so the energy storage element Cgs can alternately generate the double voltage source and the grounded output voltage v in the first mode and the second mode. Gs As shown in Fig. 3, when the pulse control signal vg is at a low level, the second transistor q2 is turned on 'so the energy storage element # Cgs charges i Vcc, and because of the third; the crystal Q3 is at the gate and the source The voltage is 〇V, so that the third transistor is turned off. At the same time, since the voltage of the fourth transistor q4 at the gate and the source is 4 Vcc, the fourth transistor Q4 is turned on, so that the output voltage of the gate driver u is grounded. The storage element Cgs is discharged through the discharge path formed by the fourth transistor Q4 to the second transistor & the output voltage Vgs is the ground voltage. As shown in FIG. 4, when the pulse wave control signal Vg is at a high level, the first transistor Qi is turned on. In addition, the negative terminal voltage of the energy storage element cgs is the voltage source Vcc, and the energy storage element Cgs is positive. The terminal voltage is 2Vcc, which causes the diode a to be deflected. At the same time, since the third transistor A turns on the second transistor Q3 at the gate and the source of the voltage _Vcc, the output voltage of the gate driver n is 2VCC. To this end, the current charges the energy storage element cgs from the first transistor Qi through the third transistor Q3, and the output voltage Vgs is the voltage of the double voltage source 2VCC. In this embodiment, the voltage source Vcc used in the simulation and experiment is 5 volts, and the first transistor Q! and the second transistor Q2 are half-bridge switches of the type MIC442, and the third transistor q3 and The fourth transistor Q4 uses switching elements of the models IRLML5103 and NDS335N, respectively. As shown in FIG. 5, the pulse wave control signal % used in this embodiment is a pulse wave of $ volt, and its output voltage is 1 volt, and is simulated and tested at a switching frequency of 1 kHz, 10 kHz, 100 kHz, and 500 kHz, respectively. As a result, there is a good effect in generating an output voltage of a double voltage source. The above-mentioned power conversion device 1 and method with the boosting capability of the present invention can boost the original voltage source to double output, so that a complicated digital control system such as a servo system can be supplied, and various different voltages are required. Source and reduce the size of the entire system. However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the practice of the present invention, that is, the simple equivalent of the patent application scope and the description of the invention. Variations and modifications are still within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a gate driver of a switching power supply device; FIG. 2 is a circuit diagram showing a preferred embodiment of a power conversion device having positive and negative output voltages according to the present invention; 3 is a circuit diagram illustrating the preferred embodiment. In the first mode, the charging circuit charges the energy storage element with a voltage source; FIG. 4 is a circuit diagram illustrating the discharge circuit of the preferred embodiment in the second mode. The energy storage element is discharged by a voltage source; and FIG. 5 is a waveform diagram illustrating the pulse wave control signal used in the preferred embodiment, which is a 5 volt pulse wave whose output voltage Vgs is 1 volt. ❹ 10 200928659 [Explanation of main component symbols] [Practical] 123 · ...... clamp voltage circuit 9 .......... • gate driver B!..... ...... inverter 91 , 92 · • Power Switch Ci·· ... Capacitor 93......... Inverter Cgs-... Energy Storage Element Vin........ Pulse Control Signal Dr··.. ....Diode Vs ........ Positive power supply Qi ··......First transistor Vout... Positive output voltage Q2... ......Second transistor [this creation] q3··· Second electric day body 1 .......... Power conversion device q4···...... Fourth transistor 11...... Gate driver Vcl··· ...voltage 111 ....... Node VCc " ..... Power supply 12.... Charge and discharge module vg...·... Pulse control signal 121. ...... Charging circuit Vgs··· ••...Output voltage 122....... Discharge circuit❹ 11