TWI513185B - A driving method and a gate driver - Google Patents

Description

Gate driver and driving method

The invention relates to a gate driver and a driving method used in a power switch, in particular to a gate driver and a driving method.

Switching losses are known to play an important role in the total power loss of MOSFET power switches. Since the MOSFET power switch exhibits an impedance characteristic during a transient period of on/off, the higher the switching frequency, the more the loss.

The gate of a MOSFET power switch can generally be regarded as a capacitor. The conventional positive output voltage gate driver for an n-channel MOSFET power switch can only be driven by a positive voltage source, but the gate of the n-channel MOSFET power switch is turned off ( The turn-off period) cannot be driven quickly, thus causing an increase in switching loss.

In order to reduce the aforementioned switching loss, a resonance circuit for a gate driver has been proposed, however, it is easy to increase cost and complexity. Another way is to use the positive output voltage and the negative output voltage to drive the n-channel MOSFET power switch, thereby reducing the off transient period and discharge time of the gate of the n-channel MOSFET power switch. However, this solution requires a positive output voltage source and another negative output voltage source to drive the n-channel MOSFET power supply. Switches are not convenient for industrial applications.

Accordingly, it is an object of the present invention to provide a gate driver and a driving method that meet a simplified design and can be quickly discharged to reduce energy loss.

Therefore, the gate driver of the present invention comprises a driving circuit, a first charge pump, a second charge pump, a third charge pump, a fourth charge pump, a first clamp circuit, and a second Clamping the pump, a first switch and a second switch.

The driving circuit is powered by an input voltage of a positive voltage power supply and has a pair of power switches. The pair of power switches collectively receive a pulse wave control signal and the outputs of the two are connected to a first node, and the pulse wave control signal has a first The mode and a second mode are used to control whether the pair of power switches are turned on or off.

The first charge pump includes a first diode and a first capacitor. The anode end of the first diode is coupled to the input voltage of the positive voltage source, and the cathode end of the first diode is connected in series. One end of a capacitor, the other end of the first capacitor is connected to the first node.

The second charge pump includes a second diode and a second capacitor. One end of the second capacitor is connected to the first node, and the other end of the second capacitor is coupled to the anode end of the second diode. The cathode end of the polar body is grounded.

The third charge pump includes a third diode and a third capacitor. The anode end of the third diode is coupled between the cathode end of the first diode and one end of the first capacitor. The cathode end of the polar body is coupled to the third capacitor At one end, the other end of the third capacitor is grounded.

The fourth charge pump includes a fourth diode and a fourth capacitor, and a cathode end of the fourth diode is coupled between the anode end of the second diode and one end of the second capacitor, and the fourth The anode end of the pole body is coupled to one end of the fourth capacitor, and the other end of the fourth capacitor is grounded.

The first clamping circuit includes a fifth diode and a fifth capacitor. The anode end of the fifth diode is coupled to one end of the third capacitor, and the cathode end of the fifth diode is connected to the fifth capacitor. At one end, the other end of the fifth capacitor is connected to a second node connected to the first node.

The second clamping circuit includes a sixth diode and a sixth capacitor. One end of the sixth capacitor is connected to the second node, and the other end of the sixth capacitor is coupled to the anode end of the sixth diode. The cathode of the body is coupled to one end of the fourth capacitor.

The first switch is a p-channel MOSFET, the gate control end of the first switch is coupled to the anode of the fifth diode, and the source terminal of the first switch is coupled to the fifth Between the cathode end of the diode and one end of the fifth capacitor; and the second switch is an n-channel metal oxide semiconductor field effect transistor component, and the gate control terminal of the second switch is coupled to the sixth diode a cathode end of the body, a source terminal of the second switch is coupled between the other end of the sixth capacitor and an anode end of the sixth diode, and the drain of the first switch and the drain of the second switch are coupled to each other An output terminal, wherein the output terminal is three times the input voltage to the first mode and the input voltage is twice the input voltage in the second mode.

Preferably, the pair of power switches comprises a first transistor and a a second transistor, the first transistor system, a p-channel metal oxide semiconductor field effect transistor device, and the second transistor system, an n-channel metal oxide semiconductor field effect transistor device.

The gate driving method of the present invention comprises the steps of: providing a driving circuit, receiving an input voltage of a positive voltage power supply and having a pair of power switches, the pair of power switches receiving a pulse control signal and the outputs of the two are connected to one a first node, the pulse control signal has a first mode and a second mode to regulate the conduction of the pair of power switches; providing a first charge pump, including a first diode and a first capacitor The anode end of the first diode is coupled to the input voltage of the positive voltage source, the cathode end of the first diode is serially connected to one end of the first capacitor, and the other end of the first capacitor is connected to the first node; The second charge pump includes a second diode and a second capacitor. One end of the second capacitor is connected to the first node, and the other end of the second capacitor is coupled to the anode end of the second diode. The cathode end of the pole body is grounded; a third charge pump is provided, including a third diode and a third capacitor, and an anode end of the third diode is coupled to the cathode end of the first diode and the first Between one end of the capacitor, the third diode The cathode end is coupled to one end of the third capacitor, and the other end of the third capacitor is grounded: a fourth charge pump is provided, including a fourth diode and a fourth capacitor, and the cathode end of the fourth diode is coupled to Between the anode end of the second diode and the end of the second capacitor, the anode end of the fourth diode is coupled to one end of the fourth capacitor, and the other end of the fourth capacitor is grounded; a first clamping circuit is provided, including a a fifth diode and a fifth capacitor, wherein an anode end of the fifth diode is coupled to one end of the third capacitor, and a cathode end of the fifth diode is serially connected to one end of the fifth capacitor The other end of the fifth capacitor is connected to a second node connected to the first node; a second clamping circuit is provided, including a sixth diode and a sixth capacitor, and one end of the sixth capacitor is connected to the second node, The other end of the sixth capacitor is coupled to the anode end of the sixth diode, and the cathode of the sixth diode is coupled to one end of the fourth capacitor; a first switch is provided, and the first switch is a p-channel metal oxide The gate of the first switch is coupled to the anode of the fifth diode, and the source terminal of the first switch is coupled to the cathode terminal of the fifth diode and the fifth capacitor Between one end; and providing a second switch, the second switch is an n-channel metal oxide semiconductor field effect transistor component, and the gate control end of the second switch is coupled to the cathode terminal of the sixth diode The source terminal of the second switch is coupled between the other end of the sixth capacitor and the anode end of the sixth diode, and the drain of the first switch and the drain of the second switch are coupled to an output end, and The first mode is three times the input voltage at the output and in the second mode The output is twice the input voltage is negative.

Preferably, in the first mode, the first transistor is turned on and the second transistor is not turned on, the second diode forward bias and the second capacitor are quickly charged to the positive input voltage, and the input voltage is accompanied by the fourth The voltage of the capacitor charges the sixth capacitor to twice the input voltage, the first diode is reverse biased, and the input voltage is charged to the third capacitor by twice the input voltage with the voltage of the first capacitor. On the other hand, the first switch The voltage between the gate and the source is a negative input voltage, causing the first switch to be turned on, and the voltage between the gate and the source of the second switch is zero, causing the second switch to be non-conducting, so that the output is three times Input voltage; in the second mode, the first transistor is non-conducting and the second transistor is turned on, the first diode and the fifth diode are forward biased and the second diode And the sixth diode is reverse biased to charge the first capacitor to the input voltage, and at the same time, the voltage between the gate and the source of the first switch is zero, causing the first switch to be non-conducting, and the gate of the second switch The voltage between the source and the source is the input voltage, causing the second switch to be turned on, the first capacitor is charged to the input voltage and the third capacitor is charged to twice the input voltage, such that the output is twice the input voltage.

The gate driver and the driving method of the present invention have the effect that the gate driver of the present invention can provide three times and minus twice the input voltage to reduce the switching loss during the on/off shutdown, and conforms to the simplified design and reduces the switching. Loss requirements.

100‧‧‧gate driver

10‧‧‧Drive circuit

11‧‧‧First charge pump

12‧‧‧Second charge pump

13‧‧‧The third charge pump

14‧‧‧The fourth charge pump

21‧‧‧First clamp circuit

22‧‧‧Second clamp circuit

B ₁ ‧‧‧Inverter

C ₁ ‧‧‧first capacitor

C ₂ ‧‧‧second capacitor

C ₃ ‧‧‧third capacitor

C ₄ ‧‧‧fourth capacitor

C ₅ ‧‧‧ fifth capacitor

C ₆ ‧‧‧ sixth capacitor

C _gs ‧‧‧ energy storage components

D ₁ ‧‧‧First Diode

D ₂ ‧‧‧Secondary

D ₃ ‧‧‧third diode

D ₄ ‧‧‧fourth dipole

D ₅ ‧‧‧ fifth dipole

D ₆ ‧‧‧ sixth diode

PWM‧‧‧ pulse wave control signal

Q ₁ ‧‧‧First transistor

Q ₂ ‧‧‧Second transistor

Q ₃ ‧‧‧First switch

Q ₄ ‧‧‧Second switch

V _CC ‧‧‧ input voltage

X1‧‧‧ first node

X2‧‧‧ second node

X3‧‧‧ output

Other features and advantages of the present invention will be apparent from the embodiments of the present invention, wherein: Figure 1 is a circuit diagram illustrating a preferred embodiment of the components of the gate driver of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a circuit diagram showing a preferred embodiment of a gate driver of the present invention in a first mode; FIG. 4 is a circuit diagram; The preferred embodiment of the gate driver of the present invention is in the second mode; FIG. 5 is a timing waveform diagram illustrating the voltage waveform of each component of the preferred embodiment, and the switching frequency is 10 kHz; FIG. 6 is a timing diagram. The waveform diagram illustrates the voltage waveform of each component of the preferred embodiment, and the switching frequency is 500 kHz. FIG. 7 is a timing waveform diagram illustrating the pulse wave control signal PWM of the preferred embodiment of the present invention. The waveform of the voltage v _{C1 of the} capacitor C ₁ , the voltage v _{C5 of the} fifth capacitor C ₅ and the voltage v _C3 of the third capacitor C ₃ ; FIG. 8 is a timing waveform diagram illustrating that the switching frequency of the preferred embodiment is 500 kHz. Pulse wave control The waveform of the signal PWM, the voltage v _{C1 of the} first capacitor C ₁ , the voltage v _{C5 of the} fifth capacitor C ₅ and the voltage v _C3 of the third capacitor C ₃ ; FIG. 9 is a timing waveform diagram illustrating the preferred embodiment The switching frequency is a waveform of the pulse wave control signal PWM of 10 kHz, the first node voltage v _X1 and the energy storage element voltage v _gs ; and FIG. 10 is a timing waveform diagram illustrating that the switching frequency of the preferred embodiment is 500 kHz. The waveform of the wave control signal PWM, the first node voltage v _X1 and the energy storage element voltage v _gs .

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

Referring to FIG. 1 and FIG. 2, in a preferred embodiment of the gate driver 100 and the driving method of the present invention, the gate driver 100 includes a driving circuit 10, a first charge pump 11, and a second charge pump 12. a third charge pump 13, a fourth charge pump 14, a first clamping circuit 21, clamping a second pump 22, a first switch and a second switch Q ₃ Q _4. The preferred embodiment is applied to an n-channel MOSFET switching element (not shown) or other similar power switch, and in the preferred embodiment is a gate that uses an energy storage element _{Cgs to} simulate an n-channel MOSFET switching element. pole.

The driving circuit 10 is powered by an input voltage V _{CC of} a positive voltage source and has an inverter B ₁ and a pair of power switches. The pair of power switches includes a first transistor Q ₁ and a second transistor Q ₂ , A transistor Q ₁ is a p-channel metal oxide semiconductor field effect transistor device, and a second transistor Q ₂ is an n-channel metal oxide semiconductor field effect transistor device. The pair of power switches collectively receive a pulse control signal PWM and the outputs of the two are connected to a first node X1. The pulse control signal PWM is a pulse wave, which may be generated by a wave width modulation or a variable frequency modulation method. a pulse control signal after the phase inverting device B ₁ having a first mode and a second mode of regulation of the power switch turned on or not.

The first charge pump 11 includes a first diode D ₁ and a first capacitor C ₁ . The anode end of the first diode D ₁ is coupled to the input voltage V _{CC of} the positive voltage source, and the first diode D of the female body ₁ is connected in series to the terminal end of the first capacitor C _1, the other end of the first capacitor C ₁ is connected to the first node X1.

The second capacitor 12 includes a second diode D ₂ and a second capacitor C ₂ . One end of the second capacitor C ₂ is connected to the first node X1 , and the other end of the second capacitor C ₂ is coupled to the second node ₂ . The anode end of the body D _{2 and} the cathode end of the second diode D ₂ are grounded.

The third charge pump 13 includes a third diode D ₃ and a third capacitor C ₃ . The anode end of the third diode D ₃ is coupled to the cathode terminal of the first diode D ₁ and the first capacitor. _{C. 1} between one end of the third diode D ₃ a cathode terminal coupled to the third capacitance C ₃ at one end, other end of the third capacitor C _3.

The fourth charge pump 14 includes a fourth diode D ₄ and a fourth capacitor C ₄ . The cathode end of the fourth diode D ₄ is coupled to the anode terminal of the second diode D ₂ and the second capacitor. C ₂ between one end of the fourth diode D ₄ is coupled to the anode terminal at an end of the fourth capacitor C _4, the fourth capacitor C ₄ to the other end.

A first clamping circuit 21 comprises a fifth diode D _5, and a fifth capacitor C _5, a fifth diode D the anode terminal ₅ is coupled to one end of a third capacitor C _3, the fifth diode D ₅ a cathode terminal connected in series with one end of the fifth capacitor C ₅ and the other end connected to the fifth capacitor C ₅ is connected to a second node X2 of the first node X1.

The second clamping circuit 22 includes a sixth diode D ₆ and a sixth capacitor C ₆ . One end of the sixth capacitor C ₆ is connected to the second node X 2 , and the other end of the sixth capacitor C ₆ is coupled to the sixth diode. D anode terminal member ₆ and the sixth diode cathode of D ₆ is coupled to one end of the fourth capacitor C ₄ of.

The first switch Q ₃ is a p-channel MOSFET, the gate control terminal of the first switch Q ₃ is coupled to the anode of the fifth diode D ₅ , and the first switch Q ₃ The source terminal is coupled between the cathode terminal of the fifth diode D ₅ and one end of the fifth capacitor C ₅ ; the second switch Q ₄ is an n-channel metal oxide semiconductor field effect transistor component, and the second switch Q the gate electrode ₄ controls the sixth terminal coupled to the cathode terminal of diode D _6, the source terminal of the second switch Q ₄ is coupled to the other end of the male terminal of the sixth capacitor C ₆ and the sixth diode D ₆ The drain of the first switch Q _{3 and} the drain of the second switch Q ₄ are both coupled to an output terminal X3, and the output terminal X3 is three times the input voltage to the first mode and the second mode is The input voltage is twice the input voltage, whereby the gate of the n-channel MOSFET switching element (represented by the energy storage element C _gs ) can be driven.

Referring to FIG. 1, with reference to FIG. 3 and FIG. 4, how the two control modes of the gate driver 100 operate will be described below. It should be noted that this embodiment assumes that the feedforward voltage for all diodes is 0, first. C value of the capacitance _C1 of the voltage v ₁ and v ₂ of the second capacitor _C2 of the voltage C are close to the input voltage (V _CC), a third voltage v ₃ of the capacitor C _C3, a fifth capacitor _C5 of the voltage v C ₅ and the sixth The value of the voltage v _C6 of the capacitor C ₆ is close to twice the input voltage (2V _CC ), and the value of the voltage v _C4 of the fourth capacitor C ₄ is close to the negative input voltage (-V _CC ).

In the first mode, the first transistor Q _{1 is} turned on and the second transistor Q _{2 is} not turned on, the second diode D ₂ forward bias and the second capacitor C _{2 are} quickly charged to the positive input voltage V _CC , and The input voltage V _{CC is} charged to the sixth capacitor C ₆ to twice the input voltage 2V _CC with the voltage of the fourth capacitor C ₄ , the first diode D _{1 is} reverse biased, and the input voltage V _{CC is} accompanied by the voltage of the first capacitor C ₁ . Charging the third capacitor C ₃ to twice the input voltage 2V _CC , and on the other hand, the voltage between the gate and the source of the first switch Q ₃ is a negative input voltage -V _CC , causing the first switch Q _{3 to be} turned on, Q voltage between the gate and the source of the second switch ₄ is zero, resulting in the second switch Q ₄ is not conducting, so that the output is three times the input voltage 3V _CC.

In the second mode, the first transistor Q _{1 is} non-conducting and the second transistor Q _{2 is} turned on, the first diode D ₂ and the fifth diode D _{5 are} forward biased and the second diode D ₂ and a sixth diode D ₆ reverse biased, the first capacitor C ₁ is charged to the input voltage V _CC, while the voltage between the gate and the source of Q ₃ of the first switch is zero, resulting in a first switch Q ₃ Non-conducting, the voltage between the gate and the source of the second switch Q ₄ is the input voltage V _CC , causing the second switch Q _{4 to be} turned on, and the first capacitor C _{1 is} charged to the input voltage V _CC and the third capacitor C _{3 is} charged. Up to twice the input voltage of 2V _CC , so that the output is twice the input voltage -2V _CC .

Based on the above description, it can be seen that the gate driver 100 can be The first mode and the second mode respectively generate three times and twice the input voltage.

The conditions used in the simulation and experiment in this embodiment are as follows: (i) the power supply voltage V _CC is +5 volts; (ii) the first capacitor C ₁ , the second capacitor C ₂ , the third capacitor C _{3 ,} and the fourth capacitor C ₄ The capacitance values are all set to 10 μF; (iii) the capacitance values of the fifth capacitor C ₅ and the sixth capacitor C ₆ are set to 1 μF; (iv) the capacitance of the analog gate capacitance C _gs is set to 22 nF; (v) A transistor Q ₁ and a second transistor Q ₂ adopt an output buffer switch of the model IXDD614P; (vi) the first switch Q ₃ and the second switch Q ₄ adopt an integrated circuit of the model FDS8333C, which includes N-channel and p-channel metal oxide semiconductor field effect transistors; (vii) Dipoles D ₁ ~ D ₆ are integrated circuits using Model 1N5819.

Referring to FIG. 2, FIG. 5 and FIG. 6, the voltage waveforms of the respective elements under the above-described conditions using the gate driver 100 of FIG. 1 are switched at frequencies of 10 kHz and 500 kHz, respectively.

2 and FIG. 7 are waveforms of the pulse wave control signal PWM whose switching frequency is 10 kHz, the voltage v _{C1 of the} first capacitor C ₁ , the voltage v _{C5 of the} fifth capacitor C ₅ , and the voltage v _C3 of the third capacitor C ₃ .

2 and FIG. 8 are waveforms of the pulse wave control signal PWM whose switching frequency is 500 kHz, the voltage v _{C1 of the} first capacitor C ₁ , the voltage v _{C5 of the} fifth capacitor C ₅ , and the voltage v _C3 of the third capacitor C ₃ .

2 and FIG. 9 are waveforms of the pulse wave control signal PWM whose switching frequency is 10 kHz, the voltage v _{X1 of the} first node X1, and the voltage v _gs of the energy storage element C _gs .

2 and FIG. 10 are waveforms of the pulse wave control signal PWM whose switching frequency is 500 kHz, the voltage v _{X1 of the} first node X1, and the voltage v _gs of the energy storage element C _gs .

In summary, in the gate driver 100 and the driving method of the present invention, only a single positive voltage power supply (input voltage Vcc) is required to supply power, and intermittently generate three times (3Vcc) including the output voltage Vcc and a negative double of the output voltage (- The drive signal v _{gs of} 2Vcc) drives the gate of the n-channel MOSFET switching element (this embodiment is represented by the energy storage element C _gs ). Therefore, the gate driver 100 can reduce the transient period and thus reduce the switching loss. In addition, since the aforementioned voltages (3Vcc and -2Vcc) are applied to the gate of the n-channel MOSFET switching element (this embodiment is represented by the energy storage element _Cgs ), in addition to the error of the Miller effect being reduced, the leakage current is also The gate driver 100 of the present invention is reduced in accordance with the simplified design of the overall circuit and has a fast action to reduce the switching loss, so that the object of the present invention can be achieved.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent changes and modifications made by the patent application scope and patent specification content of the present invention, All remain within the scope of the invention patent.

100‧‧‧gate driver

10‧‧‧Drive circuit

11‧‧‧First charge pump

12‧‧‧Second charge pump

13‧‧‧The third charge pump

14‧‧‧The fourth charge pump

21‧‧‧First clamp circuit

22‧‧‧Second clamp circuit

B ₁ ‧‧‧Inverter

C ₁ ‧‧‧first capacitor

C ₂ ‧‧‧second capacitor

C ₃ ‧‧‧third capacitor

C ₄ ‧‧‧fourth capacitor

C ₅ ‧‧‧ fifth capacitor

C ₆ ‧‧‧ sixth capacitor

C _gs ‧‧‧ energy storage components

D ₁ ‧‧‧First Diode

D ₂ ‧‧‧Secondary

D ₃ ‧‧‧third diode

D ₄ ‧‧‧fourth dipole

D ₅ ‧‧‧ fifth dipole

D ₆ ‧‧‧ sixth diode

PWM‧‧‧ pulse wave control signal

Q ₁ ‧‧‧First transistor

Q ₂ ‧‧‧Second transistor

Q ₃ ‧‧‧First switch

Q ₄ ‧‧‧Second switch

V _CC ‧‧‧ input voltage

X1‧‧‧ first node

X2‧‧‧ second node

X3‧‧‧ output

Claims (4)

A gate driver includes: a driving circuit that receives an input voltage of a positive voltage power supply and has a pair of power switches, the pair of power switches receiving a pulse control signal and the outputs of the two are connected to a first node, The pulse wave control signal has a first mode and a second mode to control whether the pair of power switches are turned on or not; a first charge pump comprising a first diode and a first capacitor, the first diode The anode end is coupled to the input voltage of the positive voltage source, the cathode end of the first diode is connected in series with one end of the first capacitor, and the other end of the first capacitor is connected to the first node; a second charge pump includes a second diode and a second capacitor, one end of the second capacitor is connected to the first node, the other end of the second capacitor is coupled to the anode end of the second diode, and the cathode end of the second diode is grounded; a third charge pump includes a third diode and a third capacitor, and an anode end of the third diode is coupled between the cathode end of the first diode and one end of the first capacitor, and the third The cathode end of the diode is coupled to the third capacitor end The other end of the third capacitor is grounded; a fourth charge pump includes a fourth diode and a fourth capacitor, and a cathode end of the fourth diode is coupled to the anode end of the second diode and the second Between one end of the capacitor, the anode end of the fourth diode is coupled to one end of the fourth capacitor, and the other end of the fourth capacitor is grounded; a first clamping circuit includes a fifth diode and a fifth The anode end of the fifth diode is coupled to one end of the third capacitor, the cathode end of the fifth diode is connected in series to one end of the fifth capacitor, and the other end of the fifth capacitor is connected to the first node. a second node connected to the second node; a second clamping circuit comprising a sixth diode and a sixth capacitor; one end of the sixth capacitor is connected to the second node, and the other end of the sixth capacitor is coupled to the sixth diode The anode end of the sixth diode is coupled to one end of the fourth capacitor; a first switch, the first switch is a p-channel metal oxide semiconductor field effect transistor component, and the gate of the first switch is controlled The terminal is coupled to the anode of the fifth diode, the source terminal of the first switch is coupled between the cathode end of the fifth diode and the end of the fifth capacitor; and a second switch, the second switch is a The n-channel metal oxide semiconductor field effect transistor component, the gate control end of the second switch is coupled to the cathode end of the sixth diode, and the source terminal of the second switch is coupled to the other end of the sixth capacitor and Between the anode ends of the hexadiodes, the drain of the first switch and the 第二 of the second switch It is coupled to an output terminal, and the output terminal in the first mode and three times the input voltage to the negative second mode is twice the input voltage. The gate driver of claim 1, wherein the pair of power switches comprises a first transistor and a second transistor, the first transistor system is a p-channel metal oxide semiconductor field effect transistor component, The second electro-crystalline system is an n-channel metal oxide semiconductor field effect transistor element. A gate driving method includes the steps of: providing a driving circuit, receiving an input voltage of a positive voltage power supply and having a pair of power switches, the pair of power switches receiving a pulse wave control signal and the outputs of the two are connected to one a first node, the pulse control signal has a first mode and a second mode to regulate the conduction of the pair of power switches; providing a first charge pump, including a first diode and a first capacitor The anode end of the first diode is coupled to the input voltage of the positive voltage source, the cathode end of the first diode is serially connected to one end of the first capacitor, and the other end of the first capacitor is connected to the first node; The second charge pump includes a second diode and a second capacitor. One end of the second capacitor is connected to the first node, and the other end of the second capacitor is coupled to the anode end of the second diode. The cathode end of the pole body is grounded; a third charge pump is provided, including a third diode and a third capacitor, and an anode end of the third diode is coupled to the cathode end of the first diode and the first Between one end of the capacitor, the third diode The cathode end is coupled to one end of the third capacitor, and the other end of the third capacitor is grounded; a fourth charge pump is provided, including a fourth diode and a fourth capacitor, and the cathode end of the fourth diode is coupled to Between the anode end of the second diode and the end of the second capacitor, the anode end of the fourth diode is coupled to one end of the fourth capacitor, and the other end of the fourth capacitor is grounded; a first clamping circuit is provided, including a a fifth diode and a fifth capacitor, wherein an anode end of the fifth diode is coupled to the third capacitor One end, the cathode end of the fifth diode is connected in series with one end of the fifth capacitor, the other end of the fifth capacitor is connected to a second node connected to the first node; and a second clamping circuit is provided, including a sixth a diode and a sixth capacitor, one end of the sixth capacitor is connected to the second node, the other end of the sixth capacitor is coupled to the anode end of the sixth diode, and the cathode of the sixth diode is coupled to the fourth capacitor a first switch, the first switch is a p-channel metal oxide semiconductor field effect transistor device, the gate control end of the first switch is coupled to the anode of the fifth diode, the first switch The source terminal is coupled between the cathode end of the fifth diode and one end of the fifth capacitor; and provides a second switch, the second switch is an n-channel metal oxide semiconductor field effect transistor component, and the second The gate control end of the switch is coupled to the cathode end of the sixth diode, and the source terminal of the second switch is coupled between the other end of the sixth capacitor and the anode end of the sixth diode. The poles of the pole and the second switch are all coupled to an output end, and in the Mode three times at the output terminal of the input voltage and the negative second mode is twice the input voltage to the output terminal. The gate driving method of claim 3, wherein in the first mode, the first transistor is turned on and the second transistor is not turned on, and the second diode forward bias and the second capacitor are quickly charged to positive Input voltage, at the same time, the input voltage is accompanied by the voltage of the fourth capacitor Charging the sixth capacitor to twice the input voltage, the first diode is reverse biased, the input voltage is charged to the third capacitor to twice the input voltage with the voltage of the first capacitor, and the gate of the first switch is The voltage between the source is a negative input voltage, causing the first switch to be turned on, and the voltage between the gate and the source of the second switch is zero, causing the second switch to be non-conducting, so that the output terminal is three times the input voltage; And in the second mode, the first transistor is non-conducting and the second transistor is turned on, the first diode and the fifth diode are forward biased, and the second diode and the sixth diode are reverse biased. , the first capacitor is charged to the input voltage, and the voltage between the gate and the source of the first switch is zero, causing the first switch to be non-conducting, and the voltage between the gate and the source of the second switch is an input The voltage causes the second switch to be turned on, the first capacitor is charged to the input voltage and the third capacitor is charged to twice the input voltage such that the output is twice the input voltage.