TWI832316B - Drivers that reduce power consumption of capacitive loads - Google Patents

Abstract

The present invention provides a driver that reduces power consumption of capacitive loads, including at least one driving signal output An input terminal, a controller, a switching circuit, a first impedance component and a voltage output terminal. The controller receives an input signal from the at least one drive signal input terminal, and the controller generates at least one control signal based on the input signal. to the switching circuit to control the switching circuit, the first impedance component and the voltage output end to form an energy storage circuit and an energy recovery circuit. Through the design of the first impedance component, the energy storage circuit and the energy are formed. recycling loop to achieve the purpose of improving the overall power conversion efficiency.

Description

Drivers that reduce power consumption of capacitive loads

The present invention relates to a driver, in particular to a driver that reduces power consumption of capacitive loads.

In order to improve the power conversion efficiency between input and output, the switching power conversion device in the prior art designs a switching circuit and makes the switching switch in the switching circuit operate at a high frequency for switching control to form a power output loop.

Currently, common high-frequency switching switches on the market use Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The control unit of the switching power conversion device outputs a control signal to the MOSFET to drive the MOSFET. Switch on or off, taking flyback converters as an example. When the MOSFET is on, the voltage passes through the MOSFET to store energy in the inductor. When the MOSFET is off, the inductor transfers the stored energy to the next stage. circuit.

However, since the gate of the MOSFET has a parasitic capacitance, when the control signal controls the MOSFET to turn on and causes the inductor to store energy, the control signal also causes the parasitic capacitance to store energy, and the energy of the parasitic capacitance is usually reduced by power consumption. , especially under high-frequency operation of MOSFET, when the operating frequency increases, the power consumption also increases, which will reduce the power conversion efficiency of the switching power conversion device.

In view of the above-mentioned shortcomings of the prior art, the main purpose of the present invention is to provide a driver that reduces the power consumption of a capacitive load and recovers energy through inductor energy storage to improve the overall power conversion efficiency of the switching power conversion device.

The main technical means adopted to achieve the above purpose is to provide the aforementioned driver for reducing the power consumption of capacitive loads, including: at least one driving signal input terminal; a controller connected to the at least one driving signal input terminal; and a switching circuit, It includes at least one switch control signal input pin, a first power input pin, a second power input pin, a first power output pin and a second power output pin, and the at least one switch control signal The input pin is connected to the controller; a first impedance component, one pin of which is connected to the first power output pin; a voltage output terminal, which is connected to the other pin of the first impedance component and with the The second power output pin is connected; wherein, the controller receives an input signal from the at least one driving signal input terminal and generates at least one control signal to drive the switching circuit so that the switching circuit communicates with the first impedance component and the The voltage output terminal forms an energy storage loop and an energy recovery loop.

Through the above structure, the driver for reducing capacitive load power consumption outputs at least one control signal to the switch circuit through the controller according to an input signal to control the switch circuit, the first impedance component and the voltage output end to form a storage energy loop and an energy recovery loop.

10:Controller

101: Timing circuit

102:Detection circuit

11: Switch circuit

12:First impedance piece

13:Load

14:Second impedance piece

15: The third impedance component

L1: first inductor

L2: Second inductor

D1: first diode

D2: Second diode

SW1: first switch

SW2: Second switch

SW3: The third switch

SW4: The fourth switch

BD1~BD4: Internal diodes

G _IN : drive signal input terminal

V _out : voltage output terminal

V _CC : first power input pin

GND: Second power input pin

Setting: Another drive signal input terminal

t: time

t11~t14,t21~t24: time point

Control: control signal

Detect: detect signal

FIG. 1 is a schematic diagram of a driver for reducing capacitive load power consumption according to the first embodiment of the present invention.

FIG. 2 is a schematic diagram of a driver for reducing capacitive load power consumption according to another embodiment of the present invention.

FIG. 3 is a schematic diagram of another embodiment of a driver for reducing capacitive load power consumption according to the present invention.

FIG. 4 is a schematic diagram of a driver for reducing capacitive load power consumption according to another embodiment of the present invention.

FIG. 5 is a schematic diagram of a driver for reducing capacitive load power consumption according to another embodiment of the present invention.

Figure 6 is a schematic diagram of the switching circuit of the driver for reducing capacitive load power consumption according to the present invention.

Figure 7 is a schematic diagram of a controller of a driver for reducing capacitive load power consumption according to the present invention.

FIG. 8 is a timing diagram of the first switch to the fourth switch control of the present invention.

FIG. 9 is another timing diagram of the first switch to the fourth switch control of the present invention.

Regarding the first embodiment of the driver for reducing capacitive load power consumption of the present invention, as shown in Figure 1, it includes at least one driving signal input terminal G _IN , a controller 10, a switching circuit 11, a first impedance element 12 and A voltage output terminal V _out . The at least one driving signal input terminal G _IN is electrically connected to the controller 10. Then, the controller 10 is further electrically connected to the switch circuit 11. Subsequently, the switch circuit 11 is connected to the third power supply output pin via two power output pins. An impedance element 12 is connected to form the voltage output terminal V _out , and the voltage output terminal V _out is electrically connected to a load 13 to provide power to the load 13 .

Specifically, in this embodiment, the switch circuit 11 includes at least one switch control signal input pin, a first power input pin V _CC , a second power input pin GND, and a first power output pin. and a second power output pin. The at least one switch control signal input pin is electrically connected to the controller 10 to receive at least one control signal from the controller 10. Then, one of the first impedance components 12 is connected The voltage output terminal V _out is electrically connected to the other pin of the first impedance component 12 and is connected to the second power output pin.

When the controller 10 receives an input signal from the at least one drive signal input terminal G _IN , it will generate the at least one control signal and transmit the at least one control signal to the switch circuit 11. The switch circuit 11 will The at least one control signal is activated to connect the first power input pin V _CC , the second power input pin GND, the first power output pin and the second power output pin to the first impedance element 12 , The voltage output terminal V _out and the load 13 form an energy storage loop and an energy recovery loop. In this embodiment, the voltage output terminal V _out is electrically connected to a load 13 , and the load 13 is a capacitive load.

In this embodiment, the input signal transmitted by the driving signal input terminal G _IN can be an action signal for driving the switch circuit 11, and the at least one driving signal input terminal can further include another driving signal input terminal Setting, by The other driving signal input terminal Setting receives another input signal to set the working mode and working parameters of the controller 10 (such as dead time interval), etc.

Furthermore, in another embodiment of the driver for reducing power consumption of capacitive loads according to the present invention, as shown in Figure 2, the driver for reducing power consumption of capacitive loads according to the present invention further includes a second impedance component 14, and the second power output pin is connected through The second impedance component 14 is electrically connected to the voltage output terminal V _out .

Next, there is another embodiment of the driver for reducing the power consumption of the capacitive load of the present invention. As shown in Figure 3, the driver of the present invention for reducing the power consumption of the capacitive load further includes a third impedance component 15. One of the third impedance components 15 is connected to One pin is electrically connected to the first power output pin and the other pin is electrically connected to the voltage output terminal V _out .

In the above embodiment, the first impedance element 12 and the third impedance element 15 can be an inductor, and the second impedance element 14 can be a resistor or an inductor. In this embodiment, the inductor or the resistor can be The equivalent method is to achieve the effect of an inductor or a resistor through the traces on the circuit board.

In the above embodiment, the first impedance element 12 cooperates with the second impedance element 14 and the third impedance element 15, so that during the charging process of the load 13 and the discharging process of the load 13, it is possible to Because of the design of the aforementioned impedance component, an appropriate charge and discharge rate is provided.

As shown in FIG. 4 , in this embodiment, the first impedance component 12 further includes a first inductor L1 and a first diode D1. After the first inductor L1 and the first diode D1 are connected in series, the first impedance element 12 is formed. Then, the first impedance element 12 is further connected to the first power output pin and the voltage output terminal V _out respectively. Electrical connection. Specifically, a pin of the first inductor L1 is electrically connected to a pin of the first diode D1, and the other pin of the first inductor L1 is electrically connected to the voltage output terminal V _out . , the other pin of the first diode D1 is electrically connected to the first power output pin.

As shown in FIG. 5 , in this embodiment, the third impedance component 15 further includes a second inductor L2 and a second diode D2. The second inductor L2 and the second diode D2 are connected in series, and the first diode D1 and the second diode D2 are in opposite directions to each other. Specifically, one pin of the second inductor L2 is electrically connected to one pin of the second diode D2, and the other pin of the second inductor L2 is electrically connected to the voltage output terminal V _out . , the other pin of the second diode D2 is electrically connected to the first power output pin, and the first diode D1 and the second diode D2 are in opposite directions to each other, for example, When the cathode of the first diode D1 is electrically connected to the first power output pin, the anode of the second diode D2 is electrically connected to the first power output pin, so that the first diode D1 and the second polar body D2 can be in opposite directions.

As shown in Figure 6, in the above embodiment, the switch circuit 11 further includes a first switch SW1, a second switch SW2, a third switch SW3 and a fourth switch SW4, and the first switch SW1, the The second switch SW2, the third switch SW3 and the fourth switch SW4 each include a first pin and a second pin. The first pins of the first switch SW1 and the third switch SW3 are respectively connected to the first pin. The first power input pin is electrically connected, and the second pins of the first switch SW1 and the third switch SW3 are electrically connected to the first pins of the second switch SW2 and the fourth switch SW4 respectively. , and the first pins of the second switch SW2 and the fourth switch SW4 respectively correspond to the first power output pin and the second power output pin, and the second switch SW2 and the fourth switch SW4 The second pins are each electrically connected to the second power input pin. Subsequently, the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 receive signals from the controller 10 respectively. The at least one control signal responds to the at least one control signal by switching the switch on or off, so that the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 can With the first power input pin V _CC , the second power input pin GND, the first power output pin, the second power output pin, the first impedance component 12 , the voltage output terminal V _out and The load 13 forms the energy storage loop or the energy recovery loop.

For example, taking NMOS switches as an example, the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 can be field-effect transistors (Field-Effect Transistor, FET). A switch SW1 includes a first gate, a first drain and a first source, the second switch SW2 includes a second gate, a second drain and a second source, and the third switch SW3 includes a third gate, a third drain and a third source, and the fourth switch SW4 includes a fourth gate, a fourth drain and a fourth source. In this embodiment, The first drain to the fourth drain are the first pins of the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4, and the first source to the The fourth source is the second pin of the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4.

In the above embodiment, the first switch SW1 to the fourth switch SW4 may be a field effect transistor, a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor. Crystal (Insulated Gate Bipolar Transistor, IGBT), in this embodiment, each of the switches further includes internal diodes (BD1 to BD4) for forward conduction operation.

As shown in FIG. 7 , in the above embodiment, the controller 10 further includes a timing circuit 101 , and the timing circuit 101 is electrically connected to the switch circuit 11 . When the controller 10 receives the at least one input signal from the at least one driving signal input terminal G _IN , it transmits the input signal to the timing circuit 101. Then, the timing circuit 101 sets the at least one control signal at a predetermined interval. After a set time, the at least one control signal is sent to the switch circuit 11 .

In this embodiment, the timing circuit 101 can generate a charging or discharging waveform through an RC circuit by dividing the at least one control signal by a preset time, so as to determine the output of the at least one control signal according to the input signal and the waveform. time, or charging or discharging the capacitor through a certain current to generate a sawtooth wave, so as to determine the output time of the at least one control signal based on the input signal and a sawtooth wave input signal, or to preset the at least one control signal through a digital counter. The trigger number is used to determine the output time of the at least one control signal, or the propagation delay time (Propagation Delay Time) of the logic circuit, so that the at least one control signal passes through one or more logic gates. The output time is controlled.

Then, the controller 10 further includes a detection circuit 102. The detection circuit 102 is electrically connected to the voltage output terminal V _out to detect the voltage of the voltage output terminal V out, so that the detection circuit 102 can detect the voltage at the voltage output terminal V _out . The voltage of the voltage output terminal V _out determines the output time of the at least one control signal output by the controller 10 . For example, when the detection circuit 102 detects that the voltage of the voltage output terminal V _out is 1/2 times the voltage between the first power input pin V _CC and the second power input pin GND, that is, When the voltage is 1/2 times Vcc, the controller 10 outputs the at least one control signal to the switch circuit 11 . In this embodiment, the detection circuit 102 can be a voltage comparator. In this embodiment, when the detection circuit 102 detects 1/2 times Vcc, the 1/2 times is only an example and does not limit the case. It can also be 1/5 times to 4/5. The Vcc between times is used as the basis for subsequent output of the at least one control signal.

Furthermore, please refer to FIG. 7 and FIG. 8 together. FIG. 8 is a timing diagram of the first switch to the fourth switch control according to the embodiment of the present invention. The controller 10 will respectively transmit the at least one control signal to the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 according to the input signal to respectively control the first switch SW1 to The fourth switch SW4.

Specifically, first, when the controller 10 has not sent the at least one control signal Control to the switch circuit 11 (that is, before time point t11), the first switch SW1, the second switch SW2 and the third switch SW3 is the switch off, and the fourth switch SW4 is the switch on.

First, the load 13 performs a charging process: at time point t11: after the controller 10 receives the input signal as a rising edge trigger signal from the drive signal input terminal G _IN , it generates the at least one control signal Control according to the input signal.

At time point t12: the controller 10 transmits the at least one control signal Control to the first switch SW1 and the fourth switch SW4, and the first switch SW1 and the fourth switch SW4 each respond to the at least one control signal Control. , the first switch SW1 changes from switch-off to switch-on, and the fourth switch SW4 changes from switch-on to switch-off. At this time, the first power input pin _Vcc passes through the first switch SW1, the first The power output pin, the first impedance component 12, the voltage output terminal V _out , the load 13 and the second power input pin GND form the energy storage circuit, that is, the first power input pin V _cc outputs a voltage to When the load 13 is applied, the first impedance component 12 is also allowed to store energy.

At time point t13: When the controller 10 receives the input signal at time point t11, it simultaneously transmits the input signal to the timing circuit 101. The timing circuit 101 responds to at least one signal after a preset time interval based on the input signal. A control signal Control transition output is a falling edge signal. The first switch SW1 changes from switch on to switch off according to the at least one control signal Control, and the third switch SW3 switches from the switch on according to the at least one control signal Control. The switch turns off and turns on. At this time, the first impedance component 12 outputs the stored electric energy to the load 13. When the electric energy stored in the first impedance component 12 is not enough to meet the voltage of the load 13 (approximately equal to Vcc ), the first power input pin V _cc will output a voltage to the load 13 via the third switch SW3, the second power output pin, and the voltage output terminal V _out . If the electric energy stored in the first impedance element 12 has met the voltage of the load 13, the electric energy stored in the first impedance element 12 will be recharged to the first power input pin Vcc through the third switch SW3. Power supply capacitor.

Then, the load 13 performs a discharge process: at time point t21, when the controller 10 receives that the input signal is a falling edge trigger signal, it generates the at least one control signal Control according to the falling edge signal, and converts the at least one control signal Control It turns into a rising edge signal.

At time point t22: the controller 10 transmits the at least one control signal Control to the second switch SW2 and the third switch SW3, so that the second switch SW2 changes from switch off to switch according to the at least one control signal Control. is turned on, and the third switch SW3 is switched from switch on to switch off. At this time, the load 13, the first impedance element 12, the second switch SW2 and the second power input pin GND form a voltage loop, so that the The electrical energy stored in the load 13 is output to the first impedance component 12 for storage. At time point t23: When the controller 10 receives the input signal at time point t21, it simultaneously transmits the input signal to the timing circuit 101. The timing circuit 101 responds to at least one signal after the preset time interval based on the input signal. A control signal Control is output as a falling edge signal and is transmitted to the second switch SW2 and the fourth switch SW4, so that the second switch SW2 is switched to switch-off according to the at least one control signal Control, and the fourth switch SW4 is switched to switch conduction. At this time, the first impedance element 12 causes a fixed freewheeling direction of the current due to its inductance characteristics, and then the electrical energy stored in the first impedance element 12 passes through the internal diode of the first switch SW1 The body BD1 outputs the power capacitor to the first power input pin Vcc.

Further, please refer to FIG. 7 and FIG. 9 together. FIG. 9 is another timing diagram of the first switch to the fourth switch control of the present invention. First, when the controller 10 has not sent the at least one control signal Control to the switch circuit 11 (that is, before the time point t11), the first switch SW1, the second switch SW2 and the third switch SW3 are switched off, and The fourth switch SW4 is turned on, and the detection circuit 102 further generates the at least one control signal Control according to the input signal and the detection signal Detect.

First, the load 13 performs a charging process: at time point t11: after the controller 10 receives the input signal as a rising edge trigger signal from the drive signal input terminal G _IN , it generates the at least one control signal Control according to the input signal.

At time point t12: the controller 10 transmits the at least one control signal Control to the first switch SW1 and the fourth switch SW4, and the first switch SW1 and the fourth switch SW4 each respond to the at least one control signal Control. , the first switch SW1 changes from switch-off to switch-on, and the fourth switch SW4 changes from switch-on to switch-off. At this time, the first power input pin _Vcc passes through the first switch SW1, the first The power output pin, the first impedance component 12, the voltage output terminal V _out , the load 13 and the second power input pin GND form the energy storage circuit, that is, the first power input pin V _cc outputs a voltage to When the load 13 is applied, the first impedance component 12 is also allowed to store energy.

At time point t13: after receiving a feedback voltage from the voltage output terminal V _out , the detection circuit 102 of the controller 10 generates the detection signal Detect according to the comparison between the feedback voltage and a preset voltage. According to the detection signal Detect, the transition output of the at least one control signal Control is a falling edge signal. The first switch SW1 changes from the switch on to the switch off according to the at least one control signal Control. At this time, the first impedance The electrical energy stored in the component 12 will be output to the load 13 via the internal diode BD2 of the second switch SW2. At time point t14, the controller 10 transmits the at least one control signal Control to the third switch SW3. The third switch SW3 changes from the switch off to the switch on according to the at least one control signal Control. At this time, the third switch SW3 The first power input pin Vcc can continuously output voltage to the load 13 through the third switch SW3, the second power output pin, and the voltage output terminal V _out .

Then, the load 13 performs a discharge process: at time point t21: when the controller 10 receives that the input signal is a falling edge signal, it changes the at least one control signal Control to a rising edge signal.

At time point t22: the controller 10 transmits the at least one control signal Control to the second switch SW2 and the third switch SW3, so that the second switch SW2 changes from switch off to switch according to the at least one control signal Control. is turned on, and the third switch SW3 is switched from switch on to switch off. At this time, the load 13 will form a loop through the first impedance element 12, the second switch SW2 and the second power input pin GND, so that the The electrical energy stored in the load 13 stores energy in the first impedance component 12 .

At time point t23: after the detection circuit 102 receives the feedback voltage from the voltage output terminal V _out , and compares the feedback voltage with the preset voltage, if the voltage drops to 1/2 of Vcc, The detection signal Detect is generated. According to the detection signal Detect, the at least one control signal Control transition is output as a falling edge signal and transmitted to the second switch SW2, so that the second switch SW2 is switched to switch-off. At this time , the electric energy of the first impedance element 12 is output to the power capacitor of the first power input pin V _cc through the internal diode BD1 of the first switch SW1. Finally, at time point t24, the fourth switch SW4 changes from switch off to switch on according to the at least one control signal Control, and the voltage output terminal V _out will communicate with the fourth switch SW4 and the second power input pin. GND is connected, so that the voltage output terminal V _out is output according to the second power input pin GND.

To sum up, through the driver of the present invention that reduces the power consumption of a capacitive load, during the charging process of the load 13, the load 13 is first charged through the first impedance element 12, and at the same time, the first impedance element 12 Electric energy is also stored, and then the first impedance element 12 provides the stored electric energy to the load 13 for charging. During the process of discharging the load 13, the second power input pin GND is first discharged through the first impedance element 12, and at the same time, the electric energy stored in the load 13 is output to the first impedance element 12. The first impedance element 12 thus stores electrical energy, and then the first impedance element 12 outputs the stored electrical energy to the power capacitor. In this way, the purpose of improving the overall power conversion efficiency is achieved.

The above embodiments are only illustrative of the present invention and are not intended to limit the present invention. Anyone skilled in the art can make modifications and changes to the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the rights of the present invention should be as set out in the patent application scope described below.

10:Controller

11: Switch circuit

12:First impedance piece

13:Load

G _IN : drive signal input terminal

V _out : voltage output terminal

V _CC : first power input pin

GND: Second power input pin

Setting: Another drive signal input terminal

Claims (9)

A driver that reduces power consumption of capacitive loads includes: at least one drive signal input terminal; a controller connected to the at least one drive signal input terminal; a switch circuit including at least one switch control signal input pin, a first A power input pin, a second power input pin, a first power output pin and a second power output pin, and the at least one switch control signal input pin is connected to the controller; a first impedance component, one pin of which is connected to the first power output pin; and a voltage output terminal, which is connected to the other pin of the first impedance component and connected to the second power output pin; wherein, the control The device receives an input signal from the at least one driving signal input terminal and generates at least one control signal to drive the switching circuit, so that the switching circuit, the first impedance component and the voltage output terminal form an energy storage loop and an energy recovery Loop, wherein the driver for reducing capacitive load power consumption further includes: a second impedance component; wherein the second power output pin is connected to the voltage output end via the second impedance component. The driver for reducing power consumption of capacitive loads as described in claim 1, wherein the driver for reducing power consumption of capacitive loads further includes: a third impedance component, one pin of which is connected to the first power output pin and the other pin is connected to the voltage output. The driver for reducing power consumption of capacitive loads as described in claim 1, wherein the first impedance element and the second impedance element can each be an inductor. The driver for reducing power consumption of capacitive loads as described in claim 2, wherein the first impedance element and the third impedance element can each be an inductor. The driver for reducing capacitive load power consumption as described in claim 2, wherein the first impedance component further includes: a first inductor; and a first diode connected in series with the first inductor. The driver for reducing capacitive load power consumption as described in claim 5, wherein the third impedance element further includes: a second inductor; and a second diode connected in series with the second inductor; wherein, the The second diode and the first diode are opposite to each other. The driver for reducing capacitive load power consumption as described in any one of claims 1 to 6, wherein the switch circuit includes: a first switch; a second switch; a third switch; and a fourth switch, wherein Each includes a first pin and a second pin; wherein the first pins of the first switch and the third switch are each electrically connected to the first power input pin, and the first switch and The second pin of the third switch is electrically connected to the first pin of the second switch and the fourth switch respectively, and the first pins of the second switch and the fourth switch respectively correspond to the The first power output pin, the second power output pin, the second switch and the second pin of the fourth switch are each electrically connected to the second power input pin. The driver for reducing capacitive load power consumption as described in claim 7, wherein the controller includes: a timing circuit connected to the switch circuit; wherein the timing circuit transmits the input signal to the switch at a preset time interval. switching circuit. The driver for reducing capacitive load power consumption as described in claim 7, wherein the controller further includes: a detection circuit connected to the voltage output end.