CN217656553U

CN217656553U - Driver for reducing power consumption of capacitive load

Info

Publication number: CN217656553U
Application number: CN202221755904.1U
Authority: CN
Inventors: 梁伟成; 张平
Original assignee: Wisetop Technology Co Ltd
Current assignee: Wisetop Technology Co Ltd
Priority date: 2022-07-07
Filing date: 2022-07-07
Publication date: 2022-10-25
Anticipated expiration: 2032-07-07

Abstract

The utility model provides a reduce driver of electric capacity load consumption, including drive signal input end, controller, switch circuit, first impedance piece and voltage output end, the controller receives input signal from the drive signal input end, the controller basis input signal generates control signal extremely switch circuit, in order to control switch circuit with first impedance piece and voltage output end forms energy storage circuit and energy recuperation return circuit, borrows by the design of first impedance piece, forms energy storage circuit and energy recuperation return circuit to reach the mesh that promotes whole power conversion efficiency.

Description

Driver for reducing power consumption of capacitive load

Technical Field

The utility model relates to a driver especially indicates a driver that reduces capacitive load consumption.

Background

In order to improve the power conversion efficiency between input and output, the switching power conversion equipment in the prior art designs a switching circuit, and makes a switch in the switching circuit work at a high frequency to perform switching control to form a power output loop.

A common high-frequency switch in the market at present uses a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and outputs a control signal to the MOSFET through a control unit of a switching power conversion device to drive the MOSFET to switch between on and off, taking Flyback converters (Flyback converters) as an example, when the MOSFET is on, voltage enables an inductor to store energy through the MOSFET, and when the MOSFET is off, the inductor transfers the stored energy to a next-stage circuit.

However, since the gate of the MOSFET has a parasitic capacitor, the control signal also stores the parasitic capacitor during the process of storing energy in the inductor by controlling the MOSFET to be turned on, and the energy of the parasitic capacitor is usually the case of power consumption, especially under the high-frequency operation of the MOSFET, when the operating frequency increases, the power consumption also increases, and thus, the power conversion efficiency of the switching power conversion device is reduced.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned prior art, the main object of the present invention is to provide a driver for reducing power consumption of capacitive load, which recovers energy by means of inductive energy storage to improve the overall power conversion efficiency of a switching power conversion device.

To achieve the above object, the main technical means of the present invention is to provide a driver for reducing power consumption of capacitive load, comprising:

a drive signal input;

the controller is connected with the driving signal input end;

the switching circuit comprises a switching control signal input pin, a first power supply input pin, a second power supply input pin, a first power supply output pin and a second power supply output pin, and the switching control signal input pin is connected with the controller;

a first impedance element, a pin of which is connected with the first power output pin;

a voltage output end connected with the other pin of the first impedance element and connected with the second power output pin;

the controller receives an input signal from the driving signal input end, generates a control signal, and drives the switching circuit to enable the switching circuit, the first impedance element and the voltage output end to form an energy storage loop and an energy recovery loop.

With the above configuration, the driver for reducing power consumption of the capacitive load outputs a control signal to the switching circuit through the controller according to an input signal, so as to control the switching circuit, the first impedance element and the voltage output end to form an energy storage loop and an energy recovery loop.

Drawings

Fig. 1 is a schematic diagram of a first embodiment of the present invention for reducing power consumption of a capacitive load.

Fig. 2 is a schematic diagram of another embodiment of the driver for reducing power consumption of the capacitive load according to the present invention.

Fig. 3 is a schematic diagram of another embodiment of the driver for reducing power consumption of the capacitive load according to the present invention.

Fig. 4 is a schematic diagram of another embodiment of the driver for reducing power consumption of the capacitive load according to the present invention.

Fig. 5 is a schematic diagram of another embodiment of the present invention for reducing power consumption of a capacitive load.

Fig. 6 is a schematic diagram of a switching circuit of the present invention for reducing power consumption of a capacitive load.

Fig. 7 is a schematic diagram of a controller for a driver for reducing power consumption of a capacitive load according to the present invention.

Fig. 8 is a control timing chart of the first to fourth switches according to the present invention.

Fig. 9 is still another timing chart of the first to fourth switch control of the present invention.

Detailed Description

Relates to a first embodiment of the driver for reducing the power consumption of a capacitive load, as shown in fig. 1, comprising a drive signal input G _IN A controller 10, a switch circuit 11, a first impedance element 12 and a voltage output terminal V _out . The drive signal input terminal G _IN Electrically connected to the controller 10, the controller 10 is further electrically connected to the switch circuit 11, and then the switch circuit 11 is connected to the first impedance device 12 via the power output pins respectively and forms the voltage output terminal V _out While the voltage output terminal V is connected _out Is electrically connected to the load 13 to provide electrical energy to the load 13.

Specifically, in the present embodiment, the switch circuit 11 includes a switch control signal input pin, a first power input pin V _CC A second power input pin GND, a first power output pin and a second power output pin, the switch control signal input pin is electrically connected to the controller 10 to receive a control signal from the controller 10, then, a pin of the first impedance element 12 is electrically connected to the first power output pin, and the voltage output end V is electrically connected to the second power input pin GND _out Is electrically connected to the other pin of the first impedance element 12 and is connected to the second power output pin.

When the controller 10 drives the signal input terminal G _IN After receiving the input signal, the control signal is generated and transmitted to the switch circuit 11, and the switch circuit 11 is actuated according to the control signal to enable the first power input pin V _CC The second power input pin GND, the first power output pin, the second power output pin, the first impedance element 12, and the voltage output end V _out And the load 13 forms an energy storage circuit and an energy recovery circuit. In this embodiment, the voltage output terminal V _out Is electrically connected to the load 13, and the load 13 is a capacitive load.

In this embodiment, the driving signal input terminal G _IN The input signal may be an operation signal for driving the switch circuit 11, and the driving signal input terminal may further include another driving signal input terminal Setting, by which another input signal is received to set the operation of the controller 10Mode and operating parameters (e.g., dead time (Deadtime) interval), etc.

Further, the present invention provides another embodiment of the driver for reducing power consumption of capacitive load, as shown in fig. 2, the driver for reducing power consumption of capacitive load further comprises a second impedance element 14, and the second power output pin is connected to the second impedance element 14 and the voltage output terminal V _out And (6) electrically connecting.

Then, the utility model discloses reduce still another embodiment of driver of electric capacity load consumption, as shown in fig. 3, the utility model discloses the driver that reduces electric capacity load consumption further includes third impedance piece 15, a pin of third impedance piece 15 with first power output pin electric connection and another pin with voltage output end V _out And (6) electrically connecting.

In the above embodiments, the first impedance element 12 and the third impedance element 15 may be inductors, and the second impedance element 14 may be resistors or inductors, in this embodiment, the inductors or the resistors may be implemented in an equivalent manner, that is, the effect of the inductors or the resistors is achieved by routing on the circuit board.

In the above embodiment, the first impedance element 12 is used in cooperation with the second impedance element 14 and the third impedance element 15, so that during the charging process of the load 13 and the discharging process of the load 13, due to the design of the impedance elements, a proper charging and discharging rate can be provided.

As shown in fig. 4, in the present embodiment, the first impedance element 12 further includes a first inductor L1 and a first diode D1. The first inductor L1 and the first diode D1 are connected in series to form the first impedance element 12, and then the first impedance element 12 is further connected to the first power output pin and the voltage output terminal V, respectively _out And (6) electrically connecting. Specifically, one pin of the first inductor L1 is electrically connected to one pin of the first diode D1, and the other pin of the first inductor L1 is electrically connected to the voltage output terminal V _out Electrically connected to the other pin of the first diode D1 and the first power output leadThe pins are electrically connected.

As shown in fig. 5, in the present embodiment, the third impedance element 15 further includes a second inductor L2 and a second diode D2. The second inductor L2 and the second diode D2 are connected in series, and the first diode D1 and the second diode D2 are in opposite phases to each other. Specifically, one pin of the second inductor L2 is electrically connected to one pin of the second diode D2, and the other pin of the second inductor L2 is electrically connected to the voltage output terminal V _out The other pin of the second diode D2 is electrically connected to the first power output pin, and the first diode D1 and the second diode D2 are in opposite phases with each other, for example, when the cathode of the first diode D1 is electrically connected to the first power output pin, the anode of the second diode D2 is electrically connected to the first power output pin, so that the first diode D1 and the second diode D2 can be in opposite phases with each other.

As shown in fig. 6, in the above embodiment, the switch circuit 11 further includes a first switch SW1, a second switch SW2, a third switch SW3 and a fourth switch SW4, and the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 each include a first pin and a second pin, the first pins of the first switch SW1 and the third switch SW3 are each electrically connected to the first power input pin, and the second pins of the first switch SW1 and the third switch SW3 are respectively and correspondingly electrically connected to the first pins of the second switch SW2 and the fourth switch SW4, the first pins of the second switch SW2 and the fourth switch SW4 are respectively used as the first power output pin and the second power output pin, the second pins of the second switch SW2 and the fourth switch SW4 are respectively electrically connected with the second power input pin, and then the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 respectively receive the control signal from the controller 10 and respectively switch to be on or off in response to the control signal, so as to enable the first switch SW1 to be on or offThe switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 may be connected to the first power input pin V _CC The second power input pin GND, the first power output pin, the second power output pin, the first impedance element 12, and the voltage output end V _out And the load 13 forms the energy storage circuit or the energy recovery circuit.

For example, taking NMOS switches as an example, the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 may be Field Effect Transistors (FETs), the first switch SW1 includes a first gate, a first drain and a first source, the second switch SW2 includes a second gate, a second drain and a second source, the third switch SW3 includes a third gate, a third drain and a third source, the fourth switch SW4 includes a fourth gate, a fourth drain and a fourth source, in this embodiment, the first drain to the fourth drain are the first pins of the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4, and the first source to the fourth source are the second pins of the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4.

In the above embodiments, the first to fourth switches SW1 to SW4 may be Field Effect transistors, metal-Oxide-Semiconductor Field-Effect transistors (MOSFETs), or Insulated Gate Bipolar Transistors (IGBTs), and in the present embodiment, each of the plurality of switches further includes an internal diode (BD 1 to BD 4) for a forward conduction operation.

As shown in fig. 7, in the above embodiment, the controller 10 further includes a timing circuit 101, and the timing circuit 101 is electrically connected to the switch circuit 11. When the controller 10 drives the signal input terminal G _IN After receiving the input signal, the input signal is transmitted to the timing circuit 101, and then the timing circuit 101 controls the operationAfter a predetermined time interval, the control signal is transmitted to the switch circuit 11.

In this embodiment, the timing circuit 101 may perform a charging or discharging waveform to the control signal by an RC circuit at a predetermined Time interval, so as to determine an output Time of the control signal according to the input signal and the waveform, or charge or discharge a capacitor through a predetermined current, generate a sawtooth wave, determine an output Time of the control signal according to the input signal and a sawtooth wave input signal, or determine an output Time of the control signal by defaulting a trigger number of the control signal through a digital counter, or determine a Propagation Delay Time (Propagation Delay Time) of a logic circuit, so that the control signal passes through one or more logic gates, thereby controlling the output Time of the control signal.

Then, the controller 10 further includes a detection circuit 102, the detection circuit 102 and the voltage output terminal V _out Electrically connected to detect the voltage output terminal V _out So that the detection circuit 102 can output a voltage according to the voltage output terminal V _out Determines the output time of the control signal output by the controller 10. For example, when the detection circuit 102 detects the voltage output terminal V _out Is the first power supply input pin V _CC And the voltage between the second power supply input pins GND is 1/2 times V of 1/2 times _CC The controller 10 outputs the control signal to the switch circuit 11. In this embodiment, the detection circuit 102 may be a voltage comparator. In this embodiment, when the detection circuit 102 detects a 1/2 times V _CC The 1/2 times is only an example and is not a limitation to the present disclosure, i.e. V between 1/5 times and 4/5 times can be adopted _CC For use as a basis for subsequent output of the control signal.

Referring to fig. 7 and 8, fig. 8 is a timing diagram of the first to fourth switch control according to the embodiment of the present invention. The controller 10 transmits the control signals to the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 respectively according to the input signal, so as to control the first switch SW1 to the fourth switch SW4 respectively.

Specifically, first, when the controller 10 has not transmitted the Control signal Control to the switch circuit 11 (i.e., before the time point t 11), the first switch SW1, the second switch SW2, and the third switch SW3 are turned off, and the fourth switch SW4 is turned on.

First, the load 13 performs a charging process: at time point t 11: the controller 10 is connected to the driving signal input terminal G _IN And after receiving that the input signal is a rising edge trigger signal, generating the Control signal Control according to the input signal.

At time point t 12: the controller 10 transmits the Control signal Control to the first switch SW1 and the fourth switch SW4, the first switch SW1 and the fourth switch SW4 respectively respond to the Control signal Control, the first switch SW1 is switched from the switch-off state to the switch-on state, and the fourth switch SW4 is switched from the switch-on state to the switch-off state, at this time, the first power input pin V is connected to the first power input pin V _CC Via the first switch SW1, the first power output pin, the first impedance 12, the voltage output terminal V _out The load 13 and the second power input pin GND form the energy storage loop, i.e. the first power input pin V _CC When the voltage is output to the load 13, the first impedance element 12 stores energy at the same time.

At time point t 13: when the controller 10 receives the input signal at a time point t11, the input signal is transmitted to the timing circuit 101, the timing circuit 101 outputs a falling edge signal to the Control signal Control after a default time interval according to the input signal, the first switch SW1 is switched from the switch on state to the switch off state according to the Control signal Control, the third switch SW3 is switched from the switch off state to the switch on state according to the Control signal Control, and at this time, the first impedance element 12 is switched from the stored electricity according to the stored electricityCan be output to the load 13 when the stored electric energy of the first impedance element 12 is not enough to satisfy the voltage of the load 13 (approximately equal to V) _CC ) While, the first power input pin V _CC Will pass through the third switch SW3, the second power output pin, the voltage output terminal V _out A voltage is output to the load 13. If the power stored in the first impedance element 12 meets the voltage of the load 13, the power stored in the first impedance element 12 will be recharged to the first power input pin V via the third switch SW3 _CC The power supply capacitor of (1).

Subsequently, the load 13 performs a discharging process: at a time point t21, when the controller 10 receives that the input signal is a falling edge trigger signal, the controller generates the Control signal Control according to the falling edge signal, and changes the state of the Control signal Control into a rising edge signal.

At time point t 22: the controller 10 transmits the Control signal Control to the second switch SW2 and the third switch SW3, so that the second switch SW2 is switched from off to on according to the Control signal Control, and the third switch SW3 is switched from on to off, at this time, the load 13, the first impedance element 12, the second switch SW2 and the second power input pin GND form a voltage loop, and the electric energy stored in the load 13 is output to the first impedance element 12 for storage. At time point t 23: when the controller 10 receives the input signal at a time point t21, the input signal is transmitted to the timing circuit 101, the timing circuit 101 outputs a falling edge signal to the Control signal Control after the timing circuit separates the default time according to the input signal, and transmits the falling edge signal to the second switch SW2 and the fourth switch SW4, so that the second switch SW2 is switched to be switched off according to the Control signal Control, and the fourth switch SW4 is switched to be switched on, at this time, the first impedance element 12 enables a current direction to be fixed and follow current due to the inductance characteristic thereof, and then the electric energy stored in the first impedance element 12 is output to the first power supply via the internal diode BD1 of the first switch SW1Input pin V _CC The power supply capacitor of (1).

Further, please refer to fig. 7 and fig. 9, fig. 9 is another timing chart of the first to fourth switch control according to the present invention. First, when the controller 10 has not transmitted the Control signal Control to the switch circuit 11 (i.e., before the time point t 11), the first switch SW1, the second switch SW2 and the third switch SW3 are turned off, the fourth switch SW4 is turned on, and the detection circuit 102 further generates the Control signal Control according to the input signal and the detection signal Detect.

At time point t 12: the controller 10 transmits the Control signal Control to the first switch SW1 and the fourth switch SW4, the first switch SW1 and the fourth switch SW4 respectively respond to the Control signal Control, the first switch SW1 is switched from the switch-off state to the switch-on state, and the fourth switch SW4 is switched from the switch-on state to the switch-off state, at this time, the first power input pin V is connected to the first power input pin V _CC Via the first switch SW1, the first power output pin, the first impedance element 12, the voltage output terminal V _out The load 13 and the second power input pin GND form the tank circuit, i.e. the first power input pin V _CC When the voltage is output to the load 13, the first impedance element 12 stores energy at the same time.

At time point t 13: the detection circuit 102 of the controller 10 is connected to the voltage output terminal V _out After receiving the feedback voltage, generating the detection signal Detect according to the comparison between the feedback voltage and the default voltage, outputting the Control signal Control to be a falling edge signal according to the detection signal Detect, and switching on the switch into switching off the switch according to the Control signal Control by the first switch SW1At this time, the stored electric energy of the first impedance element 12 is output to the load 13 via the internal diode BD2 of the second switch SW 2. At a time point t14, the controller 10 transmits the Control signal Control to the third switch SW3, and the third switch SW3 turns from the off state to the on state according to the Control signal Control, at this time, the first power input pin V is connected to the first power input pin V _CC Can be connected to the voltage output terminal V via the third switch SW3, the second power output pin _out The output voltage to the load 13 is continued.

Subsequently, the load 13 performs a discharging process: at time point t 21: when the controller 10 receives that the input signal is a falling edge signal, the controller changes the Control signal Control into a rising edge signal.

At time point t 22: the controller 10 transmits the Control signal Control to the second switch SW2 and the third switch SW3, so that the second switch SW2 is switched from off to on according to the Control signal Control, and the third switch SW3 is switched from on to off, at this time, the load 13 forms a loop through the first impedance element 12, the second switch SW2 and the second power input pin GND, so that the electric energy stored in the load 13 stores energy in the first impedance element 12.

At time point t 23: the detection circuit 102 outputs the voltage V from the voltage output terminal _out After receiving the feedback voltage, comparing the feedback voltage with the default voltage, e.g. the voltage is decreased to V _CC 1/2, the detection signal Detect is generated, the Control signal Control is output as a falling edge signal according to the detection signal Detect, and the falling edge signal is transmitted to the second switch SW2, so that the second switch SW2 is switched to be switched off, and at this time, the electric energy of the first impedance element 12 is output to the first power input pin V through the internal diode BD1 of the first switch SW1 _CC The power supply capacitor of (1). Finally, at the time point t24, the fourth switch SW4 is turned on from the off state to the on state according to the Control signal Control, and the voltage output end V _out Will be connected to the fourth switch SW4 and the second power input pin GND such that the voltage output terminal V _out And outputting according to the second power supply input pin GND.

In summary, through the utility model discloses a reduce driver of electric capacity load consumption load 13 the in-process that charges is carried out earlier through first impedance 12 is right load 13 charges, simultaneously, first impedance 12 also stores the electric energy, then, by first impedance 12 offers the electric energy of storage load 13 charges. In the process of discharging the load 13, the second power input pin GND is discharged through the first impedance element 12, and at the same time, the electric energy stored in the load 13 is output to the first impedance element 12, the first impedance element 12 stores the electric energy, and then the first impedance element 12 outputs the stored electric energy to the power capacitor. Therefore, the aim of improving the overall power conversion efficiency is fulfilled.

The above embodiments are merely illustrative of the present invention and are not intended to limit the present invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be as set forth in the claims.

Description of the reference numerals

10. Controller

101. Timing circuit

102. Detection circuit

11. Switching circuit

12. First impedance element

13. Load(s)

14. Second impedance element

15. Third impedance element

L1 first inductor

L2 second inductor

D1 First diode

D2 Second diode

SW1 first switch

SW2 second switch

SW3 third switch

SW4 fourth switch

Diode connected in BD 1-BD 4

G _IN Drive signal input terminal

V _OUT Voltage output terminal

V _CC First power input pin

GND second power input pin

Setting another driving signal input terminal

t time

time points t11 to t14 and t21 to t24

Control signal

Detect signal

Claims

1. A driver for reducing power consumption of a capacitive load, comprising:

a drive signal input;

the controller is connected with the driving signal input end;

a first impedance element, one pin of which is connected with the first power output pin;

2. The driver for reducing power consumption of capacitive loads according to claim 1, further comprising:

a second impedance element;

the second power output pin is connected with the voltage output end through the second impedance element.

3. The driver for reducing power consumption of capacitive loads according to claim 1, further comprising:

and one pin of the third impedance element is connected with the first power supply output pin, and the other pin of the third impedance element is connected with the voltage output end.

4. The driver of claim 2, wherein the first impedance element and the second impedance element can be inductors respectively.

5. The driver for reducing power consumption of capacitive loads according to claim 3, wherein said first impedance element and said third impedance element can each be an inductor.

6. The driver for reducing power consumption of a capacitive load according to claim 3, wherein the first impedance further comprises:

a first inductor;

a first diode connected in series with the first inductor.

7. The driver for reducing power consumption of a capacitive load according to claim 6, wherein the third impedance further comprises:

a second inductor;

a second diode connected in series with the second inductor;

the second diode and the first diode are in anti-phase with each other.

8. The driver for reducing power consumption of a capacitive load according to any one of claims 1 to 7, wherein the switching circuit comprises:

the first switch, the second switch, the third switch and the fourth switch respectively comprise a first pin and a second pin;

the first pins of the first switch and the third switch are electrically connected to the first power input pin, the second pins of the first switch and the third switch are electrically connected to the first pins of the second switch and the fourth switch, respectively, the first pins of the second switch and the fourth switch are used as the first power output pin and the second power output pin, respectively, and the second pins of the second switch and the fourth switch are electrically connected to the second power input pin, respectively.

9. The driver for reducing power consumption of a capacitive load according to claim 8, wherein the controller comprises:

a timing circuit connected to the switching circuit;

the timing circuit transmits the input signal to the switch circuit at a default time interval.

10. The driver for reducing power consumption of a capacitive load according to claim 8, wherein the controller further comprises:

and the detection circuit is connected with the voltage output end.