TWI463548B - Semiconductor wafer and method for producing same - Google Patents

Description

Semiconductor wafer and method of manufacturing same

The present invention relates to a semiconductor wafer having a reinforced structure and a method of fabricating the same. Another aspect of the invention relates to a chuck for supporting the semiconductor wafer. The semiconductor wafer includes a thinned central portion having a first side and a second side surrounded by at least one protruding edge portion.

In a known semiconductor wafer, it is provided with an annular frame. The frame edge includes a top surface, a bottom surface, an outer surface and an inner surface. A method of fabricating such a wafer having a thinned central portion and a ring-shaped protruding bezel is disclosed in U.S. Patent Publication No. 2008/0090505A1. A thinned central portion is formed in one of the back surfaces of one of the standard wafers, the region corresponding to one of the device forming regions on the front side of the processed standard wafer. The thinned central portion is ground by a polishing unit, and the annular frame is simultaneously formed around the thinned central portion. The annular frame edge should increase stability, thereby avoiding warping of the thinned central portion of the wafer.

The present invention provides a semiconductor wafer comprising: a thinned central portion having a first side and a second side; and at least one reinforcing structure for increasing the radial bending resistance of the semiconductor wafer. The reinforced structure provides One or more passages for a fluid to flow between and toward an outer surface of one of the reinforcing structures and one of the outer surfaces of the reinforcing structure. The fluid can be in a gaseous or liquid state.

The reinforcing structure can be configured as a plurality of elevated regions on the central portion, and the channel can be a plurality of slots that separate at least two elevated regions from each other. The slot may also be provided in the elevated area.

The slot can also be provided with a spatial orientation that includes a horizontal tilt angle (σ) between the slot and a horizontal direction of the wafer at the individual slot locations. The slot may also be provided with a radial tilt angle j ([phi]) between the slot and a radial direction of the wafer.

Preferably, at least one of the slots is spatially positioned such that there is no radial overlap between an inner bore and an outer bore of the slot. This will increase the stability of the wafer.

In another embodiment, the channel may be a ramp disposed at the elevated region.

The semiconductor wafer of the present invention is typically a standard semiconductor wafer having a thinned central portion, the thinned central portion is a flat polished mirror-like front surface of the wafer, and the first side includes a plurality of integrated bodies Electronic circuit or semiconductor device. The second side of the thinned central portion may be a recessed portion of one of the rear surfaces of the wafer, which also includes a plurality of integrated electronic circuits or semiconductor devices, the first side and the second side having via vias ( Electrical interconnect structure formed by TSV).

The present invention also provides a chuck for supporting a semiconductor wafer, the chuck comprising a circular substrate, which is subjected to a through-hole chuck Surrounded by the frame edge, the through hole corresponds to at least one position of the channel of the wafer.

The chuck may have a double annular structure corresponding to an inner ring body and an outer ring body, wherein the ring systems are perforated and rotatably arranged to each other to make the combined through hole size profile more diverse. .

The present invention also provides a method of: (1) providing a wafer 40 comprising a front surface 11 and a back surface 16; (1) - manufacturing an integrated electronic circuit 15 or a semiconductor device constructed on the front surface 11; (1) - providing at least one fluid (which may be a gas or liquid) passage 10 at the periphery of the front surface 11 and extending at least radially from an outer surface 8 of the wafer 40 toward an inner surface 9 of the wafer 40 (1) - After the wafer 40, the surface 16 defines a recess to provide a thinned central portion 2 having a first side 3 and a second side 4 surrounded by at least one reinforcing structure.

The present invention provides a wafer on which a structured metallization is readily constructed on a second side of the thinned central portion. Since the liquid can be easily discharged from the intersection between the second side of the thinned central portion and the inner surface of the bezel, any method steps performed by the liquid on the second side of the thinned central portion are utilized, Containing washing, spraying, stripping or etching will not cause problems. The accumulation of liquid makes it possible to properly structure the metallization layer and avoid contamination problems.

The invention also relates to a semiconductor wafer having a reinforced structure and a method of fabricating the same. Another aspect of the invention relates to a use To support the chuck of the semiconductor wafer.

The semiconductor wafer includes a thinned central portion having a first side and a second side surrounded by at least one protruding edge portion. The protruding edge portion includes a top surface, a bottom surface, an outer surface and an inner surface. The protruding edge formation has a plurality of through holes extending at least radially from an inner surface of the frame edge toward an outer surface of the protruding edge formation, wherein the top surface of the protruding edge formation remains unperforated. The angle of inclination of the through hole is applied between 0 and ±60 degrees from the radial direction, between 0 and ±20 degrees, preferably between 5 and ±15 degrees.

The semiconductor wafer has the advantage that excess processing liquid applied to the second side of the thinned central portion of the semiconductor wafer can be through the through holes extending radially toward the outer surface of the inner surface of the protruding edge. Discharge or divert. The accumulation of liquid in the cross-angles between the second side of the thinned central portion and the inner surface of the edged structure can be reduced or even avoided, and a better flatness of the sprayed liquid can be achieved. Furthermore, pollution can be avoided.

According to an embodiment of the invention, the height of the through hole is greater than the thickness of the thinned central portion. By the increased height of the through hole, the shunting and discharging of the liquid through the through hole can be increased.

In another embodiment, the first side of the thinned central portion and the bottom surface of the protruding edge formation provide a flat polished mirrored front surface of a standard semiconductor wafer. This has the advantage that there is no intersection angle between the thinned central portion and the protruding edge structure on the first side of the semiconductor wafer, so that the standard semiconductor process can be implemented on the first side Row.

If the wafer provides a double-sided groove portion surrounded by the protruding edge structure, not only a cross angle 隅 between the second side and the inner surface of the protruding edge structure, but also in the thinned central portion The first side and the inner surface of the protruding edge structure also have a cross angle 隅. In this or other examples, it is advantageous to provide a through hole that extends radially from the inner surface toward the outer surface (similar to the direction of the turbine blades within a turbine) in an inclined configuration.

In another embodiment, the first side of the thinned central portion is equal to the front surface of a standard wafer, and includes a plurality of rectangular blocks determined in advance by an imaginary line, wherein each block includes one An integrated electronic circuit or a semiconductor device construction. The second side of the thinned central portion is formed by a recessed portion of one of the back surfaces of a standard semiconductor wafer.

In another embodiment, the second side of the thinned central portion comprises a metallization of one of the metallization layers. This metallization can have conductive lines and pads or even bumps to provide interconnection of the back surface of the semiconductor wafer.

Furthermore, it is also possible to include a plurality of metallization structures on the second side of the thinned central portion, the plurality of insulating layers being located between the metallization structures, and including a plurality of through contacts passing through the insulating layer . This complex multi-layer metallization configuration will become feasible as the excess processing liquid will now be shunted or discharged via the through-hole protruding edge configuration of the semiconductor wafer.

The contact bump preferably comprises a sub-layer portion and at least one copper alloy An electroplated body that is covered by a layer of gold or silver alloy. In order to provide the complicated contact bump on the second side of the thinned central portion, since the wafer protruding edge structure of the frame edge includes the through hole, several different coating, spraying, spin coating and washing are performed. The processing steps will be successful.

Furthermore, the semiconductor wafer may also include a plurality of coordinated rectangular blocks determined by different lines on each side, wherein each of the coordinated blocks includes an integrated electronic circuit or a semiconductor device structure. At this time, the process of creating the integrated circuit must be implemented on both sides of the wafer in a very precise manner by means of the alignment mark and the wafer positioning mark provided at the wafer.

In another aspect, the present invention relates to a chuck for supporting a semiconductor wafer having a reinforced annular wafer frame edge, wherein the wafer has a plurality of via holes extending at least radially from an inner surface of the wafer toward One of the outer surfaces of the wafer. One of the edges of the wafer frame is still not perforated. The chuck includes a circular substrate surrounded by a chuck frame edge of a through hole. The substrate of the chuck conforms to the semiconductor wafer, and the chuck frame edge is located around the wafer. With this chuck, it is feasible to firmly support a semiconductor wafer with a thinned central portion.

In addition, it is also possible that the through hole of the chuck frame is located at the through hole at the edge of the wafer, so that the processing liquid can be shunted or discharged. Therefore, the position of the through hole of the chuck frame edge may correspond to the through hole of the wafer frame edge.

In another embodiment of the chuck, the chuck frame edge has a double annular structure including an inner ring body and an outer ring body, wherein the ring systems are perforated and rotatably arranged to each other to change combinations. Cross-sectional size of the through hole. Then, it is also possible to partially or completely close the through hole and fully open it. The through hole is placed to a maximum size and has a double annular frame edge of the chuck. If the maximum opening of the through hole is insufficient to ensure the liquid to be diverted or discharged, it is also possible to connect a vacuum container to the chuck frame edge of the chuck, and pass through the through hole of the wafer frame edge and the frame edge of the chuck The holes are used to support the split or discharge of excess liquid.

A method for fabricating a semiconductor wafer having a reinforced structure includes the following steps. First, a standard semiconductor wafer is provided. The integrated electronic circuit or semiconductor device is constructed in a plurality of predetermined rectangular blocks on the front surface of the wafer. Set several through holes and protruding structures. The vias and protruding structures are positioned along the circumference of the wafer. The vias extend radially between an outer surface of one of the predetermined regions of the wafer and an inner surface of the region, while other regions of the wafer are still unperforated and provided with protrusions.

To this end, at least one recess is ground or etched along the circumference of the wafer to form a surface behind the standard wafer having the pre-formed via. By this grinding step, a thinned central portion having a first side and a second side can be formed. The thinned central portion is then surrounded by a protruding annular edge portion. It can then be provided with a through hole so that the protruding edge configuration is retained.

One possible advantage of one of the methods is that the via structure and the protrusions are formed after the semiconductor processing step.

Another method for fabricating a semiconductor wafer having a reinforced structure includes the following steps. First, a standard semiconductor wafer is provided. Next, a plurality of through holes and protrusions are provided along the circumference of the wafer. Thereafter, grinding or etching of the grooves is performed in the surface. Subsequently, integrated electronic circuits or semi-conductors The body device configuration can be formed on one or both sides of the wafer. The device configurations can be positioned within a plurality of predetermined rectangular blocks.

The through holes may be in the form of slots that are cut by all sawing tools that are at least radially inclined from the outer surface of the wafer toward the inner surface thereof. The top surface of the wafer remains uncut. Cutting the slots to provide through holes is extremely cost effective and not extremely complicated, but contamination of the wafer surface may occur during this cutting step. Therefore, it is advantageous in that the slots are cut after the completion of the semiconductor processing step and before any thinning of the central portion of the wafer is performed.

This cutting can be performed such that the depth of the slit can be less than the thickness of the protruding structure and deeper than the thickness of the thinned central portion. If the cutting enters the thinned central portion and microcracks occur, the oblique radial cutting length of the slit can extend as little as possible into the thinned central portion.

An improved method for making the plurality of vias and protrusions is an etch process, which may be a dry etch process, preferably RIE-plasma etch (reactive ion etch). However, it is also possible to employ a wet etch process to create the plurality of vias along the circumference of the wafer.

When such a via protruding structure wafer is provided, it is possible to perform deposition of a metal or carbon seed layer for forming a metallization or bump plating on the second side of the thinned central portion. structure. This metal or carbon seed layer may be necessary if the plating structure can be achieved by an electrochemical plating process. If it is possible to spray or spin a photoresist, spray the developer, spray the etching solution, wash the cleaning solution, spray stripping in the case of diverting or discharging excess liquid through the plurality of through holes of the frame edge The at least one step of liquid removal, electroplating or coating of the electrolyte to plate the metal or carbon seed layer into the electronic bumps will form the metal or carbon seed layer.

When the metal or carbon seed layer is structured and plated into the metallization and/or electronic bumps, a thin metal or carbon seed layer can be deposited to the thinned central portion by a sputtering process. Two sides. In the case where an excess photoresist is discharged through the through hole, spraying and spin coating of a photoresist layer can be performed. Next, drying of the photoresist layer is performed. The dried layer can be structured by exposure through a mask. Next, in the case where excess photoresist and excess developer are discharged through the via, the exposed photoresist layer is developed by spin coating.

After the above steps, the structured photoresist layer is washed by spraying a washing liquid while the washing liquid is discharged through the through holes. The developed photoresist structure is then cured into a plating mask. During the electroplating process, the uncovered photoresist seed layer is subjected to recycling of the liquid on the structured seed layer and through the through hole in an electrochemical bath to divert the liquid. The seed layer is treated to form a metallization and/or metal bump.

After electroplating, the photoresist of the electroplated mask is stripped from the second side of the thinned central portion by spraying the stripping liquid while discharging the excess stripping liquid and the stripped photoresist through the through hole. except. Next, the stripped structure is cleaned by a cleaning liquid while discharging excess cleaning liquid through the through hole. Then, in the case where the excess etching liquid is discharged through the through hole, the remaining portion of the thin seed layer is irradiated by spraying the etching liquid. Wet etching.

After the wet etching, the etched structure is washed by spraying the washing liquid while discharging the excess washing liquid through the through hole. Finally, the second side of the bump is cleaned by the cleaning liquid while the excess cleaning liquid is discharged through the through hole, and the semiconductor wafer is dried. The result of the above method steps is to form contact bumps on the second side of the thinned central portion, which can be used to stack a semiconductor wafer on the other in a very small manner to form a block of the stacked semiconductor device. A block of bulk or stacked integrated circuits.

A semiconductor wafer according to the present invention is provided with: a thinned central portion having a first side and a second side; and at least one reinforcing structure for increasing the radial bending resistance of the semiconductor wafer, The reinforcing structure provides at least one passage for a fluid to flow between and toward an inner surface of one of the reinforcing structures and toward an outer surface of the reinforcing structure.

The channel may be a slot formed in the elevated region, the slot being provided with a spatial orientation comprising a horizontal tilt angle (σ) at a level of the slot and the wafer at a location of the individual slot Between directions. The slot may also be provided with a spatial orientation that provides a radial tilt angle j ([phi]) between the slot and a radial direction of the wafer at the individual slot locations.

When the spatial positioning of at least one of the slots is provided, good bending resistance is obtained, so that there is no radial overlap between an inner hole and an outer hole of the slot.

Instead of or in addition to the slot, the channel may be a ramp. It is located at the elevated area.

The present invention also provides a chuck for supporting a semiconductor wafer that is suitable for use in a channel within the semiconductor wafer.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1 shows a schematic front view of an improved semiconductor wafer 12 having a positioning mark 33 that replaces a standard positioning line 38. The alignment indicator 33 is related to the crystal positioning of the single crystal germanium wafer and is slightly labeled as compared to the alignment line 38 of a conventional semiconductor wafer. The minute positioning marks 33 are cut or etched in a predetermined area of one circumference of the wafer 12. Moreover, FIG. 1 reveals that the one-way designation 34 makes it easier to adjust the wafer 12 to a wafer chuck. Recently, since wafers having a diameter of 200 mm or more are transported by a single standard <100> crystal positioning, the positioning marks can be omitted or simply replaced by a pair of slots.

In the center of the wafer 12, its virtual axis of symmetry 63 is illustrated in Figure 1.

Figures 2 through 8 disclose a schematic representation of one of several possible methods for forming a wafer having a reinforced structure having a plurality of blocks with vias therebetween and a recessed thin central portion.

Figure 2 is a schematic cross-sectional view of a wafer 40 of a standard germanium semiconductor The wafer 40 has a thickness D in the range of 600 to 700 micrometers (μm) and a radius r of about 50 to 150 millimeters (mm). Furthermore, the standard 矽 semiconductor wafer includes a polished mirror-like front surface 11 and a flattened rear surface 16. The front surface 11 is configured to introduce an integrated circuit configuration or a semiconductor device configuration by a process of known semiconductor technology.

3 is a cross-sectional view showing the semiconductor device structure or integrated circuit 15 processed on the front surface 11 of the wafer 40 according to FIG. The dashed line is a virtual dividing line 14 of a cutting tool that later divides the wafer 40 into semiconductor wafers of a plurality of integrated circuits 15 or semiconductor wafers of a plurality of semiconductor devices. In order to subsequently connect the front and back surfaces of a semiconductor wafer having an integrated circuit through conductive vias, it is possible to etch a blind via in the polished surface prior to performing the polishing. The holes may be plated with a conductive layer. After the wafer is polished and thinned, the vias can be connected to a conductive structure that is subsequently formed on the back side of the wafer (not shown).

4 is a cross-sectional view showing the wafer 40 according to FIG. 3 after the radially extending slot 31 is cut in the circumference of the wafer. This dicing step eventually becomes the modified wafer 12 as shown in FIG. The slot 31 is cut by all of the saw blades 32, which are moved in the direction of an arrow A and simultaneously in the direction of an arrow B. The cutting length l is defined by the area of the integrated circuit 15, and the cutting depth c in the direction B is defined by the thickness D and state of the semiconductor wafer, wherein a predetermined frame edge will be provided with an undefined The top surface of the perforation. except In addition to the cutting step, it is also possible to replace it with an etching step to provide a frame edge of a through hole. Furthermore, it is preferred to use an etching step after dicing to release stress and minimize crystal defects.

In an embodiment not shown herein, a tilt angle 偏离 is offset from the radial direction by between 0 and ±20 degrees, preferably between 10 and ±15 degrees. The tilt angle Ψ is shown in the lower right portion of the wafer in FIG. 5 and has one inclined slot shown by a broken line.

Fig. 5 is a schematic front view showing the wafer 12 according to Fig. 4 after completion of the through hole grooving of the circumference of the wafer 12. In this embodiment, the spacing between the two-way slot or slot 31 is determined by an angle α of 11.75°, which causes 32 slots to be formed on the front surface 11 of the wafer 12, etc. From the through hole 10. The active surface of the wafer 12 provides a virtual rectangular block 13 surrounded by a virtual dividing line 14 of all sawing tools. In the present embodiment, an integrated circuit 15 is provided in each rectangular block.

Fig. 6 is a cross-sectional view showing the wafer 12 according to Fig. 4 in an upper side downward position. The front surface 11 is currently in a lower position, including the integrated circuit 15, while the wafer rear surface 16 is currently in an upper position, so that a grinding stone can be used for the rear surface 16 to be on the rear side of the integrated circuit 15. Make a thin central part.

Figure 7 is a cross-sectional view showing the wafer 12 according to Figure 6 after it has been ground to form a recess in the surface 16 of the wafer 12. A recessed thinned central portion 2 can be fabricated by grinding, and has a first side 3 including the integrated circuit 15 and a second side 4 formed behind the integrated circuit 15 side. An annular frame edge 1 will be formed by grinding the recess, wherein the bezel provides a top surface 6 which is part of the original rear surface 16 of the wafer. Furthermore, the frame edge 1 has a lower surface 7, which in this embodiment is coplanar to the front surface 11 of the wafer. Furthermore, the frame edge has an outer surface 8 which is identical to the outer circumferential area of the wafer. An inner surface 9 is formed during the grinding of the recessed thin central portion 2 of the wafer 12. The opening of the through hole 10 is formed by grinding the inner surface 9 within the range of the slot 31. The through holes 10 allow shunting and discharge of the processing liquid during preparation of the back side of the different integrated circuits 15 or semiconductor device configurations.

Fig. 8 is a schematic rear view showing the wafer according to Fig. 7. The frame edge 1 surrounds the thinned central portion 2, which shows its second side 4, and thus the integrated circuit 15 is indicated by a broken line. Since the top surface 6 of the frame edge 1 provides an annular edge portion 5 and is not perforated, the through hole 10 is only indicated by obliquely extending radial dotted lines. The positioning mark 33 and the adjustment mark 34 are smaller than the width w of the frame edge 1, so that the top surface 6 of the frame edge 1 is not disturbed.

Fig. 9 is a schematic cross-sectional view showing a grinding stone 41 for grinding a recessed thinned central portion 2. The grinding stone 41 is fixed to a rotatable grinding stone support 42. The grinding stone support 42 moves in the direction of the arrow C to polish the surface 16 of the wafer 12, the thinned central portion 2 has a second side 4 and an intersection between the second side 4 and the Between the inner surfaces 9 of the frame edge 1. Since the grinding stone 41 has a grinding angle α of 90°, between the second side 4 and the inner surface 9 of the frame edge 1 The intersection is also a right angle. Unless the through holes are outlined by dashed lines by all sawing tools, this will result in the accumulation of the above processing liquids and contaminants.

Figure 10 is a schematic cross-sectional view showing a modified grinding stone 41 which provides a smooth intersection between the thinned central portion 2 by a 45° grinding angle α in this embodiment. Between the surface 4 and the inner surface 9 of the frame edge 1. Through the smooth intersection to reduce the accumulation of processing liquid and the accumulation of contaminants, the area of the frame edge of the smooth intersection must be larger, and the area of the integrated circuit will be smaller than that of Figure 9. Steep intersection. Therefore, it is more reasonable to provide a frame edge 1 having a sufficient number and size of through holes to surround the wafer 12.

Figure 11 shows a schematic perspective view of a via 12 wafer. Furthermore, the thinned central portion 2 is surrounded by a frame edge 1 having an unperforated top surface 6 and an outer surface 8 and an inner surface 9, the inner surface 9 being shown with a through hole 10 . At the outer surface 8 of the frame edge 1, the positioning indicator 33 and a calibration indicator 34 are positioned so as not to interfere with the top surface 6 of the frame edge 1.

Fig. 12 is a schematic cross-sectional view showing the wafer according to Fig. 11. At this time, the wafer 12 has only one depressed portion to construct the thinned central portion 2, and an improvement of the thinned central portion will be shown in the next figure.

Figure 13 is a schematic cross-sectional view showing a double recessed central portion 29 of a wafer 12. At this time, the surface of the wafer 12 and the front surface 11 of the wafer 12 may be ground and/or etched to form a groove. In this double depression The central portion 29 has a first side 3 and a second side 4 which are surrounded by a protruding annular edge portion 5 to provide an annular frame edge 1. In this embodiment, a semiconductor process can be performed on both sides 3 and 4 after the polishing process is completed.

Figures 14 through 17 disclose schematic rear views of several modified wafers that include different alignment marks and/or alignment marks. The wafer 12 of Figure 14 has a location line 38 to provide a very small width W that is relatively less than the width of one of the standard semiconductor wafer lines. This small width should be small enough to obtain a continuous, unperforated top surface 6 of the frame edge 1. The through hole 10 of this embodiment has a pitch angle of only 10°, so that 36 through holes 10 can be positioned on the annular frame edge 1.

Figure 15 is a schematic rear view of an improved wafer 12 including the alignment and alignment marks shown in Figure 1. This alignment mark provides only a small slot in the annular frame edge 1. Therefore, the width W from a left alignment mark 33 to a right alignment mark 33 can be wider than that of the 14th figure.

Figure 16 discloses a schematic rear view of an improved wafer 12 that provides buried positioning and alignment displays 33 and 34. The indicia do not interfere with the unperforated top surface 6 of the wafer frame edge 1.

Figure 17 shows a schematic rear view of an improved wafer 12. The positioning and alignment are achieved by varying the angle between the plurality of through holes 10 such that a chuck corresponding to the key is adjustable to the wafer.

Subsequent Figures 18 through 24 disclose steps for forming a structured metallization on the second side of the thinned central portion 2 of a wafer 12. 4 on.

Figure 18 is a schematic cross-sectional view showing the deposition of a sub-layer 21 on the second side 4 of the thinned central portion 2 according to Figure 7. The nanometer thickness seed layer 21 increases the conductivity of the second side 4 of the thinned central portion 2 and provides an electrical contact for electrochemically plating a plurality of metallization structures or bumps to the thinned central portion The second side of 2 is 4. The seed layer 21 can be sprayed onto the second surface 4 or can be deposited by a metal or carbon deposition process.

Fig. 19 is a schematic cross-sectional view showing the deposition of a photoresist layer 35 to the seed layer 21 according to Fig. 18. The photoresist layer must be structured to form a plating mask prior to creating a bump or metallization on the seed layer by electroplating.

Figure 20 is a schematic cross-sectional view showing the opening 43 of the photoresist layer after an exposure step and a development step according to Figure 19. In the developing step, a developing solution is sprayed on the photoresist layer 4 of the thinned central portion 2 of the wafer 12 in an arrow direction F, and excess developing solution can pass through the through hole of the frame edge 1 of the wafer 12. 10 to split or discharge.

Figure 21 illustrates an overview of a plating unit for forming bumps on the second layer 4 of the thinned central portion 2 of the wafer 12. The plating unit has a nozzle 44 and a through-hole copper plate 45. The copper plate 45 is connected to a positive potential of the DC power source, and an electrochemical liquid is sprayed through the through-hole copper plate 45 and in an arrow direction G to be on the second surface of the thinned central portion 2 of the wafer 12. A liquid film 46 is formed on the electrode 4 as an electrochemical bath 37.

The wafer is positioned within a container 47. The outer surface 8 of the frame 1 coincides with the inner surface 48 of the container 47, which is connected to the negative potential of the DC power source. The wafer 12 is positioned at the bottom of the container 47, and a conductive sealing member 49 is in liquid close contact with the second side 3 of the wafer 12, so that copper ions can be modified and plated through the opening 43 of the photoresist layer 35. The opaque portion of the seed layer 21 is used as a plating mask 36. The excess liquid of the electrochemical bath 37 can be split or discharged via the vias 10 of the wafer 12 and the openings 50 of the container 47. If the container 47 is rotated with the wafer 12, the excess processing liquid will be discharged by the centrifugal force in the direction H of the arrow.

Fig. 22 is a view showing the outline of the wafer 12 according to Fig. 21 after the photoresist is stripped. In order to strip the photoresist, a stripping solution is sprayed onto the second side 4 of the thinned central portion and can be discharged through the via 10 of the wafer 12. The bump 20 is then depicted on the seed layer 21 of the second side 4 of the thinned central portion 2 of the wafer 12. In order to avoid a short circuit caused by the residual seed layer 21, the seed layer must be etched by an etching solution.

Fig. 23 is a schematic cross-sectional view showing the wafer 12 according to Fig. 21 after etching the seed layer. During the etching, the etching liquid can be discharged or shunted through the through holes 10 of the wafer 12, and after the etching, washing is required, so that a sprayed washing liquid can also be branched or discharged through the through holes 10.

24 shows a schematic cross-sectional view of the wafer 12 having a multilayer structure 51 on the second side 4 of the thinned central portion 2 of the wafer 12. The multilayer structure 51 can be provided with a plurality of metallization layers 17 with conductive lines and provided An insulating layer 18 is located between the metallization layers 17. It is also possible that on the top surface of the multilayer structure 51, the bumps 20 are positioned with through contacts 52 that pass through different insulating layers 18 to the metallization layers 17. The formation of the multilayer construction 51 requires multiple spraying of the processing liquid, which can now be shunted or discharged via the through-frame rim 1 of the wafer 12.

Figure 25 shows a front view of a wafer support chuck 22. The wafer support chuck can support and support a wafer 12 having a reinforced annular wafer frame edge 1 as shown in FIG. 22, wherein the wafer frame edge 1 has a plurality of through holes 10 at least by the frame The inner surface 9 of the rim 1 extends radially toward the outer surface 8 of the rim 1 . One of the top surfaces 6 of the wafer frame edge 1 remains unperforated. The chuck 22 includes a circular substrate for supporting the wafer 12, which is surrounded by the chuck frame edge 30 of the through hole 24. The substrate of the chuck 22 conforms to the semiconductor wafer, and the chuck frame edge 30 surrounds the wafer frame edge 1.

The embodiment of the chuck 22 of Fig. 25 discloses that the chuck 22 provides a chuck frame edge 30 comprising a double ring configuration having an inner ring body 26 and an outer ring body 27, wherein the ring bodies 26 and 27 They are perforated and rotatably arranged to each other to make the profile of the combined through-hole size more diverse. By means of a handle 53, the rings 26 and 27 can be moved in a closing direction C or in an opening direction O to achieve maximum opening of one of the through holes 24. The processing liquid can thus be shunted or discharged through the through hole 10 of the wafer frame edge 1 and the through holes of the ring bodies 26 and 27 of the chuck frame edge 30 in an arrow direction K.

Figure 26 is a diagram showing the wafer support chuck 22 according to Fig. 25. To cut the view. On the right hand side of Figure 26, the handle 53 is shown in cooperation with a transmission 54. The transmission 54 has a gear 56 connected to the handle 53. This gear 56 has a small number of teeth. The gear 56 is mated to one of the teeth of the substrate 23. The bearing of the shaft 55 of the gear 56 is disposed outside the ring frame 27 of the chuck frame 30, so that by moving the handle 53, the combined cross-sectional dimension of the through hole 24 may be varied.

Figure 27 illustrates a schematic cross-sectional view of a wafer support chuck 22 having a vacuum connection structure 57. The vacuum connection structure 57 helps the processing liquid L to pass through the through hole 10 of the wafer frame edge 1 and the through hole 24 through the chuck ring bodies 26 and 27 from the thinned central portion 2 of the wafer 12 The two sides 4 are split and discharged. The vacuum connection configuration 57 draws the processing liquid to a vacuum vessel 28 where it can be collected and recovered.

Fig. 28 is a schematic cross-sectional view showing the chuck 22 according to Fig. 27 in an upper side downward position. Figure 28 demonstrates that a chuck can also be used in an upper side down position, particularly when sucked into the vacuum vessel 28 by means of a vacuum connection configuration 57.

Figures 29, 30, 31 and 32 disclose another semiconductor device configuration. Components having elements similar to those of the above-described semiconductor device construction have the same reference numerals.

As shown in Fig. 30, from the bottom view of the bottom side of the wafer 12, the slot 31 is disposed such that it intersects the central portion 2 and cuts the lower surface 7 and the outer surface 8. The top surface 6 of the top side of the wafer 12 is not cut. The semiconductor device of FIGS. 29 to 32 is constructed in a The extent is similar to the semiconductor device configuration of FIG. This provides a reinforced structure as the elevated region is located on the central portion 2, the reinforced structure comprising a portion of the rim 1 .

Unlike the semiconductor device configuration of FIG. 7, the slot 31 of the semiconductor device configuration of FIGS. 29 to 32 is provided with a spatial positioning which provides a radial tilt angle j (φ) between each slot 31 and the individual slot 31. The location is between a radial direction of the wafer 12. As a result, the stability of the wafer 12 can be improved.

Fig. 31 is a sectional view taken along line A-A of Fig. 30. FIG. 31 illustrates the passage of the wafer 12 from the outer surface 8 to the inner surface 9 via which the slot 31 is provided.

32 and 29 illustrate the oblique positioning impact of the slot 31 on the flexibility of the wafer 12. The slot 31 has an inner hole 31' which is located in the radial direction of the wafer 12 but which is not on the same line as the outer hole 31 of the same slot 31. It means that the observer cannot see through a slot 31 completely when viewed from the radial direction of the wafer 12. If the radial tilt angle j is properly selected, here 60°, the effective geometric moment of inertia of the radial profile of the wafer 12 will be different from the design of FIG. A method of selecting the radial tilt angle j provides the slot such that there is no radial overlap between the inner bore 31' and the individual outer bores of the slot 31. It means that if the observer looks radially inward from the outer side of the wafer 12 via the slot 31, the observer cannot see the inner hole 31', but only the slot 31 can be seen in the frame of the wafer 12. The inner wall of the edge 1.

For a better comparison, Figure 33 reveals wafer 12 of Figure 7 by A schematic view of the outside observation, which corresponds to the schematic diagram of the wafer 12 of FIG. As shown in Fig. 33, the radial inclination angle j is 0° here, so that the inner hole 31' of the slot 31 and the individual outer holes have a complete radial overlap. If the wafer 12 and the slot 31 are the same size, the effective geometric moment of inertia of the radial profile of the wafer 12 of Figures 19 to 32 will be different from the corresponding geometric moment of inertia of the wafer of Figure 7.

It is believed that the actual size of the effective geometric moment of inertia of the radial profile of the wafer plays an important role. The minimum absolute dimension of the radial geometric moment of inertia along the circumference of the wafer is also important because the cracking of the wafer often occurs at the location of the minimum radial geometric moment of inertia. The proper location and positioning of the slot within the frame edge of the wafer will improve its behavior.

Alternatively, it may be advantageous to place the slot in a direction that is different from the preferred crystallization line or major rupture line along the main axis of symmetry of the crystal used to make the wafer.

Fig. 34 is a schematic bottom view showing another semiconductor device configuration similar to the semiconductor device configuration of Figs. 29 to 32. Components having elements similar to those of the above-described semiconductor device construction have the same reference numerals.

The slot 31 is curved in a plane of the wafer 12 and is similar to the shape of a turbine blade. One method of making the curved slot utilizes a cylindrical or tapered abrasive head that moves into the frame edge 1 of the wafer 12. The resulting slot 31 is arranged such that it intersects the central portion 2, cutting the lower surface 7 and the outer surface 8. The top surface 6 on the upper side of the wafer 12 is not cut. The slot 31 can also be at least partially borrowed It is formed by an etching process.

This provides a reinforced structure as the elevated region is located on the central portion 2, the reinforced structure comprising a portion of the rim 1 .

Alternatively, the radial geometric moment of inertia of the wafer 12 can be improved, and there may be a reduced local stress concentration point within the slot which in turn improves the rupture strength of the wafer 12. The curved slot 31 can also have a positive effect to remove liquid through the through hole 10 in the slot 31 as the wafer 31 rotates.

Figures 35 and 36 disclose a schematic bottom and side elevational view of another semiconductor device configuration similar to the semiconductor device configuration of Figures 29 to 32 or 34. Components having elements similar to those of the above-described semiconductor device construction have the same reference numerals.

The slot 31 is fabricated using a beveled or angled cutting blade that moves into the frame edge 1 of the wafer 12 beginning at the lower surface 7 and the outer surface 8. The resulting slot 31 is arranged such that it intersects the central portion 2, cutting the lower surface 7 and the outer surface 8. The top surface 6 on the upper side of the wafer 12 is not cut. The slot 31 can also be formed at least in part by an etching process.

This provides a reinforced structure as the elevated region is located on the central portion 2, the reinforced structure comprising a portion of the rim 1 .

The slot 31 has an angled base at the lower surface 7 and at the outer surface 8, which has an increased cross-sectional area for a predetermined depth of cut compared to the design of Figure 7. It may have a positive effect to exclude liquid through the through holes 10 in the slot 31.

In another alternative not shown, the slot 31 has a beveled base in the lower surface 7 and in the bezel 1 and the outer surface 8 is oriented in a radial direction relative to the wafer 12. With a tilted positioning. This design is somewhat similar to the design of Figures 29 to 32.

Figure 37 shows a schematic top view of another semiconductor device configuration. Components having elements similar to those of the above-described semiconductor device construction have the same reference numerals. The difference from the above design is that the design of Fig. 37 has a slot 31 disposed in the frame edge 1 of the top surface 6 of the wafer 12 such that the slot 31 extends past the top of the frame edge 1. The reinforced structure is formed as an elevated region between two adjacent slots 31. Figure 37 discloses a design having a radial tilt angle j(?) here at 0[deg.] such that there is a complete radial overlap between the inner bore 31' at the through hole 10 and the individual outer bores of the slot 31. There appears to be no significant advantage in the stability against bending in the radial direction of the wafer 12 compared to wafers without a reinforced construction, but this design may have the advantage of discharging liquid from a rotating wafer 12.

Figure 38 is a schematic top plan view showing another semiconductor device configuration similar to that of the semiconductor device of Figure 10 before cutting the frame 1. Components having elements similar to those of the above-described semiconductor device construction have the same reference numerals.

As shown in Fig. 39, which is a schematic cross-sectional view showing the construction of the semiconductor device of Fig. 38, a grinding stone having a grinding angle α of about 45° has an upper edge 60 formed on a top surface 6 and a second side 4 A lower edge 61 is formed and extends between the upper edge 60 and the lower edge 61 to form an inclined surface. It is also possible that the inclined mask between the upper edge 60 and the lower edge 61 has a further angle α, in particular between 10° and 60°. In another embodiment not shown, the upper edge 60 and the lower edge 61 are arcuate, so that there is no edge line in the sense of a word. This accelerates the flow of liquid through the top surface 6. Better results can be obtained if the contour of the inclined surface is mathematically shaped as a tangential hyperbolic curved surface.

The wafer 12 of Fig. 38 can be used immediately to provide electronic circuitry and semiconductor device construction on its front surface 11 and second side 4, such as shown in the above figures, particularly with reference to Figures 1-28. The liquid used in the processing steps can be discharged from the frame edge 1 by simply flowing over the inclined surface between the upper edge 60 and the lower edge 61.

Another embodiment not shown here is a combination of Fig. 37 and Figs. 38 and 39. The reinforcing structure has a raised region on the central portion, and the reinforcing structure includes a portion of the frame edge that is distinguished by the slit. The reinforcing structure forms an upper edge on a top surface and a lower edge on a second side of the wafer, and an inclined surface is formed between the upper edge and the lower edge. The wafer can be used to provide electronic circuitry and semiconductor device construction on its front and second sides. The liquid used in the processing steps can be discharged from the frame by flowing over an inclined surface or slope between the upper and lower edges and through a slot between the reinforcing structures.

Fig. 40 is a schematic top view showing the construction of another semiconductor device. Components having elements similar to those of the above-described semiconductor device construction have the same reference numerals. Similar to the design of Fig. 37, the design of Fig. 40 has a slot 31 which is provided in the frame edge 1 on the top surface 6 of the wafer 12 due to The slot 31 extends through the top of the frame edge 1. The reinforcing structure is thus arranged as an elevated block between two adjacent slots 31. A 40th publication has a radial tilt angle j of about 60° here so that there is no radial overlap between the inner hole 31' of the through hole 10 and the individual outer holes of the slot 31.

This relates to an increase in stability against bending in the radial direction of one of the wafers 12 compared to a wafer having no reinforced structure, and has an advantage in that liquid is discharged from a rotating wafer 12.

Since most of the manufacturing steps and in particular its mechanical processes (eg, the grinding of the second side 4 and the provision of the slot 31) can be set by a single side and do not require wafer intermediate processing between individual manufacturing steps, The wafer 12 can be easily fabricated. If the wafer 12 undergoes a wet process, the wafer chuck can avoid chemical contamination. Furthermore, the effective profile of the slot 31 can be increased to cause a liquid to flow through the slot 31.

Figure 42 is a cross-sectional view along line A-A of Figure 40 showing the passage from the outer surface 8 of the wafer 12 to the inner surface 9 through the slot 31.

Fig. 41 is a schematic top view showing the construction of another semiconductor device similar to the semiconductor device configuration of Figs. 40 and 42. Components having elements similar to those of the above-described semiconductor device construction have the same reference numerals.

The slot 31 is curved in a plane of the wafer 12 and is similar to the shape of a turbine blade. A method of making the curved slot uses a cylindrical or tapered abrasive head that moves into the wafer 12 inside the frame edge 1. The resulting slot 31 is arranged such that it intersects the central portion 2, cutting the lower surface 7 and the outer surface 8. The top surface 6 on the upper side of the wafer 12 is not cut. The slot 31 can also be formed at least in part by an etching process.

This provides a reinforced structure as the elevated region is located on the central portion 2, the reinforced structure comprising a portion of the rim 1 .

Alternatively, the radial geometric moment of inertia of the wafer 12 can be improved, and there may be a reduced local stress concentration point within the slot which in turn improves the rupture strength of the wafer 12. The curved slot 31 can also have a positive effect to remove liquid through the through hole 10 in the slot 31 as the wafer 31 rotates.

Figure 43 discloses another semiconductor device configuration. Components having elements similar to those of the above-described semiconductor device construction have the same reference numerals.

The slot 31 of the semiconductor device configuration of Figures 29 to 32 is provided with a spatial orientation that provides a horizontal tilt angle (σ) between each slot 31 and the horizontal direction of the wafer 12 at the location of the individual slots 31. . As a result, the stability of the wafer 12 can also be improved.

The spatial positioning of the slot 31 can also be combined with the radial tilt angle j of Figure 32. This avoids radial overlap between the inner bore 31' and the individual outer bores of the slot 31, keeping the second side 4 uncut so that it has substantially less or even no damage or cracking.

Figure 44 discloses another semiconductor device configuration. Components having elements similar to those of the above-described semiconductor device construction have the same reference numerals.

When the semiconductor device of Fig. 42 is constructed with a slot 31 having an empty Positioning to provide a horizontal tilt angle (σ) and a radial tilt angle j to pass through the top surface 6 and to maintain the lower surface 7 substantially uncut, the semiconductor device configuration of FIG. 43 is provided with a slot 31 A similar spatial location is positioned through the lower surface 7 and the upper surface 6 is maintained substantially uncut.

Figure 45 is a cross-sectional view showing another semiconductor device structure having a slot 31 having a spatial orientation to provide a horizontal tilt angle (σ) and a radial tilt angle j (φ) through which the slot 31 extends. The top surface 6 passes through the lower surface 7. A specific position on the circumference of the frame edge 1 has a virtual radial bending axis 62, an upper curved region Au, and a lower curved region A1. These regions facilitate calculation and improvement of the local geometric moment of inertia of the wafer against radial bending around the virtual radial bending axis 62, and are substantially advantageous for improving the stress level of the wafer 12.

To fabricate the semiconductor wafer with the reinforced construction described above, the operator can first create a channel of the slot 31 pattern and then create a recess in the surface 16 of the wafer 12. Alternatively, the operator may first create the groove in the surface 16 of the wafer 12 and then create the channel of the slot 31 pattern. By some manufacturing methods, if the slope 60, 61 or the slot 31 type of channel and the recess of the rear surface 16 are provided on the same side of the wafer 12 (such as 37, 40, 41, 42, 43 and 45)), the grooves of the surface 16 behind the wafer 12 and the channels of the ramp 60, 61 or the channels of the slot 31 can be created together, even during the same process.

It has the advantage that the reinforcing structure between the slots 31 is not A continuous frame edge 1 is formed, so that the liquid channel of the slot 31 type and the groove of the rear surface 16 can be disposed on the same side of the wafer 12. The reinforced construction coefficients are a collection of separate block segments that are discontinuously arranged on the circumference of the wafer 12. To form this reinforced construction, the operator can even use plasma etching without any mechanical grinding.

The slot 31 or ramp 60, 61 type of passage can be formed by a cutting tool or by a more conventional means of circumferential grinding tools and numerical control. Other methods of forming the channel of the slot 31 type or ramp 60, 61 type include the use of a laser abrasive method or a finger mill or an end mill, which is particularly suitable for use. The curved slot as shown in Fig. 34 or 41 is formed. It is also possible to provide a lithographic construction followed by at least one etching step (such as dry etching or wet etching of tantalum or a combination of both etching methods).

If a grinding step is used to form a recess in the surface behind the wafer 12, a plasma process is typically followed to release the stress of the wafer material. This can also be done by a wet etching step. The wafer 12 of the present invention provides the advantage that the plasma gas or etchant is easily removed from the grooves on the back surface of the wafer via the slot 31 pattern or the ramp 60, 61 type of channel. This is not easily achieved with known wafers with recessed back surfaces.

1‧‧‧Ring frame

2‧‧‧ Thin Central

3‧‧‧ first side

4‧‧‧ second side

5‧‧‧ annular edge

6‧‧‧ top surface

7‧‧‧ lower surface

8‧‧‧ outer surface

9‧‧‧ inner surface

10‧‧‧channel (through hole)

11‧‧‧ front surface

12‧‧‧ wafer

13‧‧‧ Block

14‧‧‧virtual line

15‧‧‧Integrated circuit

16‧‧‧Back surface

17‧‧‧metallization

18‧‧‧Insulation

19‧‧‧Metalized structure

20‧‧‧Bumps

21‧‧‧ seed layer

22‧‧‧ wafer support chuck

23‧‧‧Substrate

24‧‧‧through hole

25‧‧‧Double ring

26‧‧‧ Inner ring

27‧‧‧ outer ring

28‧‧‧Vacuum container

29‧‧‧The central part of the double depression

30‧‧‧ chuck frame

31‧‧‧ slot

31’‧‧‧ 内孔

32‧‧‧Saw blade

33‧‧‧ Positioning indication

34‧‧‧ alignment mark

35‧‧‧Photoresist layer

36‧‧‧Electroplating mask

37‧‧‧Electrochemical bath

38‧‧‧Standard Positioning Line

40‧‧‧ wafer

41‧‧‧ Grinding stone

42‧‧‧ Grinding stone support

43‧‧‧ openings

44‧‧‧Nozzles

45‧‧‧ copper plate

46‧‧‧Liquid film

47‧‧‧ Container

48‧‧‧ inner surface

49‧‧‧Electrical seals

50‧‧‧ openings

51‧‧‧Multilayer construction

52‧‧‧through joints

53‧‧‧Hands

54‧‧‧Transmission

55‧‧‧ shaft

56‧‧‧ Gears

57‧‧‧Vacuum connection construction

60‧‧‧Upper edge

61‧‧‧ lower edge

62‧‧‧Virtual radial bending axis

63‧‧‧Virtual axis of symmetry

A‧‧‧ direction

Au‧‧‧Upper curved area

Al‧‧‧Bottom bending area

B‧‧‧ directions

C‧‧‧ directions

c‧‧‧During depth

D‧‧‧thickness (direction)

D‧‧‧thickness

E‧‧‧ direction

F‧‧‧ directions

G‧‧‧ directions

H‧‧ Direction

J‧‧‧radiation angle

K‧‧ Direction

L‧‧‧Processing liquid

L‧‧‧cut length

O‧‧ Direction

R‧‧‧ Radius

‧‧‧‧ angle

Σ‧‧‧ horizontal tilt angle

Φ‧‧‧radiation angle

Figure 1 shows an overview of an improved semiconductor wafer with an alignment mark 2 to 8 are schematic views of a method for forming a wafer having a recessed thinned central portion, a ring-shaped frame edge, and a circumferential via hole; and FIG. 2 discloses an outline of a standard semiconductor wafer FIG. 3 is a cross-sectional view showing the semiconductor device after processing according to FIG. 2; and FIG. 4 is a cross-sectional view showing the wafer according to FIG. 3 after cutting the oblique radial extending slot in the circumference of the wafer; 5 is a schematic front view of the wafer according to FIG. 4; FIG. 6 is a cross-sectional view of the upper side of the wafer according to FIG. 4; FIG. 7 is a view showing the wafer according to FIG. FIG. 8 is a schematic cross-sectional view of the wafer according to FIG. 7; FIG. 9 is a schematic cross-sectional view showing a grinding stone for polishing a central portion of a recess; FIG. 10 discloses a modification. A schematic cross-sectional view of a polished stone; FIG. 11 is a schematic perspective view of a through-hole semiconductor wafer; FIG. 12 is a schematic cross-sectional view of the wafer according to FIG. 11; and FIG. 13 is a view showing a wafer having a double recess according to FIG. The central part and a surrounding frame FIG. 14 is a schematic rear view of an improved wafer; FIG. 15 is a schematic rear view of an improved wafer; FIG. 16 is a schematic rear view of an improved wafer; A schematic rear view of an improved wafer; Figure 18 is a schematic cross-sectional view showing the deposition of a sub-layer on the second side of the thinned central portion of the wafer according to Figure 7; and Figure 19 discloses depositing a photoresist layer to the seed according to the wafer of Figure 18. A schematic cross-sectional view of the layer after the layer; FIG. 20 is a schematic cross-sectional view showing the wafer according to FIG. 19 after an exposure step and a development step for processing the opening in the photoresist layer; FIG. 21 discloses that the bump is formed by plating An overview of an electroplating process in the opening of the photoresist layer; FIG. 22 is a schematic view of the wafer according to FIG. 21 after stripping a photoresist mask; and FIG. 23 discloses a crystal according to FIG. A schematic view of the circle after etching the seed layer; FIG. 24 is a schematic cross-sectional view showing the multilayer structure on the second side of the thinned central portion of the wafer; and FIG. 25 is a front view of a wafer support chuck Figure 26 is a schematic cross-sectional view showing the wafer support chuck according to Fig. 25; FIG. 27 is a schematic cross-sectional view showing a wafer support chuck having a vacuum connection structure; and FIG. 28 is a view showing the clip according to FIG. A schematic cross-sectional view of the disk in an upper side down position; Figure 29 reveals the other half FIG. 30 is a schematic cross-sectional view showing the structure of the semiconductor device of FIG. 29; and FIG. 31 is a cross-sectional view showing the structure of the semiconductor device of FIGS. 29 and 30 taken along line A-A. FIG. 32 is a schematic diagram showing the structure of the semiconductor device of FIGS. 29 to 31, and FIG. 33 is a schematic view showing the structure of the semiconductor device of FIGS. 7 and 8 from the outside; FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 35 is a schematic bottom view showing another semiconductor device structure; FIG. 36 is a schematic view showing another semiconductor device structure; FIG. 36 is a schematic view showing the semiconductor device structure of FIG. 35 viewed from the outside; FIG. A schematic top view of a semiconductor device structure; FIG. 38 is a schematic top view showing another semiconductor device structure similar to that of the semiconductor device of FIG. 10; and FIG. 39 is a schematic cross-sectional view showing the structure of the semiconductor device of FIG. 38; FIG. 41 is a schematic top view showing another semiconductor device structure; FIG. 42 is a schematic top view showing another semiconductor device structure; and FIG. 42 is a schematic view showing the semiconductor device structures of FIGS. 37 and 40 taken along a line AA; 43 is a schematic view showing another semiconductor device structure viewed from the outside; FIG. 44 is a schematic view showing another semiconductor device structure viewed from the outside; and FIG. 45 is another semiconductor device. A schematic cross-sectional view of the outer configuration of the observation.

1‧‧‧Ring frame

2‧‧‧ Thin Central

3‧‧‧ first side

4‧‧‧ second side

5‧‧‧ annular edge

6‧‧‧ top surface

7‧‧‧ lower surface

8‧‧‧ outer surface

9‧‧‧ inner surface

10‧‧‧channel (through hole)

11‧‧‧ front surface

12‧‧‧ wafer

15‧‧‧Integrated circuit

31‧‧‧ slot

c‧‧‧During depth

D‧‧‧thickness

D‧‧‧thickness

L‧‧‧cut length

Claims (37)

A wafer (12) having: a thinned central portion (2) having a first side (3) and a second side (4); and at least one reinforcing structure providing at least one channel (10) for supplying a fluid between an inner surface (9) of one of the reinforcing structures and an outer surface (8) of the reinforcing structure and facing the outer surface. The wafer (12) of claim 1, wherein the reinforcement structure increases the radial bending resistance of the wafer (12). The wafer (12) of claim 1 or 2, wherein the channel (10) comprises an inner hole (31'). The wafer (12) of claim 3, wherein the height h of at least a portion of the channel (10) is greater than the thickness d of the thinned central portion (2). A wafer (12) according to claim 1 wherein the reinforcing structure comprises an elevated region on the central portion (2). The wafer (12) of claim 5, wherein the channel (10) comprises a slot (31) that separates at least two of the elevated regions from each other. The wafer (12) of claim 5, wherein the channel (10) comprises a slot (31) disposed in the elevated region. The wafer (12) according to claim 6 or 7, wherein the slot (31) is provided with a spatial positioning, comprising a horizontal tilt angle (σ) at the slot (31) and the wafer (12) Between one of the horizontal directions at the position of the individual slot (31). Such as the wafer (12) described in claim 6 or 7, wherein The slot (31) is provided with a spatial orientation that provides a radial tilt angle j([phi]) at a radial direction of the slot (31) and the wafer (12) at the location of the individual slots (31). between. The wafer (12) according to any one of claims 6 or 7, wherein one of the at least one slot (31) is spatially positioned such that an inner hole (31' of the slot (31) There is no radial overlap between the other outer holes. The wafer (12) of claim 1, wherein the channel (10) comprises a slope (60, 61) disposed at the elevated region. The wafer (12) of claim 1, wherein the first side (3) of the thinned central portion (2) comprises a front surface (11) of a wafer (12). The wafer (12) of claim 1, wherein the first side (3) comprises a plurality of integrated electronic circuits (15) or semiconductor devices. The wafer (12) of claim 1, wherein the second side (4) of the thinned central portion (2) comprises a portion of a back surface (16) of a wafer (12). The wafer (12) according to claim 1, wherein the second side (4) of the thinned central portion (2) comprises a metallization structure (19) or a metallization layer (17). The wafer (12) of claim 1, wherein the second side (4) of the central portion (2) comprises a plurality of metallization structures comprising a plurality of insulating layers (18) located in the metal Between the structures (19), and a plurality of through-contacts passing through the insulating layer (18). The wafer (12) of claim 1, wherein the second side (4) of the central portion (2) comprises a metallization (19) having a bump (20). The wafer (12) according to claim 17, wherein the bump (20) comprises a sub-layer (21) portion and at least one electroplated body of copper or tin alloy covered with another metal, for example Gold, silver or tin. The wafer (12) according to claim 1, wherein the first side (3) and the second side (4) of the thinned central portion (2) comprise a back surface of a wafer (12) (16) and a recessed portion of the front surface (11), wherein each surface (11, 16) comprises a plurality of blocks (13), wherein each block (13) comprises an integrated electronic circuit (15) or a semiconductor Device construction. A chuck for supporting a wafer (12) according to claim 1 of the patent application, comprising a circular substrate (23) surrounded by a chuck frame edge (30), the chuck frame edge ( 30) has a plurality of through holes (24). The chuck of claim 20, wherein the position of the through hole (24) of the chuck frame edge (30) corresponds to at least one position of the channel (10) of the wafer (12). The chuck of claim 20 or 21, wherein the chuck frame edge (30) has a double ring (25) configuration having an inner ring body (26) and an outer ring body (27). The ring bodies (26, 27) are perforated and rotatably arranged to each other to make the profile of the combined through hole size more diverse. The chuck according to claim 20, wherein the through hole (24) of the chuck frame edge (30) is connected to a vacuum container (28) to pass the clip. The through hole (24) of the disk frame edge (30) supports the discharge or split of excess liquid. A method for forming a wafer having a recessed thinned central portion, comprising: - providing a wafer (40) comprising a front surface (11) and a back surface (16); - manufacturing an integrated electronic circuit (15) Or a semiconductor device is constructed on the front surface (11); providing at least one fluid channel (10) around the front surface (11) and extending radially to an outer surface (8) of the wafer (40) And between the inner surface (9) of the wafer (40); - a surface (16) forming a recess after the wafer (40) to provide a thinned central portion (2) having a first One side (3) and one second side (4) are surrounded by at least one reinforcing structure. The method of claim 24, comprising providing a plurality of electrical connection holes between the front surface (11) and the rear surface (16) of the thinned central wafer portion. The method of claim 25, comprising etching or laser ablation of the hole. The method of any one of claims 24 to 26, comprising providing a recess in the surface (16) of the wafer (40) and in the front surface (11) of the wafer (40). To provide a double recessed thinned central portion (29) having a first side (3) and a second side (4). The method of claim 24, wherein the providing the channel (10) comprises cutting the slot by all saw blades (32) (31). The method of claim 28, wherein the cutting height c of the slot (31) is deeper than the thickness d of the thinned central portion (2). The method of claim 28, wherein the cutting is performed at a radial tilt angle. The method of claim 28, wherein the cutting is performed at a horizontal tilt angle. The method of claim 24, wherein the providing the channel (10) comprises dry etching. The method of claim 32, wherein the etching comprises an RIE-plasma etching process. The method of claim 24, wherein the providing the channel (10) comprises wet etching. The method of claim 24, wherein the deposition of a metal or carbon seed layer (21) is used to form a metallization structure or a bump (20) plating structure is implemented in the thinned central portion (2) ) on the second side (4). The method of claim 35, wherein the photoresist layer (35), the developer solution, and the etchant solution are sprayed and spin-coated by diverting or discharging excess liquid through the channel (10). At least one step of washing the cleaning solution, spraying the stripping solution, plating or applying the electrolyte to form the metal or carbon seed layer (21) to form the metallization and/or plate the bump (20). The method of claim 35 or 36, wherein the gold The genus or carbon seed layer (21) is structured and plated into the metallization and/or the bump (20) comprising: - depositing a thin metal or carbon seed layer (21) to the thinned central portion (2) a second side (4); - spraying and spin coating a photoresist layer (35) in the case of discharging excess photoresist through the channel (10); - drying the photoresist layer (35); The dried layer is constructed by exposure through a mask; - the exposed photoresist layer is developed by spraying a developer solution by discharging excess photoresist and excess developer through the channel (10). Dissolving the structured photoresist layer (35) by spraying a washing liquid; discharging the developed photoresist structure into a plating mask; Electroplating the uncovered photoresist layer (21) by recycling the electrochemical seed on the structured seed layer (21) and passing the liquid through the channel (10) in an electrochemical bath Forming a metallization structure and/or a metal bump; - in the case of discharging the excess stripping liquid and the stripped photoresist through the channel (10), the plating mask is sprayed by stripping (36) the photoresist is stripped by the second side (4); - in the case where the excess cleaning liquid is discharged through the channel (10), the stripped structure is cleaned by a cleaning liquid; In the case where excess etching liquid is discharged through the channel (10), The remaining portion of the thin seed layer (21) is wet etched by spraying an etchant; - in the case where the excess washing liquid is discharged through the channel (10), the etched structure is washed by spraying the washing liquid; In the case where excess cleaning liquid is discharged through the passage (10), the second side having the bump is cleaned by the cleaning liquid; and the wafer (12) is dried.