JP2008103433A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase productivity when dividing a wafer, where a plurality of semiconductor device are formed by division with streets, into individual pieces, and to suppress deterioration in quality caused by contamination, surface reforming, or the like. <P>SOLUTION: There are provided: a process of forming a resist 11 covering the outside of a street region on an element formation surface of the wafer 1; a process of performing plasma etching to the wafer 1 from the side of the resist 11 to form a groove 4 in the street region; a process of removing the resist 11 from the wafer 1; and a process of cutting the wafer 1 by a dicing blade 13 in the groove 4 for dividing into each semiconductor device 5. The groove formation by plasma is used together with the cutting, thus increasing the productivity as compared with a conventional method for dividing into individual pieces with plasma only and that for forming two grooves for each street by laser. The groove 4 by the plasma has a tapered shape, cut refuse can be discharged efficiently, and the contamination and the deterioration in quality caused by the cut refuse can be restrained. Heat generation and reforming at a machining section can be restrained as compared with the division by the plasma only. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique for separating a semiconductor device from a wafer.

  Conventionally, as a method of dividing a wafer on which a plurality of semiconductor devices are formed into individual semiconductor devices, the wafer is back-ground to a predetermined thickness, and then cut with a diamond blade along the streets dividing each semiconductor device. The method of dividing is then common. However, in recent semiconductor devices, various composite materials are used for miniaturization and speeding up, and there is a tendency to form multi-layer wiring, and it is difficult to cut and divide a wafer with a diamond blade.

For example, the wiring material tends to shift from an Al-based metal material to a material having high electrical conductivity such as a Cu-based metal material. In addition, the interlayer insulating film tends to move toward a porous material having a low dielectric constant. The conventionally used SiO ₂ or FSG has a Young's modulus of about 70 GPa, whereas the Low- The material referred to as k material is 5 to 15 Gpa and less than one fifth. There are over 10 wiring layers.

  As described above, materials having various physical properties such as Si for substrates, Cu for wiring, and low-k materials for interlayer insulating films have come to be used in multiple layers, making it difficult to cut with a diamond blade. Therefore, problems such as peeling at the cut surface, chipping, and metal burrs due to ductility of the wiring material are occurring.

As a countermeasure against this problem, there is laser grooving. In this method, two narrow grooves are formed in the street by a laser, and the space between the grooves is cut by a diamond blade and divided. Due to the presence of the two thin grooves, stress due to the blade does not act on the wiring layer and the interlayer insulating film, and peeling at the cut surface, chipping, metal burrs, and the like are less likely to occur (Non-Patent Document 1). A method of dividing into pieces by plasma etching has also been proposed. Since a blade is not used, mechanical stress due to this cannot be generated, and metal burrs, peeling, and the like are unlikely to occur (Patent Document 1).
Disco website "http://www.disco.co.jp/jp/solution/library/low_k.html" JP 2006-114825 A

  However, the first dividing method described above requires two steps, that is, a step of forming two grooves with a laser and a step of cutting and dividing with a blade, and each step needs to be processed for each street. , Requires a lot of work time. In particular, when the size of the semiconductor device is small, the number of streets increases, and when the wafer diameter is large, the street length becomes long, so that the working time becomes long and the productivity decreases. In addition, since the groove by the laser is formed in the direction perpendicular to the wafer surface, it is difficult to discharge the cutting waste when cutting between the two grooves with the blade, and the cutting waste is not formed in the step which was the bottom of the groove. If it stays as it is, it will contaminate the semiconductor device, leading to quality degradation in the next process and market.

  In the second dividing method described above, since the dividing is performed only by plasma etching, the production efficiency is lowered depending on the etching rate. Considering an actual plasma etching rate of 2 μm / min, 150 minutes is required for batch division of 300 μm, which is the thickness of a general semiconductor device. According to the dicing blade, even a 300 mm wafer on which a 5 mm square semiconductor device is formed can be divided in several tens of minutes. Further, since a modified layer is generated in the cross section by heat during plasma etching, there is a concern that the single crystallinity of the wafer is impaired and the bending strength of the semiconductor device is lowered.

  In view of the above problems, an object of the present invention is to improve productivity when a semiconductor device is singulated from a wafer and to suppress deterioration in quality due to contamination, surface modification, and the like.

  In order to solve the above-described problems, a method of manufacturing a semiconductor device according to the present invention provides a method of manufacturing a semiconductor device on a device forming surface of a wafer when a plurality of semiconductor devices are divided into streets and divided into individual semiconductor devices. A resist coating step for forming a resist layer covering a region other than the street region, a groove forming step for etching the wafer with plasma from the resist layer side to form a groove in the street region, and the groove formed A resist removing step of removing the resist layer from the wafer and a dividing step of cutting the wafer into a semiconductor device by cutting the wafer with a dicing blade in the groove.

  In the groove forming step, the groove is formed so that a side surface thereof is an inclined surface. The groove formed in the groove forming step is preferably deeper than the semiconductor element formation layer. In the dividing step, it is also preferable to cut and divide the wafer with two types of dicing blades having different blade widths.

  Prior to the resist coating process, a back grinding process can be performed in which the wafer is back ground to a predetermined thickness. Between the resist coating process and the groove forming process, a back grinding process for grinding the wafer to a predetermined thickness can be performed. In this back surface grinding step, a protective tape covering the front surface side may be applied before and after grinding, and the protective tape may be peeled off.

  The semiconductor device of the present invention is a semiconductor device having a semiconductor element formation layer on a silicon substrate, wherein the side surface of the semiconductor device extends from the surface end of the semiconductor element formation layer in an inclined manner with respect to the substrate thickness direction. And a cutting surface extending along the thickness direction of the substrate following the plasma processing surface.

  The plasma processing surface is formed over the side surface of the semiconductor element formation layer and at least a part of the side surface of the silicon substrate. The cutting surface has a step shape.

In the method of manufacturing a semiconductor device according to the present invention, the piece is divided into two steps of groove formation and cutting, and the groove formation is collectively performed by plasma.
For this reason, it is possible to remarkably improve productivity as compared with the conventional method in which the piece division is performed only with plasma. Compared to the conventional method of forming two grooves per street with a laser, the groove formation time is not affected by the increase in the number of streets due to the semiconductor size or the increase in street length due to the large diameter of the wafer, Productivity can be improved.

  Since the groove formed by the plasma has a tapered shape with a wide opening, the cutting waste discharging efficiency in the cutting process is improved and the contamination of the cross section is reduced. In addition, since the calorific value of the processed part can be reduced as compared with the case of dividing only with plasma, the single crystallinity of the wafer is not impaired, and the reduction in the bending strength of the semiconductor device can be suppressed.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a flow of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
First, as shown in FIG. 1A, a resist 11 is formed on the wafer 1 (resist coating step). The wafer 1 is made of Si, and is formed by dividing a plurality of semiconductor devices 5 by streets 3 as shown in FIG. The resist 11 is formed by providing an opening 12 in a portion corresponding to the street 3 on the surface of the semiconductor element formation layer 2 of the wafer 1 (hereinafter referred to as an element formation surface or simply the surface).

  For this purpose, although not shown, a resist film is first formed on the entire surface of the wafer. For this purpose, a general method is a method using a spin coater or the like, which is applied to the entire surface by dropping a resist material while rotating the wafer on a rotary table. An arbitrary film thickness can be obtained depending on the physical characteristics of the resist material, the number of rotations of the rotary table, temperature, and the like. Next, using the light transmittance of the resist film, the street on the surface of the wafer is recognized by a camera or the like, and light such as ultraviolet rays or X-rays is irradiated using a photomask on which a predetermined pattern is written. The resist film is developed. This resist formation method uses a photographic printing method, but is not limited to this method, and a method of directly applying a die-cut resist or a method of exposing by scanning light without using a photomask Etc. may be used.

  Next, as shown in FIG. 1B, grooves 4 are formed on the surface of the wafer 1 (groove forming step). That is, plasma is supplied from the resist 11 side, and the surface layer portion of the wafer 1 corresponding to the opening 12 of the resist 11, that is, the portion corresponding to the street 3 is etched. At this time, the groove 4 is formed into a tapered shape having a wide opening side by using a highly isotropic plasma. The groove 4 is desirably deeper than the semiconductor element formation layer 2 and is at least a depth obtained by adding the etching variation amount to the thickness of the semiconductor element formation layer 2 in consideration of the variation in the in-plane etching amount.

The reason for using plasma is that only the wafer surface can be selectively etched. Chemical etching with a chemical solution or the like requires treatment on the backside of the wafer and the like. As a gas for generating plasma for etching the Si wafer, a commonly used fluorine-based stable gas such as SF ₆ , CF ₄ , C ₂ F ₆ , C ₂ F ₄ , CHF ₃ or the like is used. No special plasma apparatus is required, but a plasma apparatus with a narrow gap between the electrodes that can be applied with a high voltage in order to increase the etching rate is preferable.

When etching was performed using SF ₆ at an applied voltage of 2500 W and a degree of vacuum of 500 Pa (Disco's plasma etcher DFE8060), an etching rate of 1.5 μm / min could be obtained. Since the depth of the semiconductor element forming layer of a general semiconductor device is about 2 μm to 8 μm, when setting the groove depth exceeding the semiconductor element forming layer, for example, 15 μm, the etching is completed by etching for 10 min under the above conditions. It will be.

Next, as shown in FIG. 1C, the resist 11 is removed (resist removing step). There is no particular limitation on the removal method, but generally used processes such as ashing can be used. It is also possible to ash the resist 11 by generating O ₂ plasma or the like having a strong chemical action using the above-described plasma apparatus.

  Next, as shown in FIG. 1D, the wafer 1 is ground by a dicing blade 13 and divided into individual semiconductor devices 5 (dividing step). Cutting waste generated at the time of cutting is removed by supplying cutting water to the blade and the processing part.

  The dividing process will be described in detail. FIGS. 3A and 3B show enlarged states before and after the wafer is divided. As described above, the groove 4 made of plasma has a taper shape with a wide opening and is formed deeper than the semiconductor element formation layer 2. With the formation of the groove 4, the interlayer insulating film and the wiring layer existing in the semiconductor element formation layer 2 in that portion are removed. Therefore, only the Si single crystal as the base material of the wafer 1 is divided by the dicing blade 13 for grinding. Reference numeral 14 denotes a dicing sheet.

  Selection of the dicing blade 13 and setting of conditions for grinding division of such a single material are relatively easy. The blade width W1 of the dicing blade 13 is set in consideration of the amount of kerf, that is, the kerf width W2 is desirably sufficiently narrow so as to be narrower than the groove width W0 of the groove 4 formed by plasma. To do. It is also possible to determine the blade width W1 (and the kerf width W2) first, and then determine the groove width W0 in consideration of productivity such as blade life and stability.

  Since cutting is performed in the tapered groove 4 by such a dicing blade 13, the cutting waste D is quickly washed away by the cutting water, and the discharge efficiency is good. In addition, the dicing blade 13 does not touch mechanically brittle or ductile materials such as an interlayer insulating film and a wiring layer exposed on the inner surface of the groove. Further, since the groove inner surface is an inclined surface, the cutting waste D is easily discharged along the inclined surface, and the attack impact on the interlayer insulating film and the wiring layer due to the collision of the cutting waste D is reduced. In addition to suppressing the quality deterioration, the adhesion of the cutting waste D to the inclined surface and the stagnation in the stepped portion are reduced, and contamination can be suppressed.

  In the semiconductor device 5 after the division, the outer peripheral surface of the surface layer portion is a portion corresponding to the groove 4 described above, an inclined surface extending outward from the surface end portion of the semiconductor element forming layer 2 and extending in the substrate thickness direction, and an upward surface subsequent thereto. Since both are plasma-treated surfaces, there is no cutting trace and it is smooth. Following the upward surface is a dicing portion by the dicing blade 13, which is a surface along the substrate thickness direction, that is, a surface perpendicular to the element formation surface, and has a cutting trace.

  If the groove width W0 is larger than the kerf width W2, the function is achieved. The size of the groove width W0 depends on the opening 12 of the resist 11, and the size does not affect the productivity. Desirably, the divided semiconductor device 5 is formed so wide that the tool for picking up the semiconductor device 5 does not touch the cross section. As a result, the tool can be prevented from coming into contact with the interlayer insulating film and the wiring layer exposed in the cross section, and further quality improvement can be achieved. As the apparatus provided with the dicing blade 13, a dicing apparatus generally used in assembling a semiconductor device (dicing process) can be used.

FIG. 3C shows a state after division by the above-described conventional first division method for comparison. Cutting waste D tends to accumulate in the stepped portion.
As described above, according to the first embodiment of the present invention, the groove 4 is formed on the surface portion of the wafer 1 and the other portions are cut into two pieces, and the groove 4 is formed by plasma. This is done in a lump. The same applies to each manufacturing method described later.

  By doing in this way, it is possible to improve productivity significantly compared with the conventional method which divides | segments an individual piece only with plasma. Further, since the calorific value of the processed portion can be reduced as compared with the case of dividing only with plasma, the single crystallinity of the wafer 1 is not impaired, and the reduction of the bending strength of the semiconductor device 5 can be suppressed. Compared to the conventional method in which two grooves are formed for each street with a laser, the groove formation time is not affected by the increase in the number of streets due to the semiconductor size or the increase in street length due to the increase in wafer diameter. , Improve productivity. Furthermore, since the groove 4 formed by plasma has a tapered shape with a wide opening, the discharge efficiency of the cutting waste D in the cutting process can be improved, contamination of the cross section can be reduced, and the interlayer of the cutting waste D can be reduced. It is possible to suppress deterioration in quality caused by attack impact on the insulating film and the wiring layer.

A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 4A, the back surface of the wafer 1 is polished (back surface polishing step). This back surface polishing is performed by an infeed method using a grindstone generally used for this type of wafer back surface polishing until the wafer 1 has a predetermined thickness.

Thereafter, the resist coating process, the groove forming process, the resist removing process, and the dividing process are performed in the same manner as in the first manufacturing method described above.
The backside polishing step is performed because the process time can be shortened by the reduction in wafer thickness. Thus, the method of performing resist coating after the backside polishing is suitable when the final thickness of the semiconductor device is 150 μm or more. When the final apparatus thickness is less than 150 μm, that is, when the wafer 1 is polished to less than 150 μm, the wafer 1 may be warped and the resist 11 may not be applied stably.

A method of manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 5A, a resist 11 is formed on the wafer 1 (resist coating step). What is necessary is just to carry out similarly to the above-mentioned 1st manufacturing method.

  Next, as shown in FIG. 5B, the back surface of the wafer 1 is polished (back surface polishing step). What is necessary is just to carry out similarly to the above-mentioned 2nd manufacturing method. The reason why the resist coating is performed before the backside polishing is that the resist 11 can be applied accurately and stably.

Thereafter, the groove forming step, the resist removing step, and the dividing step are performed in the same manner as in the first manufacturing method described above.
If the resist 11 has poor shape stability and it is necessary to polish the wafer to less than 150 μm, the second manufacturing process described above is performed by taking a warp suppressing measure such as bonding the back surface of the wafer to a glass substrate or the like. A resist coating may be performed after the back surface polishing as in the method. This is a method that causes an increase in the number of processes.

In the dividing step, two types of dicing blades having different blade widths may be used. FIGS. 6A, 6B, and 6C show enlarged states before, during, and after the wafer division.
The wafer 1 is half-cut by the first dicing blade 13A in the groove 4 and cut by the second dicing blade 13B in the groove 4 'formed thereby, so that the wafer 1 is divided into individual semiconductor devices 5. .

  The blade width of the dicing blades 13A and 13B to be used is set so that the kerf width is narrower than the width of the groove formed first. That is, the blade width W11 of the dicing blade 13A is selected so that the kerf width W21 is narrower than the width W0 of the groove 4 by plasma, and the blade width 21 of the dicing blade 13B is larger than the width of the groove 4 ′ by the dicing blade 13A. Also, the kerf width W22 is selected to be narrow. It is desirable to use a dicing apparatus called a dual dicing saw to which two types of dicing blades can be attached.

  When the cutting division is performed in two stages in this way, the ratio of the wafer thickness to the kerf width is very large, and even if the cutting scraps are likely to remain in the processing portion or the vicinity thereof, the cutting scraps D are formed into the grooves 4 by cutting water. 4 'can be discharged efficiently from the large opening. In addition, since the amount of cutting at the first stage is reduced, the amount of cutting waste D is reduced, and the possibility of collision of the cutting waste D with the side surface of the wiring layer is reduced. Since the distance increases, the possibility of collision of the cutting waste D becomes smaller. The groove 4 needs to have a tapered shape for the reason described above, but the groove 4 'and the subsequent cutting groove are formed in the Si single crystal portion, so it is necessary to consider the attack of the cutting waste D on the inner surface of these grooves. There is no problem because it becomes a wall surface in the thickness direction of the substrate.

  In the semiconductor device 5 after the division, the outer peripheral surface of the surface layer portion is a portion corresponding to the groove 4 described above, an inclined surface extending outward from the surface end portion of the semiconductor element forming layer 2 and extending in the substrate thickness direction, and an upward surface subsequent thereto. Since both are plasma-treated surfaces, there is no cutting trace and it is smooth. Following the upward surface is a dicing portion by the dicing blades 13A and 13B, a surface along the thickness direction of the substrate (that is, a surface perpendicular to the element formation surface), an upward surface that follows, and a subsequent substrate thickness. It is a surface along the direction and has a stepped shape, each with a cutting mark.

  The present invention is particularly useful for manufacturing a semiconductor device in which a composite material is used to form a multilayer wiring for miniaturization and speeding up.

The flowchart of the manufacturing method of the semiconductor device in the 1st Embodiment of this invention 1 is a perspective view of a conventional type wafer on which the semiconductor device of FIG. 1 is formed. Sectional drawing of the process of dividing | segmenting the semiconductor device of FIG. 1 from a wafer. Flowchart of a method for manufacturing a semiconductor device according to a second embodiment of the present invention Flowchart of a semiconductor device manufacturing method according to the third embodiment of the present invention Sectional drawing of the other process which divides each said semiconductor device from a wafer

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wafer 2 Semiconductor element formation layer 3 Street 4 Groove 5 Semiconductor device
11 resist
13 Dicing blade
13A, 13B dicing blade

Claims (9)

  A resist coating step of forming a resist layer covering a portion other than the street region on an element formation surface of the wafer when dividing a wafer formed by dividing a plurality of semiconductor devices by streets into individual semiconductor devices; and the wafer Forming a groove in the street region by etching with plasma from the resist layer side, a resist removing step of removing the resist layer from the wafer on which the groove is formed, and removing the wafer from the groove A semiconductor device manufacturing method for performing a dividing step of cutting into a semiconductor device by cutting with a dicing blade.   2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the groove forming step, the groove is formed so that a side surface thereof is an inclined surface.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the groove formed in the groove forming step is deeper than the semiconductor element forming layer.   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the dividing step, the wafer is cut and divided by two kinds of dicing blades having different blade widths.   2. The method of manufacturing a semiconductor device according to claim 1, wherein a back grinding process for grinding the wafer to a predetermined thickness is performed prior to the resist coating process.   2. The method of manufacturing a semiconductor device according to claim 1, wherein a back grinding process for grinding the wafer to a predetermined thickness is performed between the resist coating process and the groove forming process.   In the semiconductor device having a semiconductor element forming layer on a silicon substrate, the side surface of the semiconductor device includes a plasma processing surface extending from the surface end of the semiconductor element forming layer with an inclination to the substrate thickness direction, and the plasma processing surface And a cutting surface extending along the substrate thickness direction.   8. The semiconductor device according to claim 7, wherein the plasma processing surface is formed over the side surface of the semiconductor element formation layer and at least a part of the side surface of the silicon substrate.   8. The semiconductor device according to claim 7, wherein the cutting surface has a step shape.

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