JP2010093187A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor integrated circuit device that reduces production of foreign matter, has high throughput, and is inexpensive. <P>SOLUTION: In the method of manufacturing the semiconductor integrated circuit device, resist 20 is patterned on a semiconductor substrate 11 where a semiconductor circuit 12 is formed by a nano-imprint method so as to form an opening in a scribe area S using a stamper 30. Then the semiconductor substrate 11 is etched using the resist 20 patterned on the semiconductor substrate 11 as a mask, and then the resist 20 is removed from the semiconductor substrate 11. Then the semiconductor substrate 11 having the resist 20 removed is fixed on a stage, and the semiconductor substrate 11 is diced through stealth dicing using a laser. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and in particular, a semiconductor integrated circuit device that is used when manufacturing a microdevice such as a semiconductor element, a liquid crystal display element, an image pickup element (CCD: Charge Coupled Device) or a thin film magnetic head. The present invention relates to a dicing method.

  Conventionally, a blade dicing method using a blade is generally used as a method of dicing a semiconductor integrated circuit formed on a semiconductor substrate to process each semiconductor chip. However, since this method applies mechanical stress to the semiconductor substrate, there is a possibility that the glass coat film for protecting the semiconductor element may crack. In addition, since chips come out from the blade, they adhere to the semiconductor element and become foreign matter, leading to a decrease in yield. Furthermore, since heat is generated due to friction at the time of cutting, which may affect the product, it was necessary to perform dicing while supplying water to the cutting point. This cutting water may enter the electrode surface of the semiconductor integrated circuit, causing a defect. As described above, blade dicing has many elements that cause defects in the semiconductor integrated circuit device.

  In recent years, laser dicing using a laser having a wavelength that passes through a semiconductor substrate has begun to spread. This method is a method of scanning a dicing line of a semiconductor substrate while irradiating a laser, and is called stealth dicing. The laser is focused so as to focus on the inside of the silicon crystal of the semiconductor substrate. Since silicon is melted and cooled and the crystal changes into an amorphous structure only inside the substrate, there is no damage to the surface layer. Further, a strong compressive stress is generated due to volume expansion accompanying local amorphization. Since very strong tensile stress is concentrated at the upper and lower ends of the amorphous layer, it can be easily cleaved by applying external stress to the semiconductor substrate. Compared with the blade dicing method, this method is advantageous in that no chips are generated and that no cutting water is required. However, when there is a fine pattern on the dicing line, there remains a possibility that foreign matters are generated by chipping.

  Therefore, it is necessary to remove the fine pattern on the dicing line in advance. The surface of the semiconductor substrate is scanned with a laser having a wavelength that does not pass through the semiconductor substrate to remove a TEG (Test Element Group) pattern or the like that is a source of foreign matter. Thereafter, a laser having a wavelength that transmits the semiconductor substrate is irradiated to the inside of the semiconductor substrate on the dicing line to cleave. This method is called double laser dicing.

  FIG. 12 is a cross-sectional view illustrating a method of cleaving a semiconductor substrate by double laser dicing. FIG. 12A is a diagram showing, for comparison, a case where laser irradiation is performed without removing a fine pattern such as TEG present in the scribe region S. FIG. As shown in FIG. 12A, when the semiconductor substrate 11 is cleaved, if a fine pattern such as the TEG 13 remains on the dicing line 14, it is chipped into small foreign matters. If the foreign matter adheres to the semiconductor integrated circuit 12, it causes a short circuit and the chip becomes a defective product.

  As shown in FIG. 12B, in the double laser dicing, the first laser irradiation is performed on the surface of the semiconductor substrate 11 before performing the laser irradiation using stealth dicing. Then, a fine pattern such as TEG 13 existing in the scribe region S is removed.

Patent Document 1 discloses a prior art document that discloses a method for manufacturing a semiconductor integrated circuit device in which a fine pattern on a dicing line is removed with a blade and then stealth dicing is performed. In the method disclosed in Patent Document 1, TEG and the like formed on a dicing line are removed with a rotating blade. Thereafter, a laser is irradiated to the inside of the semiconductor substrate on the dicing line.
JP 2006-287271 A

  In double laser dicing, as shown in FIG. 12B, since the first laser irradiation is ablation, fine cracks 16 are generated on the substrate surface after the fine pattern is removed. The fine crack 16 may extend to the semiconductor integrated circuit 12 when the semiconductor substrate 11 is cleaved. In order to prevent this, it is necessary to form the groove 15 between the fine crack 16 and the semiconductor integrated circuit 12. By forming the groove 15, the extension direction of the crack changes to the internal direction of the substrate, so that it is possible to prevent the crack from extending to the semiconductor integrated circuit 12 when cleaving.

  Double laser dicing requires three times of laser irradiation for one dicing as described above. If the TEG 13 in the scribe region S is avoided and the zigzag is irradiated with the laser, it is necessary to control the complicated stage, and the irradiation time becomes long, resulting in a decrease in throughput. In addition, since the first laser irradiation performed on the surface of the substrate removes TEG and the like by ablation, a substance scattered from the surface may become a foreign substance. Furthermore, it is necessary to provide a predetermined safety interval between the semiconductor integrated circuit region and the laser irradiation unit so that the heat of the laser irradiation unit does not affect the characteristics of the semiconductor integrated circuit device. Therefore, there is a problem that the number of products that can be obtained from one semiconductor substrate is reduced.

  In the method of manufacturing a semiconductor integrated circuit device described in Patent Document 1, the TEG on the dicing line is removed by a rotating blade. If the foreign matter generated at this time adheres to the semiconductor integrated circuit, the yield of the product cannot be improved even if cleaving is performed by subsequent stealth dicing to prevent chipping.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an inexpensive method for manufacturing a semiconductor integrated circuit device with reduced generation of foreign matter, high throughput, and low cost.

  A manufacturing method of a semiconductor integrated circuit device according to the present invention includes the following steps. A resist is applied on the semiconductor substrate on which the semiconductor integrated circuit is formed. On the semiconductor substrate coated with the resist, a stamper having a protrusion is pressed at a position facing a scribe region including a dicing line of the semiconductor substrate. When the stamper is pressed, the resist is exposed and / or heated. The stamper is peeled off and the resist is developed. The semiconductor substrate is etched using the resist patterned on the semiconductor substrate as a mask. The resist is removed from the etched semiconductor substrate. The semiconductor substrate from which the resist has been removed is fixed on a stage. A laser focal point is set inside the semiconductor substrate fixed on the stage. The stage is moved to irradiate the laser on the dicing line of the semiconductor substrate. The semiconductor substrate irradiated with the laser is cleaved.

  According to this method of manufacturing a semiconductor integrated circuit device, the TEG pattern and the like in the scribe region are removed by etching while the semiconductor integrated circuit is protected by the resist. In this state, since stealth dicing is performed and the semiconductor substrate is cleaved, generation of foreign matters due to chipping can be reduced.

  In the method for manufacturing a semiconductor integrated circuit device, the resist may be formed of a material having thermoplasticity. In this case, the stamper is pressed while the resist is heated and softened. Thereafter, the stamper is peeled off while the resist is cooled and cured.

  In the method for manufacturing a semiconductor integrated circuit device, the resist may be formed of a photocurable material. In this case, the resist is exposed and cured while the stamper is pressed. The stamper is peeled off from the cured resist, and the resist is developed.

  In the method for manufacturing the semiconductor integrated circuit device, the resist may be formed of a material having photocurability and thermoplasticity. In this case, the stamper is pressed while the resist is heated and softened. With the stamper pressed, the resist is exposed and cured. The stamper is peeled off from the cured resist, and the resist is developed.

  In the method for manufacturing the semiconductor integrated circuit device, the pattern density may be made uniform by forming a dummy pattern in the scribe region on the semiconductor substrate. Furthermore, the optimum pressure when pressing the stamper on the semiconductor substrate may be controlled by calculating the pattern density. When calculating the pattern density, the area of the pattern and the line integral of the pattern edge may be included as factors.

  In the semiconductor substrate in which a dummy shot is arranged on the outer peripheral portion of the semiconductor substrate and the semiconductor integrated circuit is formed on the entire surface, the step of pressing the stamper includes the step of pressing a stamper smaller than the semiconductor substrate. It is also possible to press the entire surface of the semiconductor substrate while sequentially shifting the pressing position so as to correspond to the position where the is formed. In the step of etching the semiconductor substrate, isotropic etching may be performed.

  According to the present invention, it is possible to provide an inexpensive method for manufacturing a semiconductor integrated circuit device with reduced generation of foreign matter, high throughput, and low cost.

One Embodiment of Manufacturing Method of Semiconductor Integrated Circuit Device In a manufacturing method of a semiconductor integrated circuit device, first, a plurality of semiconductor integrated circuits in which circuits are integrated on a semiconductor substrate such as a silicon wafer are formed. Next, dicing is performed to divide the silicon wafer into individual semiconductor integrated circuit devices. Each of the divided semiconductor integrated circuit devices is electrically connected to an external terminal provided on the base material by die-bonding to the base material. Thereafter, the semiconductor integrated circuit device is sealed with resin or the like to be assembled as a semiconductor package. The present invention particularly relates to a dicing method for dividing the semiconductor integrated circuit device into individual semiconductor integrated circuit devices.

  A semiconductor substrate dicing method according to an embodiment of the present invention will be described below with reference to the drawings.

Embodiment 1
FIG. 1 is a cross-sectional view showing a method of providing an opening in a resist on a semiconductor substrate using a nanoimprint method according to Embodiment 1 of the present invention. First, as shown in FIG. 1A, a semiconductor device 10 in which a semiconductor integrated circuit 12 is formed on an upper portion of a semiconductor substrate 11 is prepared. In a scribe region S formed between the semiconductor integrated circuits 12 adjacent to each other, a fine pattern such as a TEG 13 for process monitoring is provided. TEG is an evaluation circuit for each process included in the semiconductor substrate process.

A resist 20 is applied to the entire upper surface of the semiconductor device 10. The resist 20 can be made of a thermoplastic material such as polymethyl methacrylate or a photocurable material such as an epoxy resin. The stamper 30 is disposed so as to face the semiconductor device 10. The stamper 30 has a convex portion at a position corresponding to the scribe region S of the semiconductor device 10 and a concave portion at a position corresponding to the semiconductor integrated circuit 12. As the stamper 30, a Si substrate or a SiO ₂ layer of a SiO ₂ / Si substrate having a pattern formed thereon or a transparent quartz substrate having a pattern formed thereon can be used.

  Next, as shown in FIG. 1B, a stamper 30 is pressed onto the upper surface of the resist 20. When using a material having thermoplasticity for the resist 20, the stamper 30 is pressed in a state where the resist 20 is heated and softened. Thereafter, in a state where the resist 20 is cooled and cured, the stamper 30 is peeled off to form a pattern on the resist 20. This method is called thermal cycle nanoimprint, and a structure of the order of 10 nm can be formed on the resist 20 having a large area.

  Further, when using a photo-curing material for the resist 20, the stamper 30 is exposed and cured by ultraviolet light or the like in a state where the stamper 30 is pressed on the low-viscosity resist 20, and then the stamper 30 is removed. The resist 20 is developed by peeling. In this case, since the stamper 30 needs to be light transmissive, a transparent quartz substrate or the like is used. This method is called optical nanoimprinting and is performed by imprinting, so that the pattern of the stamper 30 can be transferred with high accuracy without being affected by light diffraction. The resist 20 may be formed of a material having photocurability and thermoplasticity, such as methyl methacrylate resin (PMMA). In this case, the stamper 30 is pressed while the resist 20 is heated and softened. In this state, the resist 20 is exposed and cured, and then the stamper 30 is peeled off to develop the resist 20.

  For details of the nanoimprint method, for example, “Special feature“ Frontier of Micro / Nano Processing Technology ”of Surface Science Vol. 25, No. 10, pp 628-634, 2004” (hereinafter referred to as “Reference A”). It is described in.

  Next, as shown in FIG. 1C, the semiconductor device 10 is etched using the resist 20 on which the pattern is formed as a mask. Etching may be performed by either dry etching or wet etching. The semiconductor integrated circuit 12 covered with the resist 20 remains, but the fine pattern such as the TEG 13 existing in the scribe region S not covered with the resist 20 is removed, and the opening K is formed. This etching may be isotropic etching. When isotropic etching is performed, the lower portion of the fine pattern can also be etched, so that the fine pattern existing in the scribe region S can be sufficiently removed. After the etching, the resist 20 is removed with a solvent or the like.

  In Embodiment 1 of the present invention, for example, the nanoimprint apparatus described in Reference Document A can be used. FIG. 2 is a schematic diagram showing the structure of the nanoimprint apparatus according to Embodiment 1 of the present invention. As shown in FIG. 2A, the nanoimprint apparatus 200 includes an optical fiber 209, a lens 201, a sapphire window 208, a stamper 202, a substrate holder 205, a base plate 207, a load cell 210, a ball screw 211, and a stepping motor in order from the top. 212, a guide pole 213, and the like. The substrate holding unit 205 includes an elastic body 204 that supports a substrate 203 coated with a resist, pins 206, and the like.

  FIG. 2B is an enlarged view of the light irradiation unit 220. As shown in FIG. 2B, a Teflon (registered trademark) sheet 214 is disposed between the substrate 203 and the elastic body 204. The nanoimprint apparatus 200 can perform both optical nanoimprint and thermal cycle nanoimprint. When using a photo-curing resin for the resist, it is cured by irradiating with ultraviolet light through the upper sapphire window 208. When a thermoplastic resin is used for the resist, it is performed by heating a heater below the substrate holding unit 205. The stamper 202 is attached to the sapphire window 208, and the stamper 202 is pressed when the substrate 203 coated with resist moves upward.

When the stamper 202 and the substrate 203 are in contact with each other, bubbles in the air are taken into the resin and the pattern may be deteriorated. Therefore, the imprinting can be performed in a vacuum atmosphere. The load at the time of imprinting is measured by the load cell 210. A high-pressure mercury lamp is used as the ultraviolet light source. The wavelength of this light source is 300 nm to 400 nm. It is possible to irradiate a range of 1 cm ² through the guide of the optical fiber 209.

  FIG. 3 is a schematic diagram showing a state where laser scanning is performed on the semiconductor substrate by stealth dicing according to the first embodiment of the present invention. Laser irradiation using stealth dicing is performed with the semiconductor substrate fixed on a stage. A laser focus 300 is set inside a semiconductor substrate fixed on the stage. The stage is moved to irradiate the laser on the dicing line of the semiconductor device 10. By dividing the semiconductor substrate irradiated with the laser, the semiconductor substrate is divided into individual semiconductor integrated circuit devices (semiconductor chips).

  As shown in FIG. 3, since the nonlinear absorption effect is generated only at the focal point 300 inside the semiconductor substrate, the front and back surfaces of the semiconductor device 10 are not damaged. Dicing is realized by scanning the relative position between the laser beam and the semiconductor substrate at a high speed by a moving mechanism such as a stage in accordance with the dicing pattern.

  FIG. 4 is a cross-sectional view illustrating a method for cleaving a semiconductor substrate by stealth dicing according to Embodiment 1 of the present invention. FIG. 4A is a diagram showing a case where laser irradiation is performed without removing a fine pattern such as TEG present in the scribe region S for comparison with the embodiment of the present invention. As shown in FIG. 4A, when the semiconductor substrate 11 is cleaved, if a fine pattern such as the TEG 13 remains on the dicing line 14, it is chipped into small foreign matters. If the foreign matter adheres to the semiconductor integrated circuit 12, it causes a short circuit and the chip becomes a defective product.

  FIG. 4B is a diagram showing an embodiment of the present invention, in which etching is performed before laser irradiation using stealth dicing to remove a fine pattern such as TEG present in the scribe region S. It is. As shown in FIG. 4B, since there is no fine pattern that causes chipping on the dicing line 14, the semiconductor substrate 11 can be cleaved while preventing the generation of foreign matter. Therefore, the yield of products can be improved.

  In double laser dicing, as described above, three times of laser irradiation are required for one dicing, so that the laser irradiation time becomes longer. When the nanoimprint method is used, the stamper 30 corresponding to the semiconductor device 10 may be pressed once, so that the throughput can be significantly improved.

  FIG. 5 is a diagram showing a method for cleaving a semiconductor substrate according to the first embodiment of the present invention. The semiconductor device 10 in which the amorphous layer is formed on the dicing line by stealth dicing is cleaved by pressing it against the cleaving die 40 having an arc shape on the upper portion to obtain individual chip-like semiconductor integrated circuit devices.

  FIG. 6 is a plan view showing a distribution of semiconductor integrated circuits formed on the semiconductor substrate. One square in the figure represents one semiconductor integrated circuit. FIG. 6A is a plan view showing a state in which the distribution of the semiconductor integrated circuits on the semiconductor substrate has symmetry. As shown in FIG. 6A, when semiconductor integrated circuits are symmetrically arranged on a semiconductor substrate, the pressing force distribution when pressing the stamper 30 on the resist on the semiconductor substrate is made uniform. Can do. However, in this case, chipping occurs in the eight semiconductor integrated circuit devices indicated by oblique lines in the figure, so that only 32 normal semiconductor integrated circuit devices can be taken.

  FIG. 6B is a plan view showing a state where the distribution of the semiconductor integrated circuit on the semiconductor substrate has lost symmetry. As shown in FIG. 6B, by shifting the position of the semiconductor integrated circuit with respect to the semiconductor substrate, a semiconductor integrated circuit device in which chipping occurs compared to the arrangement of the semiconductor integrated circuit shown in FIG. Can be reduced by two. As a result, the yield of the semiconductor integrated circuit device can be improved by 6.25%. Instead, since the symmetry of the arrangement of the semiconductor integrated circuit in the entire semiconductor substrate is broken, the pressing force distribution when the stamper 30 is pressed onto the resist on the semiconductor substrate becomes non-uniform, and the stamper 30 is inclined and pressed. Is done. In order to uniformly press the stamper 30 onto a resist on a semiconductor substrate having a diameter of 300 mm with an alignment accuracy of 0.1 microns or less, it is not sufficient to hold the stamper 30 straight. Accordingly, the dummy shot described below is used to make the pattern density on the semiconductor substrate uniform.

  FIG. 7 is a diagram for explaining a method of pressing a stamper on a semiconductor substrate on which a semiconductor integrated circuit is formed on the entire surface by arranging dummy shots according to the first embodiment of the present invention. One square in FIG. 7A corresponds to one shot of the mask pattern when the pattern of the semiconductor integrated circuit 100 is transferred to the semiconductor substrate. In the present embodiment, nine semiconductor integrated circuits 100 are included in one shot, but the present invention is not limited to this. As shown in FIG. 7A, normally, the semiconductor integrated circuit 100 is formed in a range indicated by a hatched portion in the drawing excluding the outer peripheral portion of the semiconductor substrate. In this case, an empty area where the semiconductor integrated circuit 100 is not patterned is formed in the outer periphery of the semiconductor substrate. A semiconductor integrated circuit device cannot be obtained from this empty area. Therefore, in order to reduce this empty area, the position of the hatched portion is shifted in the horizontal and vertical directions of the semiconductor substrate. That is, in order to form the largest number of semiconductor integrated circuit devices, the semiconductor integrated circuit 100 is formed by shifting the arrangement in the horizontal direction and the vertical direction. Therefore, the pattern on the semiconductor substrate is often formed asymmetrically in the left-right and up-down directions, and the pattern density becomes non-uniform when viewed over the entire surface of the semiconductor substrate.

  When the stamper 30 is pressed onto the resist on the semiconductor substrate in this state, the pressing force distribution becomes non-uniform and it is difficult to maintain alignment accuracy. Therefore, the dummy shot 70 is arranged on the outer periphery of the semiconductor substrate so that the semiconductor integrated circuit 100 is formed on the entire surface of the semiconductor substrate. In this case, since the pattern density is uniform over the entire surface of the semiconductor substrate, the stamper 30 can be pressed against the entire surface of the resist on the semiconductor substrate with a uniform pressing force.

  As shown in FIG. 7B, the stamper 30 having a pressing surface smaller than the entire surface on the semiconductor substrate may be used to press the semiconductor integrated circuit 100 so as to correspond to the position. The pressing is performed so that the stamper 30 and the semiconductor substrate are pressed over the entire surface of the semiconductor substrate while sequentially shifting the relative positions thereof. Specifically, the semiconductor device 10 is inserted into the holder 50 and held. At this time, the heights of the upper surfaces of the semiconductor device 10 and the holder 50 are made to coincide with each other and are held so that no gap is generated on the side surfaces. By doing so, the stamper 30 can be pressed at a position corresponding to the semiconductor integrated circuit 100 formed by the dummy shot 70 with a uniform pressing force distribution. As a result, variation in the etching effect can be reduced, and the defect rate during dicing can be reduced. Further, the number of semiconductor integrated circuit devices obtained from one semiconductor substrate is increased, and the yield can be improved.

  FIG. 8 is a diagram showing an example of a mask pattern for forming a pattern on a semiconductor substrate, to which the present embodiment is applied. As shown in FIG. 8, a semiconductor integrated circuit 100, a TEG 103, an alignment mark 104, and a dummy pattern 105 are formed on the mask pattern 60. Usually, since the alignment mark 104 is arranged at the corner portion of the mask pattern 60, the TEG 103 cannot be arranged at the corner portion, and the uniformity of the arrangement of the TEG 103 cannot be maintained. By arranging the dummy pattern 105 at the position shown by the oblique lines in FIG. 8, the pattern density in the mask pattern can be made uniform. FIG. 9 is a diagram showing an example of a floor plan of the semiconductor integrated circuit 100 to which the present embodiment is applied. As shown in FIG. 9, a module region 101 is formed inside, and a scribe region 102 is formed at the end. Usually, since various modules exist in the module area 101, the pattern arrangement is non-uniform. As shown in FIGS. 8 and 9, when the pattern arrangement is not uniform, for example, the present inventor has disclosed Japanese Patent Laid-Open Nos. 2005-128395, 2004-117474, and 2004-259830. And a method related to a pattern density evaluation method and a dummy pattern generation method proposed in Japanese Patent Laid-Open No. 2002-31882. As a result, it is possible to make the pattern density uniform by forming a dummy pattern in the scribe region 102.

  FIG. 10 is a diagram for explaining the optimum pressure when the stamper is pressed onto the resist on the semiconductor substrate according to the first embodiment of the present invention. The stamper 30 shown in FIG. 10A has four protrusions 31 of the stamper 30 that form recesses in the resist 20. On the other hand, two protrusions 32 are formed on the stamper 30 shown in FIG. The force applied when the stamper 30 is pressed onto the resist 20 requires a load twice as large when there are four convex portions as compared with when there are two convex portions. That is, the force applied when pressing the stamper 30 onto the resist 20 is proportional to the pattern density. Therefore, if the pattern density of the stamper 30 is calculated in advance, the optimum pressure can be set in advance. If the pressing load is insufficient for the optimum pressure, a pattern cannot be sufficiently formed on the resist 20. Further, when the load is larger than the optimum pressure, the semiconductor device is cracked or chipped. For example, as described in Reference Document A above, the pressing pressure when pressing the quartz stamper 30 onto the resist 20 is 5 to 10 MPa in the case of thermal cycle nanoimprint and 0.1 MPa in the case of optical nanoimprint.

  FIG. 11 is a diagram for explaining the optimum pressure when the stamper is pressed onto the resist on the semiconductor substrate according to the first embodiment of the present invention. The stamper 30 shown in FIG. 11A is provided with four convex portions 33 of the stamper 30 that form concave portions in the resist 20. On the other hand, two protrusions 34 are formed on the stamper 30 shown in FIG. The two stampers 30 have the same area in which the resist 20 is recessed. However, as shown in FIG. 11B, the number of pattern edges 21 formed on the resist 20 is twice the number of pattern edges 22 shown in FIG. Considering the influence of the viscosity and elasticity of the resist 20, the load applied when the stamper 30 is pressed onto the resist 20 varies depending on the density of the edges. Therefore, the optimum pressure can be obtained by calculating the pattern density by performing line integration of the pattern area using the height of the pattern edge as a factor. As for the detailed method, for example, the inventor proposed the pattern density proposed in Japanese Patent Application Laid-Open Nos. 2005-128395, 2004-117474, 2004-259830, and 2002-31882. Techniques relating to the evaluation method and the dummy pattern generation method can be used.

Embodiment 2
In the present invention, as a method of patterning a resist on a semiconductor substrate so as to form the opening K in the scribe region S, there is a method other than the nanoimprint method such as a photolithography method. For example, in the photolithographic method, instead of the stamper 30 shown in FIG. By these methods, etching is performed using the resist 20 patterned on the semiconductor substrate as a mask. As a result, a fine pattern such as TEG present on the scribe region S is removed.

  Usually, laser irradiation by stealth dicing is performed from the back surface of a semiconductor substrate. This is because if a fine pattern such as TEG 13 is present in the scribe region S, the laser beam is scattered and the focus 300 is not well matched. The semiconductor device 10 according to the second embodiment of the present invention is etched using a resist patterned by a photolithography method as a mask so as to form an opening in a region corresponding to the region corresponding to the scribe region S before laser irradiation. As a result, the fine pattern in the scribe region S is removed. Therefore, even if laser irradiation is performed from the surface of the semiconductor substrate, stealth dicing by irradiating the set focal point 300 with laser can be realized. In this case, when the semiconductor substrate 11 is fixed on the stage, the semiconductor integrated circuit 12 can be set on the stage with the top surface thereof. Since laser irradiation can be performed without bringing the semiconductor integrated circuit 12 into contact with the stage, it is possible to prevent the semiconductor integrated circuit 12 from being attached with scratches, dust, and the like, and to prevent the generation of defective products.

  The steps in Embodiment 2 of the present invention are as follows. When dicing the semiconductor integrated circuit device, the semiconductor substrate 11 is etched using the resist 20 patterned on the semiconductor substrate 11 by photolithography as a mask. The resist 20 is removed from the etched semiconductor substrate 11. The semiconductor substrate 11 from which the resist 20 has been removed is fixed on the stage. A laser focus 300 is set inside the semiconductor substrate 11 fixed on the stage. The stage is moved, and laser is irradiated onto the dicing line 14 of the semiconductor substrate 11 from the surface side of the semiconductor substrate 11. The semiconductor substrate 11 irradiated with the laser is cleaved.

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is sectional drawing which showed the method of providing an opening part in the resist on a semiconductor substrate using the nanoimprint method based on Embodiment 1 of this invention. It is a schematic diagram which shows the structure of the nanoimprint apparatus based on the embodiment. It is a schematic diagram which shows the state which is performing the laser scan to the semiconductor substrate by the stealth dicing based on the embodiment. (A) is the figure which showed the case where laser irradiation was performed without removing fine patterns, such as TEG which exists in a scribe area | region, for the comparison with embodiment of this invention, (B). FIG. 3 is a diagram in which etching is performed before laser irradiation using stealth dicing according to Embodiment 1 of the present invention to remove a fine pattern such as TEG present in a scribe region. It is the figure which showed the method of cleaving a semiconductor substrate based on Embodiment 1 of this invention. (A) is the top view which showed the state where distribution of the semiconductor integrated circuit on a semiconductor substrate has symmetry, (B), the distribution of the semiconductor integrated circuit on a semiconductor substrate loses symmetry FIG. It is a figure explaining the method which presses a stamper to the semiconductor substrate which arranged the dummy shot based on Embodiment 1 of this invention, and the semiconductor integrated circuit was formed in the whole surface. It is the figure which showed an example of the mask pattern which forms a pattern in the semiconductor substrate used as the object to which this Embodiment is applied. It is the figure which showed an example of the floor plan of the semiconductor integrated circuit used as the object to which this Embodiment is applied. It is a figure explaining the optimal pressure at the time of pressing a stamper to the resist on a semiconductor substrate based on Embodiment 1 of this invention. It is a figure explaining the optimal pressure at the time of pressing a stamper to the resist on a semiconductor substrate based on the embodiment. (A) is the figure which showed the case where laser irradiation was performed, without removing fine patterns, such as TEG which exists in a scribe area | region, for comparison, (B) is laser irradiation using stealth dicing. FIG. 2 is a diagram in which double laser dicing is performed before performing a step to remove a fine pattern such as a TEG existing in a scribe region.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Semiconductor device, 11 Semiconductor substrate, 12,100 Semiconductor integrated circuit, 13,103 TEG, 14 Dicing line, 15 Groove, 16 Fine crack, 20 Resist, 21,22 Pattern edge, 30 Stamper, 31,32,33, 34 convex part, 40 cutting mold, 50 holder, 60 mask pattern, 70 dummy shot, 101 module area, 102 scribe area, 104 alignment mark, 105 dummy pattern, 200 nanoimprint apparatus, 201 lens, 202 stamper, 203 substrate, 204 Elastic body, 205 substrate holding part, 206 pins, 207 base plate, 208 sapphire window, 209 optical fiber, 210 load cell, 212 stepping motor, 213 guide pole, 214 Teflon (registered trademark) ) Sheet, 220 light irradiator, 300 focal point, K aperture, S scribe area.

Claims (10)

Applying a resist on a semiconductor substrate on which a semiconductor integrated circuit is formed;
Pressing a stamper having a protrusion on the semiconductor substrate coated with the resist at a position corresponding to a scribe region including a dicing line of the semiconductor substrate;
Exposing and / or heating the resist when pressing the stamper;
Peeling the stamper and developing the resist;
Etching the semiconductor substrate using the resist patterned on the semiconductor substrate as a mask;
Removing the resist from the etched semiconductor substrate;
Fixing the semiconductor substrate from which the resist has been removed on a stage;
Setting the focus of the laser inside the semiconductor substrate fixed on the stage;
Moving the stage and irradiating the laser on a dicing line of the semiconductor substrate;
And a step of cleaving the semiconductor substrate irradiated with the laser. The resist is formed from a thermoplastic material;
The step of exposing and / or heating the resist includes a step of pressing the stamper in a state where the resist is heated and softened.
The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step of developing the resist includes a step of peeling the stamper in a state where the resist is cooled and cured. The resist is formed of a photocurable material;
The step of developing the resist includes
In a state where the stamper is pressed, the resist is exposed and cured;
2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a step of peeling the stamper from the cured resist and developing the resist. The resist is formed from a material having photocurability and thermoplasticity;
The step of exposing and / or heating the resist comprises:
A step of pressing the stamper while the resist is heated and softened;
The step of developing the resist includes
In a state where the stamper is pressed, the resist is exposed and cured;
2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a step of peeling the stamper from the cured resist and developing the resist.   5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the pattern density is made uniform by forming a dummy pattern in the scribe region on the semiconductor substrate in the previous period.   6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein an optimum pressure when the stamper is pressed onto the semiconductor substrate is controlled by calculating a pattern density.   The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein, when calculating the pattern density, a pattern area and a line integral of a pattern edge are included as factors. In the semiconductor substrate in which a dummy shot is arranged on the outer periphery of the semiconductor substrate, and the semiconductor integrated circuit is formed on the entire surface,
In the step of pressing the stamper, the stamper having a pressing surface smaller than the surface of the semiconductor substrate is shifted over the entire surface of the semiconductor substrate while sequentially shifting the pressing position so as to correspond to the position where the semiconductor integrated circuit is formed. Including the step of pressing,
A method for manufacturing a semiconductor integrated circuit device according to claim 1.   The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein isotropic etching is performed in the step of etching the semiconductor substrate. Etching the semiconductor substrate using a resist patterned on the semiconductor substrate as a mask so as to form an opening in a scribe region on the semiconductor substrate on which the semiconductor integrated circuit is formed;
Removing the resist from the etched semiconductor substrate;
Fixing the semiconductor substrate from which the resist has been removed on a stage;
Setting the focus of the laser inside the semiconductor substrate fixed on the stage;
Irradiating the laser on the dicing line of the semiconductor substrate from the surface side of the semiconductor substrate by moving the stage;
And a step of cleaving the semiconductor substrate irradiated with the laser.

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