TWI456728B - 具有防電磁干擾結構的半導體結構與其製造方法 - Google Patents

具有防電磁干擾結構的半導體結構與其製造方法 Download PDF

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TWI456728B
TWI456728B TW100123912A TW100123912A TWI456728B TW I456728 B TWI456728 B TW I456728B TW 100123912 A TW100123912 A TW 100123912A TW 100123912 A TW100123912 A TW 100123912A TW I456728 B TWI456728 B TW I456728B
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package
conductive
substrate
stand
conductive pin
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TW201232746A (en
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Kuo Hsien Liao
Alex Chi-Hong Chan
Fuh-Yuh Shih
Jian Cheng Chen
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Claims (12)

  1. 一種半導體結構，包括：一基板單元，具有一接地端、一上表面及一下表面；一半導體元件，設置於鄰近該基板單元之該上表面；一導電性接腳，設置於鄰近該基板單元之該上表面；一封裝體，包覆該半導體元件且具有一第一封裝上表面、一第二封裝上表面及一第一封裝側面，該第一封裝上表面實質上平行於該第二封裝上表面，且該第一封裝側面係連接該第一封裝上表面與該第二封裝上表面；以及一防電磁干擾膜，包括一上部、一側部及一支部，該上部係覆蓋該第一封裝上表面，該側部係覆蓋該第一封裝側面，而該支部係覆蓋該第二封裝上表面；其中，該導電性接腳連接該基板單元之該接地端與該防電磁干擾膜之該側部，且該導電性接腳具有相對之一第一側與一第二側，該封裝體覆蓋該導電性接腳之該第一側，該導電性接腳之該第二側、該基板單元與該封裝體共同定義一凹口空間。
  2. 如申請專利範圍第1項所述之半導體結構，其中該導電性接腳包括：一第一部分，該第一部分連接於該接地端；以及一第二部分，連接該第一部分與該防電磁干擾膜之該側部；其中，該第一部分與該第二部分之連接處定義一轉折部。
  3. 如申請專利範圍第1項所述之半導體結構，其中該 導電性接腳具有一端面，該導電性接腳之該端面與該封裝體之該第一封裝側面係實質上齊平。
  4. 如申請專利範圍第1項所述之半導體結構，其中該基板單元更具有一基板側面，該封裝體更具有一第二封裝側面，該防電磁干擾膜更具有一外側面，該基板側面、該第二封裝側面與該防電磁干擾膜的該外側面係實質上齊平。
  5. 如申請專利範圍第1項所述之半導體結構，其中該封裝體之該第一封裝上表面更具有至少一凹口。
  6. 一種半導體結構的製造方法，包括：提供一基板，該基板具有一接地端、一上表面及一下表面；設置一半導體元件於鄰近該基板之該上表面；設置一導電性腳架於鄰近該基板之該上表面，其中該導電性腳架設於該基板之該接地端上，其中該導電性腳架具有相對之一第一側與一第二側；形成一封裝材料，其中該封裝材料包覆該半導體元件，且該封裝材料覆蓋導電性腳架之該第一側，該導電性腳架之該第二側與該基板定義一凹口空間；形成至少一第一切割狹縫，其中該至少一第一切割狹縫至少經過該封裝材料及該導電性腳架，使該導電性腳架形成一導電性接腳以及使該封裝材料形成一封裝體，該封裝體具有一第一封裝上表面、一第二封裝上表面及一第一封裝側面，該第一封裝上表面實質上平行於該第二封裝上表面，且該第一封裝側面係連接該第一封裝上表面與該第 二封裝上表面，其中該導電性接腳之該第二側、該基板與該封裝體共同定義該凹口空間；形成一防電磁干擾材料，其中該防電磁干擾材料覆蓋該封裝體之該第一封裝上表面、該第二封裝上表面、第一封裝側面及該導電性接腳；以及形成至少一第二切割狹縫，其中該至少一第二切割狹縫至少經過該基板。
  7. 如申請專利範圍第6項所述之製造方法，其中於鄰近該基板之該上表面設置該導電性腳架之該步驟中，該導電性腳架包括：二第一部分，設於該接地端上；以及一連接部分，係連接該二第一部分；其中，各該第一部分與該連接部分之連接處定義一轉折部。
  8. 如申請專利範圍第7項所述之製造方法，其中於形成該至少一第一切割狹縫之該步驟中，該至少一第一切割狹縫經過該連接部分，使該連接部分形成二第二部分，其中相連接之該第一部分與該第二部分係形成該導電性接腳。
  9. 如申請專利範圍第6項所述之製造方法，其中該導電性腳架具有至少一貫穿部；於形成該封裝材料之該步驟中，該封裝材料經由該至少一貫穿部而覆蓋該導電性腳架之該第二側。
  10. 如申請專利範圍第6項所述之製造方法，其中於鄰近該基板之該上表面設置該導電性腳架之該步驟中更包 括：鄰近該基板之該上表面設置一導電性框體，其中該導電性框體包括一邊框及該導電性腳架，該邊框連接該導電性腳架；其中，透過鄰近該基板之該上表面設置該導電性框體，使該導電性框體之該導電性腳架設於該接地端。
  11. 如申請專利範圍第6項所述之製造方法，其中於形成該封裝材料之該步驟中更包括：設置一層壓材料覆蓋該半導體元件；以及硬化該層壓材料，以形成該封裝材料。
  12. 如申請專利範圍第6項所述之製造方法，其中於形成該至少一第一切割狹縫之該步驟中更包括：於該封裝體之該第一封裝上表面形成至少一凹口。
TW100123912A 2010-12-17 2011-07-06 具有防電磁干擾結構的半導體結構與其製造方法 TWI456728B (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI459521B (zh) * 2012-03-08 2014-11-01 矽品精密工業股份有限公司 半導體封裝件及其製法
TWI446514B (zh) * 2012-06-14 2014-07-21 矽品精密工業股份有限公司 半導體封裝件及其製法
US9601464B2 (en) 2014-07-10 2017-03-21 Apple Inc. Thermally enhanced package-on-package structure
US10109593B2 (en) 2015-07-23 2018-10-23 Apple Inc. Self shielded system in package (SiP) modules
US9721903B2 (en) 2015-12-21 2017-08-01 Apple Inc. Vertical interconnects for self shielded system in package (SiP) modules
TWI710099B (zh) * 2020-04-16 2020-11-11 矽品精密工業股份有限公司 封裝結構及其製法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7198987B1 (en) * 2004-03-04 2007-04-03 Skyworks Solutions, Inc. Overmolded semiconductor package with an integrated EMI and RFI shield
US20090152688A1 (en) * 2007-12-13 2009-06-18 Byung Tai Do Integrated circuit package system for shielding electromagnetic interference
US20090212401A1 (en) * 2008-02-26 2009-08-27 Byung Tai Do Package system for shielding semiconductor dies from electromagnetic interference
US7656047B2 (en) * 2005-01-05 2010-02-02 Advanced Semiconductor Engineering, Inc. Semiconductor device package and manufacturing method
TW201008478A (en) * 2008-08-08 2010-02-16 Advanced Semiconductor Eng Semiconductor device packages with electromagnetic interference shielding and forming method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100703090B1 (ko) * 2005-08-30 2007-04-06 삼성전기주식회사 후면 접지형 플립칩 반도체 패키지
WO2008062982A1 (en) * 2006-11-21 2008-05-29 Lg Innotek Co., Ltd Electromagnetic shielding device, radio frequency module having the same, and method of manufacturing the radio frequency module
US8043892B2 (en) * 2007-05-02 2011-10-25 Samsung Electronics Co., Ltd. Semiconductor die package and integrated circuit package and fabricating method thereof
JP2010010441A (ja) * 2008-06-27 2010-01-14 Murata Mfg Co Ltd 回路モジュールの製造方法および回路モジュール

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7198987B1 (en) * 2004-03-04 2007-04-03 Skyworks Solutions, Inc. Overmolded semiconductor package with an integrated EMI and RFI shield
US7656047B2 (en) * 2005-01-05 2010-02-02 Advanced Semiconductor Engineering, Inc. Semiconductor device package and manufacturing method
US20090152688A1 (en) * 2007-12-13 2009-06-18 Byung Tai Do Integrated circuit package system for shielding electromagnetic interference
US20090212401A1 (en) * 2008-02-26 2009-08-27 Byung Tai Do Package system for shielding semiconductor dies from electromagnetic interference
TW201008478A (en) * 2008-08-08 2010-02-16 Advanced Semiconductor Eng Semiconductor device packages with electromagnetic interference shielding and forming method thereof

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