TWI456573B - 資料傳輸及在記憶體裝置中之程式化 - Google Patents

資料傳輸及在記憶體裝置中之程式化 Download PDF

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Publication number
TWI456573B
TWI456573B TW098136331A TW98136331A TWI456573B TW I456573 B TWI456573 B TW I456573B TW 098136331 A TW098136331 A TW 098136331A TW 98136331 A TW98136331 A TW 98136331A TW I456573 B TWI456573 B TW I456573B
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Taiwan
Prior art keywords
memory
data
translation table
memory device
control circuit
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TW098136331A
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English (en)
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TW201023184A (en
Inventor
Vishal Sarin
Frankie F Roohparvar
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Micron Technology Inc
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Claims (15)

  1. 一種用於在一記憶體裝置中資料傳輸、程式化及讀取之方法，該方法包括：將原始資料傳輸至一記憶體陣列；將額外數位附加至該原始資料以形成一新的程式化字；將該新的程式化字程式化至該記憶體陣列，其中回應一第一轉譯表而將該額外數位附加至該原始資料，其中該第一轉譯表回應一特定錯誤邊限而提供不同的最低有效位元解譯窗口；及回應不同於該第一轉譯表之一第二轉譯表而自該記憶體陣列讀取該經程式化字，該第二轉譯表經組態以提供對於存在於一讀取臨限電壓中之一干擾條件之一錯誤補償邊限。
  2. 如請求項1之方法，其中該等額外數位包括複數個邏輯零位元。
  3. 如請求項1之方法，其中該等額外數位包括該原始資料之鏡像位元。
  4. 如請求項1之方法，其中該原始資料包括複數個邏輯位元。
  5. 如請求項1之方法，其中傳輸該原始資料包括傳輸一個邏輯位元且程式化該新的程式化字包括程式化三個或更多個邏輯位元。
  6. 如請求項1之方法，其中傳輸該原始資料包括傳輸兩個 邏輯位元且程式化該新的程式化字包括程式化複數個邏輯位元。
  7. 如請求項1之方法，其中形成該新的程式化字係由該記憶體裝置執行。
  8. 如請求項1之方法，且其進一步包括：該記憶體陣列自一控制電路接收該原始資料以用於程式化至一所選記憶體單元；回應來自該第一轉譯表之轉譯以形成包括作為最高有效位元之該原始資料及作為最低有效位元之額外資料之該新的程式化字；將該新的程式化字程式化至該所選記憶體單元；及驗證對該新的程式化字之成功程式化。
  9. 一種非揮發性記憶體裝置，其包括：記憶體控制電路，其用於控制該記憶體裝置之運作，該記憶體控制電路經組態以傳送原始資料；及一記憶體陣列，其耦合至該記憶體控制電路且回應於該記憶體控制電路而運作，該記憶體陣列係組態為以該原始資料程式化且附加額外資料，其中該所附加之額外資料增加該原始資料之一經程式化之臨限電壓邊限；其中該記憶體陣列經組態以回應一第一轉譯表而將該額外資料附加至該原始資料，其中該第一轉譯表回應一特定錯誤電壓邊限而提供不同的最低有效位元解譯窗口，及該記憶體陣列進一步經組態以回應不同於該第一轉譯表之一第二轉譯表而自該記憶體陣列讀取該經程式 化原始資料，該第二轉譯表經組態以提供對於存在於一讀取臨限電壓中之一干擾條件之一錯誤補償邊限。
  10. 如請求項9之記憶體裝置，其中該記憶體陣列包括一NAND架構。
  11. 如請求項9之記憶體裝置，其中該記憶體控制電路經組態以僅讀取以該所附加之額外資料程式化之該原始資料。
  12. 如請求項9之記憶體裝置，其中該記憶體控制電路經組態以讀取該經程式化之原始資料且忽略該所附加之額外資料。
  13. 如請求項9之記憶體裝置，其中該記憶體控制電路進一步經組態以自一所選記憶體單元讀取資料、存取一轉譯表以解譯該讀取資料，且回應於該轉譯表將該讀取資料轉譯回至該原始資料。
  14. 如請求項9之記憶體裝置，其中該記憶體陣列接收n個原始資料位元且附加m個位元之該額外資料，其中n不等於m。
  15. 如請求項14之記憶體裝置，其中該記憶體控制電路將n+m個位元傳送至該記憶體陣列。
TW098136331A 2008-10-30 2009-10-27 資料傳輸及在記憶體裝置中之程式化 TWI456573B (zh)

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US12/261,124 US8127091B2 (en) 2008-10-30 2008-10-30 Programming memory cells with additional data for increased threshold voltage resolution

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US (2) US8127091B2 (zh)
EP (1) EP2351044B1 (zh)
JP (1) JP5545552B2 (zh)
KR (1) KR101199131B1 (zh)
CN (1) CN102197437B (zh)
TW (1) TWI456573B (zh)
WO (1) WO2010059406A1 (zh)

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US8917553B2 (en) 2011-03-25 2014-12-23 Micron Technology, Inc. Non-volatile memory programming
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US9696918B2 (en) 2014-07-13 2017-07-04 Apple Inc. Protection and recovery from sudden power failure in non-volatile memory devices
US20230037044A1 (en) * 2021-07-30 2023-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-level cell data encoding
US11860733B2 (en) * 2021-12-08 2024-01-02 Western Digital Technologies, Inc. Memory matched low density parity check coding schemes

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CN102197437A (zh) 2011-09-21
WO2010059406A1 (en) 2010-05-27
JP2012507803A (ja) 2012-03-29
US20120144101A1 (en) 2012-06-07
EP2351044A4 (en) 2012-09-19
EP2351044B1 (en) 2015-10-21
CN102197437B (zh) 2015-12-09
TW201023184A (en) 2010-06-16
JP5545552B2 (ja) 2014-07-09
US20100115176A1 (en) 2010-05-06
KR101199131B1 (ko) 2012-11-09
KR20110089312A (ko) 2011-08-05
US8127091B2 (en) 2012-02-28
EP2351044A1 (en) 2011-08-03

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