TWI455219B - 準晶片尺寸封裝積體製程 - Google Patents

準晶片尺寸封裝積體製程 Download PDF

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Publication number
TWI455219B
TWI455219B TW097125660A TW97125660A TWI455219B TW I455219 B TWI455219 B TW I455219B TW 097125660 A TW097125660 A TW 097125660A TW 97125660 A TW97125660 A TW 97125660A TW I455219 B TWI455219 B TW I455219B
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Taiwan
Prior art keywords
layer
die
metal layer
metal
depositing
Prior art date
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TW097125660A
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English (en)
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TW200913099A (en
Inventor
David J Fryklund
Alfred H Carl
Brian P Murphy
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Skyworks Solutions Inc
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Publication of TW200913099A publication Critical patent/TW200913099A/zh
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Publication of TWI455219B publication Critical patent/TWI455219B/zh

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Description

準晶片尺寸封裝積體製程
本發明係關於半導體元件封裝及其製造方法。更特別地，至少一個實施例係關於覆晶半導體元件封裝以及封裝方法。
相關申請案
本發明係主張在35 U.S.C §119 (e)下之美國臨時申請案第60/954,483號(於2007年8月7日所提申)的標題為「準晶片尺寸封裝積體製程」”之優先權，其之整體內容係以引用方式納入本文中。
目前，許多半導體封裝技術被廣為接受於射頻(RF)構件的工業上。然而，此種封裝技術係相對複雜的，並且使得符合成本與操作上的要求變為困難，特別當操作頻率往更高區間移動與尺寸變為更重要時。
一種廣泛被使用的封裝技術係「晶片與銲線」封裝的晶粒，其包括將被包覆之晶粒耦合至封裝載體上。為基板或金屬引線框架(lead frame)之封裝載體係提供從晶粒至封裝外部之連線。在標準的晶片與銲線的封裝中，該介於晶粒與載體之互連係使用接合銲線所製作。該晶粒係附接於載體而面向上，及銲線係先接合於晶粒上，隨後係環繞並接合於該載體。晶片與銲線封裝之晶粒係承受著相對大的尺寸與寄生電感的問題，以及具有以一些基板材料於製造上的問題。
一個由晶片與銲線所封裝的晶粒之實例100係說明於圖1中。該晶粒102係藉由接合銲線108而附接於封裝載體104而面向上，其包括金屬引線框架106。接合銲線典型係約1-5毫米(mm)之長度。如圖1中所能見，該引線框架106於水平方向上實質延伸超過該晶粒102之邊緣。此提供相對大尺寸之藉由晶片與銲線所封裝的晶粒。即使晶粒本身係小的，當其亦必須容納引線框架時，於基板上的「禁入(keep out)」”區域(即其中無其他構件可被放置的區域)或被晶粒附接於其上之PCB係更大的。再者，該使用於連接晶粒於引線框架的接合銲線108係由於線的直徑與長度而造成一系列的寄生電感，其可能對於該構件之整體電氣及/或射頻性能係不利的。由晶片與銲線所封裝的晶粒另外的缺點是在晶粒102上的主動元件係藉由晶粒基板之全部厚度而自載體104所分離(其可包括接地及/或冷卻鍍板)。如圖1所示，元件110(如場效電晶體)係位於晶粒的上表面且遠離載體104，其使得元件110之熱管理變為更困難。一種常用的解決方案係藉由通路(via)112來連接元件110至載體104。此解決方案於矽基板上係可接受的，雖然其必增加製造的複雜度。然而，砷化鎵(GaAs)基板當通路(特別是許多的通路)被鑽孔穿過基板時係非常脆且容易破裂。
一種用於標準晶片與銲線封裝之替代的封裝技術係覆晶封裝。覆晶係描述將晶粒以電氣連接於封裝載體之方法。相對於標準使用接合銲線以將晶粒連接於載體的晶片 與銲線封裝，在覆晶封裝中晶粒與載體之間的互連係穿過直接置於晶粒表面之有導電性的「凸塊」所作成。該凸塊的晶粒接著係被「顛倒(flipped over)」及被面向下地放置於凸塊上以將晶粒直接連接至載體。覆晶封裝經常被使用於球格陣列(BGA)型封裝中。於BGA型封裝中，相對於其晶粒附接於上的面，載體的面具有其貼附的銲接球型之陣列(通常在格結構中)。此銲接球型(或凸塊)陣列係取代標準封裝的金屬引線框架。
覆晶BGA封裝的實例係說明於圖2中。晶粒102係耦合至可典型地為堅硬的壓層板或類似結構之載體104。介於晶粒102與載體104之間的覆晶連接通常係由兩種方法中之一者所形成：使用導電黏著劑或，或更常見地銲接劑(solder)。在銲接連接的例子中，具銲錫凸塊114 (solder bump)之凸塊的晶粒係藉由銲接劑回流製程而附接於載體104，其係非常相似於使用將球格陣列球型116連接至封裝外部之製程。通路120可被使用於銲錫凸塊114(及晶粒連線)與BGA的球型116之互連，以便提供來自封裝外部與晶粒的連線。在晶粒係被電銲接合後，通常為環氧類樹脂之未充滿材料118係被添加於晶粒102與載體104之間。該環氧類樹脂未充滿材料118係被使用於控制由晶粒102(通常為矽或GaAs)與載體104之間的熱膨脹差異所引起在銲點(solder joints)中的應力。
在覆晶的設計中，元件110係非常接近於載體104，該載體如前所討論可包括接地/冷卻鍍板，使得熱管理變得 容易。此外，晶片係直接耦合至載體104以消除結合晶片與銲線封裝的接合銲線之寄生電感。覆晶BGAs已認為在矽領域上係為可被接受的，但於GaAs類似領域中係較不利的，大部份係由於BGA圖案增加的尺寸(特別由凸塊與凸塊之間隔所引起的)以及易脆的GaAs材料。
至少一些觀點以及實施例係關於晶片尺寸封裝製程，其提供與封裝相互作用的構件之電路設計以達到優異的射頻性能與小的尺寸。再者，此優異的射頻性能與小的尺寸可在封裝製程中以最小複雜度而達成。在至少一個實施例中，封裝製程可使用批次技術，包括金屬沉積及僅單一種類的聚合物之沉積與選擇性移除，使得製程適合於高生產量、低成本晶片/模組之製造。
根據一個實施例，封裝半導體晶粒之方法可包括以一覆晶結構配置來將晶粒黏著於基板，以第一聚合物層塗佈於晶粒上，選擇性地移除第一聚合物層以提供至少一開口以將一部份之晶粒曝光，以及將第一金屬層沉積於第一聚合物層上，第一金屬層至少部份由至少一開口所填滿以提供與晶粒之電氣接觸，以及包括實質上環繞於第一金屬層上部表面之平面上的晶粒以提供一環繞於晶粒之電磁遮蔽。在一個實例中，以第一聚合物層塗佈的晶粒可包括將晶粒以SU8塗佈。在另一實例中，該方法可進一步包括將銲錫凸塊附接於電氣接觸上。此外，在至少一個實例中，該方法亦可包括沉積第二聚合物層於第一金屬層上之行 為，及選擇性移除第二聚合物層以提供至少一開口於電氣接觸上方及提供電氣接觸的入口。
一半導體元件的實施例係可包括基板，在覆晶結構配置中係附接於一個或更多晶粒，該晶粒具有上表面及下表面，該下表面係配置相對於上表面並黏著於基板上，第一SU8層配置於在晶粒之上表面上方，第一SU8層包括至少一提供對於晶粒入口之開口，第一金屬層配置於第一SU8層上方，第一金屬層包括至少一與晶粒之電氣接觸，以及至少部份環繞於第一晶粒之電磁遮蔽。在一實例中，該電磁遮蔽可為第一金屬層的部份。在另外實例中，半導體元件係可進一步包括配置於電磁遮蔽的第二SU8層。在另一實例中，半導體元件係可進一步包括配置於第一金屬層上的第二SU8層，第二SU8層包括一開口以提供至少一電氣接觸之切割道。半導體元件可進一步包括配置於第二SU8層上方的第二金屬層，第二金屬層包括至少一個凸塊接觸電氣，其耦合至晶粒上的電氣接觸。在此實例中，第二金屬層可包括電磁遮蔽。銲錫凸塊可被附接於至少一個凸塊接觸，該銲錫凸塊形成球格陣列的部份。
根據另一個實施例，一種半導體元件的製造方法可包括將複數個晶粒以一與另一晶粒相隔的預定距離黏著至半導體晶圓上，將第一SU8層配置於該複數個晶粒之上，選擇性地移除第一SU8層以提供至少一個存取點至複數個晶粒的每一者上及提供切割道以將另一晶粒分隔之複數個晶粒的每一晶粒，將金屬接觸沉積於第一SU8層上，該金屬 接觸包括至少一用於複數個晶粒中各晶粒的電氣接觸，該至少一電氣接觸係至少一個電氣接觸係由經對於各別晶粒之相對應的存取點所構成，及將金屬層沉積於第一SU8層上，該金屬層形成一至少部份環繞於該複數個晶粒中各晶粒的電磁遮蔽。在一個實例中，該方法係可進一步包括將第二SU8層沉積於金屬層上方。銲錫凸塊可被附接於金屬接觸，及晶圓可被沿著切割道被單粒化而提供獨立的半導體元件。
另一個實施例係關係於一種半導體模組之製造方法，各模組包括至少兩個晶粒。該方法可包括將複數個晶粒附接於電鍍基板上，該複數個晶粒係被安排於群組中以提供半導體模組，各群組包括至少兩個晶粒，將第一SU8層配置於該複數個晶粒上；形成複數個於第一SU8層上之開口以提供第一各別存取點至該複數個晶粒之每一者，及沉積第一金屬層於第一SU8層上及該複數個開口之中，第一金屬層提供介於至少兩個經第一各別存取點之間的各模組之晶粒之電氣連接。該方法可進一步包括將第二SU8層沉積於第一金屬層上方，選擇性地移除第一SU8層以提供至少一第二存取點於各模組，以及提供切割道將各別模組與其他者分隔，將金屬接觸沉積於第一SU8層上，該金屬接觸係包括至少一用於各模組之電氣接觸，至少一電氣接觸係由經對於各別模組之相對應的第二存取點所構成，以及將第二金屬層沉積於第二SU8層上，該第二金屬層形成至少部份環繞各模組之電磁遮蔽。該晶圓係可被沿著切割道被 單粒化而提供獨立的半導體模組。
至於本發明之其他觀點、實施例及優點係被詳細討論如下。此外，可被了解的是前述資訊與下列詳細之描述係僅為說明性的各種觀點及實施例之例子，及意圖以提供用於了解所主張之觀點及實施例的瀏覽或架構。所附的圖式係被包括以提供說明及進一步各種觀點及實施例之了解，以及係被併入與組成本說明書之部份。該圖式與本說明書之其他部份係供解釋所描述和主張之觀點及實施例的原則和操作。
至少一些觀點及實施例係關於半導體封裝技術及製程，及根據其所製造的元件。如上所討論，傳統的晶片與銲線封裝的元件有許多的缺點，包括相對大的尺寸及寄生電感。根據至少本發明的一些觀點，準晶片尺寸封裝製程可被使用於矽或砷化鎵(GaAs)的基板上，以提供覆晶球格陣列(BGA)元件，其係小、堅固的、具優異的射頻性能或前述所有者。如此所使用者，術語「準晶片尺寸」係指元件封裝和封裝製程，其封裝尺度係與元件或附接於其上之元件約相同之尺寸的尺寸。此外，提供電磁遮蔽的能力係可被建立於製程的實施例中，藉此提供良好的遮蔽元件以被製造無額外的、複雜製程步驟，如下進一步所討論。
根據一些實施例，晶片設計及封裝設計可依續連貫，提供晶片設計以整併入封裝設計中。與其中晶片必須符合於一些可用的封裝之一者的傳統晶片與銲線封裝不同，本 發明之實施例提供封裝以符合晶片設計，及可因此使有更彈性設計製程及更小、更有空間效率的晶片成為可能。例如，以傳統的晶片與銲線封裝，接合銲墊必須被沿著晶粒周邊排列以便提供接合銲線以將晶粒連接至封裝的引線框架。相反的，使用覆晶BGA及根據本發明之觀點的封裝製程，晶粒與封裝可被一起設計以提供彈性的晶粒佈局而不需要周邊接合銲墊。當電力可被直接帶入晶粒之核心而不是必須導引至邊緣時，此可提供如減少的電力/接地電感及減少的雜訊的優點。此外，當晶粒全部表面可被使用於互連，而非如以傳統的晶片與銲線封裝時僅為邊緣之用時，覆晶排列可提供更高的訊號密度。因此，相較於經接合銲線連接的晶粒，覆晶設計係能支持在相同晶粒尺寸上頗大數量的互連。再者，相較於傳統的晶片與銲線封裝的晶粒，黏著晶粒覆晶係提供入口至晶粒表面及提供更佳的熱管理。至少一些實施例可提供具有非常小的電感之小型封裝(藉由實際上缺少BGA之接合銲線與短電感路徑)及在廣泛頻率範圍中好的性能，如下文中進一步討論。
其可被了解的是：於此討論之方法與裝置之實施例係不限制應用於下列描述所提出之構件的結構與排列之細節或說明於所附之圖式。該方法與裝置能夠實施於其它實施例及係以各種方式被實行或被完成。特定實施方式的實例係於此提供以僅用於說明之目的並不意圖做限制。特別地，與任一個或更多實施例有關之所討論的方式、要素和特徵係不意圖被排除在任何其他實施例中的相似作用。同 樣地，使用於此的詞組和術語係用描述的目的及不應該被認定作為限制。該於此「包含」、「包括」、「具有」、「含有」、「涉及」之用法及其變化型係意味包括該列於其後之項目和對等例，以及其他的項目。
根據封裝製程之至少一個實施例，該晶粒可為覆晶及被囊封於聚合物中。該聚合物可支持金屬電鍍圖案，其係可互連額外的晶粒以及介接BGA圖案。因此，該製程可提供用於對面積敏感之晶粒以被互連至其他晶粒，並且扮演一插入物於工業界標準的BGA圖案中。此外，金屬遮蔽可被整併於封裝內部，因而管理射頻干涉波及諧和波，其如下進一步討論。因為該晶粒係被顛倒的，該互連路徑可被良好地管理以減少或最小化電感以及提供非常短之路徑至散熱片，若為所欲或必要的。進一步地，因為該製程使用批次技術(亦即：疊層沉積和選擇性移除)，數以千計的模組係可被同時製造於晶圓上。
準晶片尺寸之封裝技術之實例的流程圖係說明於圖3中。該製程之觀點係連續參考圖3而被討論在下文中。
參考圖3和4，在第一步驟200中，基板300係可被一種或更多金屬層來電鍍，其全體顯示於如圖4中之302層。於一實例中，金屬層302可包括一非常薄的鈦層，其具有例如約1000埃(Å)之厚度。該鈦層可被薄的金層所覆蓋，其具有如約2000 Å之厚度。在另一實例中，標準的電鍍基板係可被購買，並且該製程係因此可忽略步驟200而以一已電鍍之基板於步驟202開始。該基板通常係可為 矽基板，但亦可為砷化鎵或其他材料。
參考圖3及5，於步驟202中，晶粒304係可被附接於電鍍基板300上。該晶粒係附接於覆晶上。圖5係說明兩個被以一預定距離而分離放置於基板300上的晶粒304a，304b。可了解的是該基板可為半導體晶圓的部份，其係具有數以百計或甚至數以千計以預定間隔被貼附之晶粒，而且其最後將被單粒化以使得個封裝之晶粒形成單一晶片。因此，圖5說明了部份的此種晶圓。該晶粒304係可使用如環氧類樹脂、銲接製程、或其他黏著劑而被貼附。可藉調正標示或基線的使用以使在基板上晶粒之佈置和位置容易被蝕刻於電鍍基板上。圖6係說明示意地標示以顯示一預備用於晶片及調正標示307的基板區域之輪廓306。圖7係示意性說明輪廓306具有晶粒304放置於其中的俯視圖。
於下一個步驟204中，一聚合物層可被放置於電鍍基板上，於晶粒304上方，以及開口可在聚合物層中藉選擇性移除(例如，藉由蝕刻或其他製程)部份的聚合物層而被形成。參考圖8，其說明圖5之晶圓部份的剖面圖，其說明於步驟204中所形成的聚合物層308。該層308具有開口310形成於其中，其將被使用以形成晶粒304的電氣接觸，如下進一步討論。另一開口312係亦被提供於層308中，此開口係被稱為「切割道」，其形成分割道以分隔兩晶粒，沿著該分割道而將晶圓單粒化為獨立晶片，如下進一步討論。圖9係說明圖6及7之晶片輪廓的俯視圖，其 係顯示聚合物層308及形成於其中之開口310與切割道312。
根據一個實施例，該層308係可包括聚合物SU8。SU8係一種可光成像的環氧類樹脂。然而，可被了解的是本發明非限於使用SU8以及其他相似或等同聚合物或環氧樹脂可被用來代替。在一實例中，該層308係可具有約25微米之厚度t1。然而，可被了解的是：此厚度係僅為一實例並且該層308係可具有不同的厚度，取決於如所使用的應用、製程及/或材料。可進一步被了解的是：雖然聚合物層之沉積和選擇性移除被說明於圖3如同步驟(步驟204)中，然而在實務上步驟204係係可被分成二個或更多製程步驟。例如，其中步驟204可包括沉積該層的第一製程步驟(204a)，以及其中該層被選擇性移除以提供開口的第二製程步驟(204b)。
仍參考圖3，在步驟206中，金屬層係可被施用於晶圓，於聚合物層上，以形成用於晶片之電氣接觸。參考圖10，說明接著步驟206的圖8之晶圓部份的剖面圖。圖10顯示在聚合物層308中的開口310中所形成之金屬接觸318。在一個實施例中，額外的金屬化係可被沉積於步驟206中以提供用於晶片的電磁遮蔽，如下進一步討論。根據另一實施例，SU8的重複層及金屬互連係可在凸塊被添加以完成BGA之前被施用(如箭號208所示)，其取決於電路與晶粒複雜度。
根據一個實施例，另一層聚合物層係(例如：SU8) 可被沉積於第一金屬層之上，其係提供接觸318。此動作係可被說明於顯示圖10之晶圓部份的圖11中，其係進一步包括第二聚合物層320。第二聚合物層320可被選擇性移除以形成開口322，其可被使用以形成電氣連接至下方的金屬接觸318。在至少一實例中，聚合物層中一層或更多係可包括結合一個或更多添加物之SU8。特別地，在至少一實例中，一上方或最終之聚合物層係可包括具有一光學上不透光之添加物結合於其內的SU8，例如在圖11所說明的實例中之第二聚合物層320。此添加物係可包括，如氧化鐵、氧化鎳、氧化鋁、氧化鈦、滴定鈣、氧化鋅、氧化鋯以及氧化錫。
參考圖12，第二金屬層324係可被沉積於第二聚合物層320之上方。此第二金屬層324可將接觸318延伸至第二聚合物層320表面上方，以及係亦可被使用以提供用於晶片周圍之電磁遮蔽的內建法拉第機架314。在一實例中，該遮蔽金屬係可延伸自在晶片中之接地接觸、延伸在晶片周圍，因而提供法拉第機架314。可被了解的是遮蔽係不完全的，因為至少對於大部份的構件而言在遮蔽中之斷裂可被提供用於射頻輸入/輸出(in/out)及DC偏壓輸入/輸出訊號路徑。再者，可被了解的是在一些實例中：多重遮蔽係可被提供以便在模組內遮蔽獨立構件以及遮蔽全部的模組/晶片。該遮蔽金屬層係可例如包括非常薄的金層。因此，在至少一實例中，額外的聚合物層(未顯示)可被提供於在遮蔽金屬層上以保護遮蔽。如上所討論，此額外的 聚合物層可包括光學上不透光之添加物結合於其內的SU8，特別是若此層形成此封裝之最上面或最終的聚合物層。
參考圖13，此說明在圖6和7的晶片輪廓內第二金屬層324之佈局實例的俯視圖。在此實例中，晶粒係一單極雙投開關，及金屬層324係因而被安排以提供適用於開關的接觸。可被了解的是金屬層324的佈局(以及在步驟206中被沉積的第一金屬層之佈局)係可取決於被實施於晶粒中電路而變化。在所說明的實例中，金屬層包括形成法拉第機架314的部份以及形成經延伸接觸324的部份。接觸324結束於將附接BGA之凸塊的放大部份326上。
再次參考圖3，一旦全部金屬和聚合物層的沉積及選擇性移除已被完成，BGA的凸塊將被貼附在步驟208中。圖14說明圖12之結構，其亦包括部份BGA的凸塊316。最後，在步驟210中，該晶圓可沿切割道312被單粒化以提供獨立的封裝晶片。取決於晶粒的電路系統，此晶片可為不連續的元件(例如：單極雙投或多投開關、放大器、濾波器或其他元件)或可為包括一個或更多元件的模組，其係可與其他模組互連以形成組合元件。如上文所討論，該藉由製程之實施例所製造的封裝可容易地互連於其他晶粒上，以及可因此具有理想模組型式。
上述所討論準晶片尺寸封裝製程之實施例係使用GaAs而被用來製造單極雙投開關。該開關實例之俯視圖係被說明於圖15中。如上所討論，開關400係包括由以耦合於 金屬遮蔽404之球型402的BGA所表示之接地接觸。開關係黏著於鍍金之矽基板上，其係連接於地並且因而至該遮蔽以創造接地側板或法拉第機架。開關包括兩個射頻輸出接觸406及408，以及射頻輸入共用埠410，其各者係分別耦合至球型412、414及416的BGA上。開關亦包括兩個分別耦合至球型422及424的DC偏壓終端418、420。當然，可被了解的是該I/O係可逆的，以使得埠410可被使用以作為共用輸出埠，並且接觸406與408可被使用以作為不同的輸入埠。圖16說明部份的實例晶圓，其包括多數此種由切割道312所分隔的開關400。
圖15的開關之實例係須經許多測試，以及至少一實例開關之性能係可被量測。在一個實例中，開關係須經機械/晶粒剪切試驗，其測試晶粒對於基板之黏著強度。該開關係能夠抵抗至少250克的剪切作用力。在其他實例中，開關係須經凸塊剪切試驗，其測試凸塊對於基板之黏著強度。再次，開關係能夠抵抗至少250克的剪切力。在此等實例中，開關係可使用較傳統含鉛銲錫更脆的無鉛銲錫而被製造，並且通常係促成傳統封裝元件之降低堅固。在其他實例中，於131度的攝氏溫度、85%溼度及以施加-5伏特至偏壓埠而持續96小時下，開關經歷和通過初步的HAST(高加速的剪切試驗)。
雖然先前已嘗試以製造類似的覆晶BGA封裝，此等嘗試係被相信以具有多重型式之聚合物和許多額外的製程步驟(諸如研磨)，其係妨礙進入諸如商用無線市場之市場 所需的低成本、大量生產。相反地，根據本發明之至少一個實施例的製程僅使用一種型式之聚合物(例如：SU8)，以及不需要封裝互連表面之額外研磨。此外，在晶片之接觸可使用較典型用於銲線接合所需之金便宜的銅以被製作。因此，如上所討論，因為該製程係使用批次技術(亦即：疊層沉積與選擇性移除)，數以千計之模組可被同時製造於晶圓上，其提供大量製造。此等因素與簡單製程步驟及封裝的晶片之小尺寸係一起促成跟據本發明觀點所製造的低成本晶片。此外，元件的小尺寸和高性能(如下文所說明)符合無線市場之需求，且亦使此元件相當合適於許多其他市場和應用。
參考圖17，此係說明根據本發明觀點的開關400之實例的俯視圖。為了尺寸之比較，圖17係亦說明在傳統晶片與銲線中類似於單極雙投開關426之俯視圖。圖17係依比例繪製以顯示在兩封裝之間的尺寸差異。如由圖17所見，該開關400係具有較傳統封裝開關426為小的封裝尺寸。此外，當包括開關426之引線框架時，傳統封裝開關426之佔位空間448(以及因而「禁入區域」)係較該開關400者大許多。
參考圖18，此係說明圖17之兩開關400，426之側視圖。為適當比較兩開關之尺寸，圖18係依比例繪製。可看到的是該開關400亦具有較傳統封裝的開關426(即，高度h2>h1)小許多之輪廓(較低之高度，h1)。該開關400之所減少的高度係節省垂直空間以提供更緊密的電路板板(開關與其他相似地封裝元件可被附接於其上)，及提供開關抵抗較大之晶粒剪切力。再者，由於減少開關的佔位空間和高度，該開關係可佔有約標準封裝GaAs單極雙投開關七分之一的體積。
在一個實例中，根據本發明之實施例的開關之隔離性能(isolation performance)係被測試。在此實例中，該S21隔離係以自DC(約0Hz)延伸至60.0億赫茲(6GHz)之頻率範圍作測試。該S31隔離亦係以相同頻率範圍被量測。對於此等測試，開關係被連接於在測試板下之元件，以及測試係在周遭空氣氣溫下所實行。5.0V之控制電壓係被使用的。所量測的隔離之標繪圖係以分貝(dB)為單位而說明於圖19中。記錄曲線430係表示S21隔離和記錄曲線432係表示S31隔離。如由圖19可見，依照本發明所製造開關係達到在6GHz下約18dB之隔離，以及較由0到5.0GHz下的20dB大(明顯地較在低於4.5GHz下之20dB為大)。
為比較之目的，S21隔離係被量測以用於在相同頻率範圍(0-6GHz)與相同測試狀況下之兩傳統的開關(亦即：相同的溫度、控制電壓等)。用於兩傳統元件之各者的所量測之隔離對頻率的繪製圖係說明於圖20中。第一元件係標準封裝的(例如：晶片與銲線所封裝的)單極雙投開關，其係市售於貨號AS 179而得自MA, Woburn的Skyworks Solutions Inc.。所量測用於此元件之隔離係以記錄曲線434說明於圖20中。如自圖20所見，第一元件達到在6GHz下約-8.757dB之隔離。該第二元件係傳統覆晶封裝之單極 雙投開關。所量測用於此元件之隔離係以記錄曲線436而說明於圖20中，並且可了解的是：該元件係達到在6GHz下約-10.84dB之隔離。藉比較圖19與20，可了解的是：根據本發明觀點的開關達到至少與兩傳統元件在頻率範圍間有一良好的隔離，以及係在高頻上(在4.5GHz以上)實質上更佳地實行。
在另一個實例中，根據至少一本發明之實施例的插入損耗(insertion loss)係在頻率範圍0-6GHz下被測試。S21之插入損耗(亦即：當開關係被組態以使得一射頻輸出埠(標示為埠2)係被連接於共用之射頻輸入埠(標示為埠1)時的插入損耗)，以及S31之插入損耗(亦即：具有其他連接於共用射頻輸入埠之射頻輸出埠(標示為埠3))係被量測。為此等測試之目的，開關係再次被連接於待試元件板，控制電壓係5.0V，並且此測試係在周遭空氣溫度狀況下被實行。參考圖21，此係說明S21插入損耗對頻率(記錄曲線438)及S31插入損耗對頻率(記錄曲線440)之標繪圖。如自圖21所見，開關可達到在6GHz下約-1.16dB之插入損耗及在全部頻率範圍下具有好的性能。
為了比較之目的，用於如上文所討論兩個傳統元件之插入損耗性能係以在相同測試狀況下而於相同的頻率範圍內被量測。此結果係被說明於圖22中。記錄曲線442係表示用於第一傳統封裝元件之所量測的S21插入損耗對頻率，以及記錄曲線444係表示用於第二傳統覆晶封裝元件之所量測的S21插入損耗對頻率。藉比較圖21及22可見， 根據本發明觀點的開關在較高末段之頻率範圍可達到較兩傳統元件中一者為更好的插入損耗。如上所討論，根據本發明觀點的開關達到在6GHz下約-1.16dB之S21插入損耗，然而在6GHz下第二傳統元件達到-1.572dB及第一傳統元件僅達到-2.703dB。
根據另一個實施例，半導體晶圓可被形成於複數個晶片之內，其係包括模組而不是獨立晶粒。參考圖23，此係說明此種晶圓之實例的一部份。如上文所討論，該複數個晶粒係可以預定間隔而被附接於電鍍基板300。然而，於此實施例中，藉由切割道(沿其晶圓係被單粒化)與其他模組分隔之各模組328可包括二個或更多獨立晶粒。在圖23所說明之實例中，各模組328係包括第一晶粒330與第二晶粒332。該些晶粒330，332係可為一併操作以提供所欲之功能之不同構件。例如，一個晶粒係可為放大器及其他的濾波器，使得該模組在所欲之頻帶中提供一放大訊號。
如上所討論，聚合物層(例如：SU8)及金屬層可被沉積於晶粒330，332之上方以提供電氣接觸324至晶粒330，332上，以及至可附接BGA之凸塊316。在一個實施例中，額外的SU8及金屬層係為必要的(相較於其中在各晶粒僅包括單一晶粒之實施例)，以提供在模組328內之兩晶粒330，332之間的互連334。在一實例中，一與接線之接觸亦可被提供以使得BGA之凸塊316可被附接於其上，如在圖23中所說明。如上所討論，至少一 金屬層可實質地環繞於模組328且於基板300上被耦合於金屬層302，以便提供保護模組免於電磁干擾的法拉第機架314。因此，一電磁遮蔽(法拉第機架)係可被內建於封裝一模組328之製程中，該模組328係以上文所討論用於包括一個晶粒之晶片相同的方法來包含二個或更多晶粒。
總結，至少本發明一些觀點及實施例係關於半導體元件以及其之封裝製程，其係微小、堅固且在一廣泛頻帶中達到良好的射頻性能。在至少一個實施例中，封裝半導體晶片係可為覆晶BGA元件，其係包括一個或更多以至少一層SU8(或其他聚合物)所塗佈之晶粒，並且具有被佈置於SU8層上之金屬層來提供接觸和互連。該金屬層係亦可被組態為形成法拉第機架(至少部份地環繞於該等晶粒)，以提供內建用於獨立晶粒或用於包括二個或更多晶粒之模組的電磁遮蔽。用於製造此種半導體晶片之製程亦以被描述。
具有因而所描述之許多觀點的至少一實施例，可被了解的是：各種改變，修改，以及改善係意指為此揭示內容以及意為在本發明範疇中。因此，前述敘述與圖式係僅為實例之作用，並且本發明範疇應被決定自所附加專利申請範圍之適當架構以及其等同物。
100‧‧‧晶片與銲線所封裝的晶粒
102‧‧‧晶粒
104‧‧‧封裝載體
106‧‧‧金屬引線框架
108‧‧‧接合銲線
110‧‧‧元件
112‧‧‧通路
114‧‧‧銲錫凸塊
116‧‧‧BGA球型
118‧‧‧環氧類樹脂之未充滿材料
120‧‧‧通路
300‧‧‧(電鍍)基板
302‧‧‧金屬層
304a,304b‧‧‧晶粒
306‧‧‧輪廓
307‧‧‧調正標示
308‧‧‧聚合物層
310‧‧‧開口
312‧‧‧切割道
314‧‧‧法拉第機架
316‧‧‧凸塊
318‧‧‧金屬接觸
320‧‧‧第二聚合物層
322‧‧‧開口
324‧‧‧第二金屬層，經延伸接觸，電氣接觸
326‧‧‧經放大部份
328‧‧‧模組
330‧‧‧第一晶粒
332‧‧‧第二晶粒
334‧‧‧互連
400‧‧‧開關
402‧‧‧球型BGA
404‧‧‧金屬遮蔽
406,408‧‧‧接觸
410‧‧‧射頻輸入共用埠
412,414,416,422‧‧‧球型BGA
418,420‧‧‧DC偏壓終端
426‧‧‧球型BGA，單極雙投開關，傳統封裝開關
430~444‧‧‧記錄曲線
448‧‧‧佔位空間
至少一個實施例之各種觀點係參考後附圖式被討論在上文中。於不意圖依比例繪製之圖式中，每個相同或近似 相同之被說明於各種圖式中的構件係以相似數值表示。為清楚之目的，並非每個構件係可被標示於每一個圖式中。
該等圖式係被提供用於說明與解釋之目的，並且係不意圖做為本發明限制之定義。在該等圖式中：圖1係一傳統晶片與銲線封裝晶粒之一個實例的一圖；圖2係一傳統球格陣列覆晶半導體封裝之一個實例的一圖；圖3係一說明根據本發明觀點的一製程之一個實例的流程圖；圖4係一電鍍基板之一剖面圖；圖5係圖4之電鍍基板的一剖面圖，其係根據本發明觀點具有兩個附接於其上之晶粒；圖6係一遮罩之一上俯視圖的一示意說明，其係顯示具有對準標記之一晶片的輪廓；圖7係圖6之略圖的一上俯視圖，其係顯示被放置於該輪廓內的晶粒；圖8係圖5之結搆的一剖面圖，其係亦根據本發明觀點顯示一聚合物層；圖9係顯示圖8之聚合物層的一遮罩之一上俯視圖；圖10係圖8之結搆的一剖面圖，其係另外顯示金屬接觸；圖11係圖10之結構的一剖面圖，其係亦顯示一第二聚合物層； 圖12係圖11之結構的一剖面圖，其係亦顯示一額外被配置於該第二聚合物層上之金屬層；圖13係圖6之輪廓的一上俯視圖，其係亦顯示一金屬層之一示範性佈局；圖14係圖12之結構的一剖面圖，其係另外地顯示附接於該等金屬接觸的凸塊；圖15係根據由本發明製程之一實施例所製作的一單極雙投開關實例之一俯視圖。圖16係一部份晶圓的一俯視圖，其係說明數個由切割道所分離之圖15的單極雙投開關之實例；圖17係一傳統晶片與銲線封裝半導體元件與根據本發明觀點之半導體封裝的一俯視圖，其係說明兩元件之間在佔位空間尺寸上的差異；圖18係圖17之兩個元件的一側視圖，其係說明兩元件之間在高度上的差異；圖19係一對於根據本發明觀點的一單極雙投開關之一個實施例的隔離對頻率之標繪圖；圖20係一對於兩個實例傳統的單極雙投開關之隔離對頻率的標繪圖；圖21係一對於該單極雙投開關的兩個實施例之插入損耗對頻率的標繪圖；圖22係一對於相同兩個實例傳統的單級雙投開關之插入損耗對頻率的標繪圖；以及圖23係包括遮蔽模組的一半導體晶圓之一個部份實例 的一剖面圖。

Claims (52)

  1. 一種封裝一半導體晶粒之方法，該方法係包括：將該晶粒以一覆晶結構配置而黏著至一基板；將該晶粒以第一聚合物層塗佈，該第一聚合物層包含SU8；選擇性地將該第一聚合物層移除，以提供至少一個開口來將一部份之晶粒曝光；以及將一第一金屬層沉積於該第一聚合物層上，該第一金屬層係至少部份地填滿該至少一個開口，以提供一電氣接觸至該晶粒，並且係包含一部份，該部份係大致上環繞於該第一金屬層之一上部表面的一平面中之晶粒，以提供一環繞於該晶粒之電磁遮蔽。
  2. 如申請專利範圍第1項之方法，其係進一步包括將一銲錫凸塊附接於該電氣接觸。
  3. 如申請專利範圍第1項之方法，其係進一步包括：將SU8的一第二聚合物層沉積於該第一金屬層上；及選擇性地將該SU8的第二聚合物層移除以提供一開口於該電氣接觸上，並且以允許存取該電氣接觸。
  4. 如申請專利範圍第3項之方法，其係進一步包括：將一第二金屬層沉積於該第二聚合物層上，該第二金屬層係經由該電氣接觸以被電氣連接至該第一金屬層。
  5. 如申請專利範圍第4項之方法，其係進一步包括：將一第三聚合物層沉積於該第二金屬層上；及選擇性地將該第三聚合物層之一部分移除以提供 存取該第二金屬層之一部分。
  6. 如申請專利範圍第5項之方法，其中沉積該第三聚合物層係包含沉積其中結合有一光學上不透光之添加物的一SU8層。
  7. 如申請專利範圍第1項之方法，其係進一步包括：將交錯的額外聚合物層和金屬層沉積於該第一金屬層上，該等交錯的額外聚合物層和金屬層係包含與該第一金屬層接觸的一第二SU8層和一最上面聚合物層；及將該第一金屬層和該等額外金屬層電氣互連，該第一金屬層和該等額外金屬層中至少一者係在該晶粒周圍提供電磁屏蔽。
  8. 如申請專利範圍第7項之方法，其中沉積該最上面聚合物層係包含沉積其中結合有一光學上不透光之添加物的一SU8層。
  9. 一種封裝一半導體晶粒之方法，該方法係包括：將該晶粒以一覆晶結構配置而黏著至一基板；將該晶粒以第一聚合物層塗佈；選擇性地將該第一聚合物層移除，以提供至少一個開口來將一部份之晶粒曝光；將一第一金屬層沉積於該第一聚合物層上，該第一金屬層係至少部份地填滿該至少一個開口，以提供一電氣接觸至該晶粒，並且係包含一部份，該部份係大致上環繞於該第一金屬層之一上部表面的一平面中之 晶粒，以提供一環繞於該晶粒之電磁遮蔽；將交錯的額外聚合物層和金屬層沉積於該第一金屬層上，該等交錯的額外聚合物層和金屬層係包含與該第一金屬層接觸的一第二SU8層和一最上面聚合物層；及將該第一金屬層和該等額外金屬層電氣互連，該第一金屬層和該等額外金屬層中至少一者係在該晶粒周圍提供電磁遮蔽。
  10. 如申請專利範圍第9項之方法，其中沉積該等額外聚合物層係包含沉積SU8層。
  11. 如申請專利範圍第9項之方法，其中沉積該最上面聚合物層係包含沉積其中包含一光學上不透光之添加物的一SU8層。
  12. 一種半導體元件之製造方法，該方法係包括：將複數個晶粒以各個晶粒彼此相隔一預定距離之方式而黏著至一半導體晶圓；將一第一SU8層佈置於該複數個晶粒上；選擇性地移除該第一SU8層以對該複數個晶粒中每一者提供至少一個存取點，且提供切割道來將該複數個晶粒之各別晶粒彼此分隔；將金屬接觸沉積在該第一SU8層上，該等金屬接觸係包含用於該複數個晶粒中每一者的至少一個電氣接觸，該至少一個電氣接觸係經由至該各別晶粒之相對應存取點所構成；以及將一金屬層沉積於該第一SU8層上，該金屬層形成至 少部份環繞該複數個晶粒中每個各別晶粒的一電磁遮蔽。
  13. 如申請專利範圍第12項之方法，其係進一步包括將一第二SU8層沉積於該金屬層上。
  14. 如申請專利範圍第13項之方法，其中沉積該第二SU8層係包含沉積其中包含結合有一光學上不透光之添加物的SU8之一層。
  15. 如申請專利範圍第13項之方法，其係進一步包括：將一額外金屬層沉積於該第二SU8層上；及將該額外金屬層電氣連接至該金屬層。
  16. 如申請專利範圍第15項之方法，其係進一步包括：將一第三SU8層沉積於該額外金屬層上；及選擇性地將該第三SU8層之一部分移除以提供存取該額外金屬層。
  17. 如申請專利範圍第12項之方法，其係進一步包括將銲錫凸塊附接於該等金屬接觸。
  18. 如申請專利範圍第17項之方法，其係進一步包括將沿著該等切割道單粒化該晶圓以提供獨立的半導體元件。
  19. 如申請專利範圍第12項之方法，其中將該複數個晶粒黏著至該半導體晶圓係包含以一覆晶結構配置來黏著該複數個晶粒中的各個晶粒。
  20. 如申請專利範圍第12項之方法，其中將該複數個晶粒黏著至該半導體晶圓係包含使用一環氧類樹脂和 一銲接製程中一者來黏著該複數個晶粒。
  21. 一種半導體模組之製造方法，每個模組係包括至少兩個晶粒，該方法係包括：將複數個晶粒附接於一電鍍基板，該複數個晶粒係以群組被安排來提供該等半導體模組，每個群組係包括至少兩個晶粒；將一第一SU8層佈置於該複數個晶粒上，及形成複數個開口於該第一SU8層中，以提供一第一各別存取點至該複數個晶粒中每一者；沉積一第一金屬層於該第一SU8層上以及至該複數個開口中，該第一金屬層係經由該等第一各別存取點來提供每個模組中至少兩個晶粒之間的一電氣連接；將一第二SU8層沉積於該第一金屬層上，及選擇性地移除該第一SU8層以提供至少一個第二存取點至每個棋組，並且以提供將各別模組彼此分隔的切割道；將金屬接觸沉積於該第一SU8層上，該等金屬接觸係包含至少一個用於每個模組之電氣接觸，該至少一個電氣接觸係經由至該各別模組之相對應第二存取點所構成；及將一第二金屬層沉積於該第二SU8層上，該第二金屬層係形成至少部份環繞於每個模組之一電磁遮蔽。
  22. 如申請專利範圍第21項之方法，其係進一步包括將沿著該等切割道單粒化該晶圓以提供獨立的半導體模組。
  23. 如申請專利範圍第21項之方法，其係進一步包括針對各個模組而將一銲錫凸塊附接於該至少一個電氣接觸。
  24. 如申請專利範圍第21項之方法，其係進一步包括：將一聚合物層沉積於該第二金屬層上；及選擇性地將該聚合物層之一部分移除以提供存取該第二金屬層。
  25. 如申請專利範圍第24項之方法，其中沉積該聚合物層係包含沉積其中包含結合有一光學上不透光之添加物的SU8之一層。
  26. 一種半導體元件，其係包括：一基板；一第一晶粒，其係以一覆晶結構配置而被附接於該基板，該第一晶粒係具有一上表面以及一下表面，該下表面係被佈置為相對於該上表面並且被黏著至該基板；一第一SU8層，其係被佈置於在該第一晶粒上之上表面上，該第一SU8層具有至少一個提供存取至該第一晶粒的開口；一第一金屬層，其係被佈置於該第一SU8層上，該第一金屬層係包括至少一個電氣接觸至該第一晶粒；以及一電磁遮蔽，其係至少部分地環繞於該第一晶粒。
  27. 如申請專利範圍第26項之半導體元件，其中該第一金屬層係包括該電磁遮蔽。
  28. 如申請專利範圍第27項之半導體元件，其係進一 步包括一被佈置於該電磁遮蔽上之第二SU8層。
  29. 如申請專利範圍第26項之半導體元件，其係進一步包括一被佈置於該第一金屬層上之第二SU8層，該第二SU8層係具有一開口以提供存取至該至少一個電氣接觸。
  30. 如申請專利範圍第29項之半導體元件，其係進一步包括一被佈置於該第二SU8層上之第二金屬層，該第二金屬層係包括至少一個凸塊接觸，該至少一個凸塊接觸係將該電氣接觸電氣耦合至該第一晶粒。
  31. 如申請專利範圍第30項之半導體元件，其係進一步包括一銲錫凸塊，該銲錫凸塊係被附接於該至少一個凸塊接觸，該銲錫凸塊係形成一球格陣列的部份。
  32. 如申請專利範圍第30項之半導體元件，其中該第二金屬層係包括該電磁遮蔽。
  33. 如申請專利範圍第29項之半導體元件，其中該第二SU8層係包含一光學上不透光之添加物。
  34. 如申請專利範圍第26項之半導體元件，其係進一步包括一第二晶粒，該第二晶粒係以一覆晶結構配置而被附接於該基板，其中該第一SU8層係被佈置於第二晶粒上，該第一金屬層係進一步包括在該第一晶粒與該第二晶粒之間的一互連，以及該電磁遮蔽係至少部份地環繞於該第一晶粒及該第二晶粒兩者。
  35. 一種半導體元件，其係包括：一基板； 一第一晶粒，其係以一覆晶結構配置而被附接於該基板，該第一晶粒係具有一上表面以及一下表面，該下表面係被佈置為相對於該上表面並且被黏著至該基板；一第一聚合物層，其係被佈置於該基板上且該第一晶粒之上表面上，該第一聚合物層係包括至少一個提供存取至該第一晶粒的開口；一第一金屬層，其係被佈置於該第一聚合物層上，該第一金屬層係包括至少一個電氣接觸至該第一晶粒；以及一電磁遮蔽，其係被形成在該第一金屬層中且在該第一金屬層之一上表面的一平面中環繞於該第一晶粒。
  36. 如申請專利範圍第35項之半導體元件，其中該第一聚合物層係由SU8所形成。
  37. 如申請專利範圍第35項之半導體元件，其係進一步包括一被佈置於該第一金屬層上之第二聚合物層，該第二聚合物層具有一開口以提供存取至該至少一個電氣接觸。
  38. 如申請專利範圍第37項之半導體元件，其中該第二聚合物層係包含結合有一光學上不透光之添加物的SU8。
  39. 如申請專利範圍第37項之半導體元件，其係進一步包括： 一第二金屬層，其被佈置在第二聚合物層上，該第二金屬層係經由該電氣接觸被電氣連接至該第一金屬層；及一第三聚合物層，其被佈置於該第二金屬層上，該第三聚合物層具有一開口以提供存取至該第二金屬層之一部分。
  40. 如申請專利範圍第39項之半導體元件，其中該第三聚合物層係包含結合有一光學上不透光之添加物的SU8。
  41. 如申請專利範圍第35項之半導體元件，其係進一步包括以一覆晶結構配置而被附接於該基板之一第二晶粒，其中該第一聚合物層係被佈置於該第二晶粒上，該第一金屬層係進一步包含在該第一晶粒與該第二晶粒之間的一互連，且該電磁遮蔽係在第一金屬層之上表面的平面中環繞於該第一晶粒及該第二晶粒兩者。
  42. 如申請專利範圍第35項之半導體元件，其係進一步包括經附接於該電氣接觸之一銲錫凸塊。
  43. 一種半導體元件，其係包括：一基板；一第一晶粒，其係以一覆晶結構配置而被附接於該基板，該第一晶粒係具有一上表面以及一下表面，該下表面係被佈置為相對於該上表面並且被黏著至該基板；一第一聚合物層，其係被佈置於該第一晶粒上之上表面上，該第一聚合物層係包括至少一個提供存取至該 第一晶粒的開口；一第一金屬層，其係被佈置於該第一聚合物層上，該第一金屬層係包括至少一個電氣接觸至該第一晶粒；交錯的額外聚合物層和金屬層，其係被佈置於該第一金屬層上，該等交錯的額外聚合物層和金屬層係包含與該第一金屬層接觸的一第二聚合物層和一最上面聚合物層；以及一電磁遮蔽，其係包含該第一金屬層之一部分，以大致上在該第一金屬層之一上表面的一平面中環繞於該第一晶粒，來提供一電磁遮蔽環繞於晶粒，該第一金屬層和該等額外金屬層係經電氣連接且該電磁遮蔽係包含該第一金屬層之一部分和該等額外金屬層中至少一者的至少一部分。
  44. 如申請專利範圍第43項之半導體元件，其中該最上面聚合物層係包含結合有一光學上不透光之添加物的SU8。
  45. 如申請專利範圍第43項之半導體元件，其係進一步包括以一覆晶結構配置而被附接於該基板之一第二晶粒，其中該第一聚合物層係被佈置於該第二晶粒上，該第一金屬層係進一步包含在該第一晶粒與該第二晶粒之間的一互連，且該電磁遮蔽係在第一金屬層之上表面的平面中環繞於該第一晶粒及該第二晶粒兩者。
  46. 如申請專利範圍第43項之半導體元件，其像進一 步包括以一覆晶結構配置而被附接於該基板之一第二晶粒，其中該第一聚合物層係被佈置於該第二晶粒上。
  47. 如申請專利範圍第46項之半導體元件，其中該第一金屬層係進一步包括在該第一晶粒與該第二晶粒之間的一互連。
  48. 一種半導體元件之製造方法，該方法係包括：將複數個晶粒以各個晶粒彼此相隔一預定距離之方式而黏著至一半導體晶圓；將一第一聚合物層沉積於該複數個晶粒上；選擇性地移除該第一聚合物層以提供至少一個存取點至該複數個晶粒中每一者，且提供切割道來將該複數個晶粒中之各別晶粒彼此分隔；將金層接觸沉積在該第一聚合物層上，該等金屬接觸係包含至少一個用於該複數個晶粒中各個晶粒的電氣接觸，該至少一個電氣接觸係經由至該各別晶粒之相對應存取點所構成；將一第一金屬層沉積於該第一聚合物層上，該第一金屬層係形成至少部份環繞於該複數個晶粒中每個各別晶粒的一電磁遮蔽；將交錯的額外聚合物層和金屬層沉積於該第一金屬層上，該等交錯的額外聚合物層和金屬層係包含與該第一金屬層接觸的一第二聚合物層和一最上面聚合物層；及將該第一金屬層和該等額外金屬層中至少一者電氣 互連，該第一金屬層和該等額外金屬層中至少一者係在該晶粒周圍提供電磁屏蔽。
  49. 如申請專利範圍第48項之方法，其中沉積該第一聚合物層和該等額外聚合物層係包括沉積SU8層。
  50. 如申請專利範圍第48項之方法，其中沉積該最上面聚合物層係包括沉積包含光學上不透光之添加物的SU8層。
  51. 一種半導體模組之製造方法，每個模組係包括至少兩個晶粒，該方法係包括：將複數個晶粒以各個晶粒彼此相隔一預定距離之方式而附接於一半導體晶圓，該複數個晶粒係以群組被安排來提供該等半導體模組，每個群組係包括至少兩個晶粒；將一第一聚合物層佈置於該複數個晶粒上；選擇性地移除該第一聚合物層以提供至少一個存取點至該複數個晶粒中每一者，並且提供將該複數個晶粒中之各別晶粒彼此分隔的切割道；將金屬接觸沉積於該第一聚合物層上，該等金屬接觸係包含至少一個用於該複數個晶粒中各個晶粒之電氣接觸，該至少一個電氣接觸係經由至該各別晶粒之相對應存取點所構成；電氣連接各個半導體模組之至少兩個晶粒；以及將一第一金屬層沉積於該第一聚合物層上，該第一金屬層係形成至少部份環撓於每個模組之一電磁遮 蔽。
  52. 如申請專利範圍第51項之方法，其中將該複數個晶粒附接於該半導體晶圓係包括以一覆晶結構配置將該複數個晶粒中的各個晶粒附接於該半導體晶圓。
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