TW200612530A - Method for fabricating thermally enhanced and directly connected semiconductor device - Google Patents

Method for fabricating thermally enhanced and directly connected semiconductor device

Info

Publication number
TW200612530A
TW200612530A TW093131116A TW93131116A TW200612530A TW 200612530 A TW200612530 A TW 200612530A TW 093131116 A TW093131116 A TW 093131116A TW 93131116 A TW93131116 A TW 93131116A TW 200612530 A TW200612530 A TW 200612530A
Authority
TW
Taiwan
Prior art keywords
semiconductor device
directly connected
chips
thermally enhanced
circuit structure
Prior art date
Application number
TW093131116A
Other languages
Chinese (zh)
Other versions
TWI238506B (en
Inventor
Chu-Chin Hu
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW093131116A priority Critical patent/TWI238506B/en
Application granted granted Critical
Publication of TWI238506B publication Critical patent/TWI238506B/en
Publication of TW200612530A publication Critical patent/TW200612530A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Abstract

A method for fabricating a thermally enhanced and directly connected semiconductor device is proposed, wherein a plurality of chips are disposed on a heat sink and at least an insulating layer is formed on the chips and heat sink. At lest a circuit structure is formed on the insulating layer and electrically connected to the chips. There can be provided a plurality of semiconductor devices, each comprising a hest sink, chip and circuit structure electrically extended form the chip, in strip or single type via a singulation process. A plurality of conductive elements used for electrical connection to outside can be formed on the outer surface of the circuit structure.
TW093131116A 2004-10-14 2004-10-14 Method for fabricating thermally enhanced and directly connected semiconductor device TWI238506B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW093131116A TWI238506B (en) 2004-10-14 2004-10-14 Method for fabricating thermally enhanced and directly connected semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093131116A TWI238506B (en) 2004-10-14 2004-10-14 Method for fabricating thermally enhanced and directly connected semiconductor device

Publications (2)

Publication Number Publication Date
TWI238506B TWI238506B (en) 2005-08-21
TW200612530A true TW200612530A (en) 2006-04-16

Family

ID=37000289

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093131116A TWI238506B (en) 2004-10-14 2004-10-14 Method for fabricating thermally enhanced and directly connected semiconductor device

Country Status (1)

Country Link
TW (1) TWI238506B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI455219B (en) * 2007-08-07 2014-10-01 Skyworks Solutions Inc Near chip scale package integration process
CN109935557A (en) * 2017-12-19 2019-06-25 凤凰先驱股份有限公司 Electronic packing piece and its preparation method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI455219B (en) * 2007-08-07 2014-10-01 Skyworks Solutions Inc Near chip scale package integration process
CN109935557A (en) * 2017-12-19 2019-06-25 凤凰先驱股份有限公司 Electronic packing piece and its preparation method
CN109935557B (en) * 2017-12-19 2023-05-30 恒劲科技股份有限公司 Electronic package and method for manufacturing the same

Also Published As

Publication number Publication date
TWI238506B (en) 2005-08-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees