TWI430413B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- TWI430413B TWI430413B TW98108539A TW98108539A TWI430413B TW I430413 B TWI430413 B TW I430413B TW 98108539 A TW98108539 A TW 98108539A TW 98108539 A TW98108539 A TW 98108539A TW I430413 B TWI430413 B TW I430413B
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- H—ELECTRICITY
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Description
本發明係有關於一種在半導體晶片的側面形成側面配線的半導體裝置，特別係有關於一種容易製造且可縮小晶片面積的半導體裝置。The present invention relates to a semiconductor device in which side wiring is formed on a side surface of a semiconductor wafer, and more particularly to a semiconductor device which is easy to manufacture and which can reduce the area of the wafer.
在半導體晶片被安裝於搭載部的半導體裝置中，為了接續半導體晶片的電子電路及搭載部的電極，使用打線接合、覆晶封裝、側面配線等。透過切斷被設置在半導體晶圓的切割線上的貫通孔，側面配線被形成於半導體晶片的側面(例如，參閱專利文獻1)。In the semiconductor device in which the semiconductor wafer is mounted on the mounting portion, wire bonding, flip chip mounting, side wiring, or the like is used in order to connect the electronic circuit of the semiconductor wafer and the electrode of the mounting portion. The side wiring is formed on the side surface of the semiconductor wafer by cutting the through hole provided in the dicing line of the semiconductor wafer (for example, see Patent Document 1).
[專利文獻1]特開平6-120294號公報[Patent Document 1] JP-A-6-120294
目前為止係在半導體晶片的邊上形成側面配線。因此，由1個貫通孔形成2個半導體晶片的側面配線。所以，因為必須在半導體晶圓上形成許多貫通孔，使得晶圓的強度變弱，故製造困難。又，因為側面配線的面積係1/2個貫通孔的大小，而有晶片面積變大的問題。Surface wiring has been formed on the side of a semiconductor wafer so far. Therefore, the side wiring of two semiconductor wafers is formed by one through hole. Therefore, since a large number of through holes must be formed on the semiconductor wafer, the strength of the wafer is weakened, which is difficult to manufacture. Moreover, since the area of the side wiring is the size of 1/2 through holes, there is a problem that the wafer area becomes large.
又，在半導體晶片的頂面，為了接續電子電路及側面配線而形成頂面配線。目前為止，在頂面配線之頂面的外周內的長度係與側面配線相同。因此，當側面配線的位置改變時，因為側面配線未被接續至頂面配線，故側面配線之位置的自由度低。Further, on the top surface of the semiconductor wafer, a top surface wiring is formed in order to connect the electronic circuit and the side wiring. Up to now, the length in the outer circumference of the top surface of the top wiring is the same as that of the side wiring. Therefore, when the position of the side wiring is changed, since the side wiring is not connected to the top wiring, the degree of freedom of the position of the side wiring is low.
為了解決上述問題，本發明之第1目的在於得到一種半導體裝置，其容易製造且可縮小晶片面積。第2目的在於得到一種半導體裝置，其可提升側面配線之位置的自由度。In order to solve the above problems, a first object of the present invention is to provide a semiconductor device which is easy to manufacture and which can reduce the wafer area. A second object is to obtain a semiconductor device which can increase the degree of freedom of the position of the side wiring.
第1發明係一種半導體裝置，其特徵為包括：半導體晶片，具有頂面及底面與連結前述頂面及前述底面的側面；電子電路，形成在前述頂面；底面電極，形成在前述底面；及側面配線，在前述半導體晶片的角中，被形成在前述側面上，接續前述電子電路及前述底面電極。According to a first aspect of the invention, a semiconductor device includes: a semiconductor wafer having a top surface and a bottom surface; and a side surface connecting the top surface and the bottom surface; an electronic circuit formed on the top surface; and a bottom electrode formed on the bottom surface; The side wiring is formed on the side surface of the semiconductor wafer at the corner of the semiconductor wafer to connect the electronic circuit and the bottom surface electrode.
第2發明係一種半導體裝置，其特徵為包括：半導體晶片，具有頂面及底面與連結前述頂面及前述底面的側面；頂面配線，在前述頂面中沿著前述頂面的外周形成；電子電路，被形成於前述頂面，且被接續至前述頂面配線；底面電極，形成在前述底面；及側面配線，被形成在前述半導體晶片的前述側面上，且接續前述頂面配線及前述底面電極，且前述頂面配線之前述頂面的外周內的長度係前述頂面的一邊以上。According to a second aspect of the invention, a semiconductor device includes: a semiconductor wafer having a top surface and a bottom surface; and a side surface connecting the top surface and the bottom surface; and a top surface wiring formed along an outer circumference of the top surface in the top surface; An electronic circuit is formed on the top surface and connected to the top surface wiring; a bottom surface electrode is formed on the bottom surface; and a side surface wiring is formed on the side surface of the semiconductor wafer, and the top surface wiring and the foregoing The bottom electrode has a length in the outer circumference of the top surface of the top wiring which is one side or more of the top surface.
透過第1發明，可得到容易製造且可縮小晶片面積的半導體裝置。透過第2發明，可提升側面配線之位置的自由度。According to the first aspect of the invention, it is possible to obtain a semiconductor device which is easy to manufacture and which can reduce the area of the wafer. According to the second invention, the degree of freedom of the position of the side wiring can be improved.
圖1、2係繪示實施例1的半導體晶片之立體圖。半導體晶片10係具有彼此相對的頂面及底面、與連接頂面及底面的側面。半導體晶片10的頂面係四角形，其具有角12a、鄰接角12a的角12b、存在於角12a的對角線上之角12c、及存在於角12b的對角線上之角12d。1 and 2 are perspective views of the semiconductor wafer of the first embodiment. The semiconductor wafer 10 has a top surface and a bottom surface that face each other, and side surfaces that connect the top surface and the bottom surface. The top surface of the semiconductor wafer 10 has a quadrangular shape having an angle 12a, an angle 12b of the abutment angle 12a, an angle 12c existing on the diagonal of the corner 12a, and an angle 12d existing on the diagonal of the corner 12b.
在半導體晶片10的頂面中，形成頂面配線14a以連接角12a及角12b，且形成頂面配線14b以連接角12c及角12d。在半導體晶片10的頂面形成電子電路16。電子電路16具有被接續至頂面配線14a的輸入端子16b，及被接續至頂面配線14b的輸出端子16a。在半導體晶片10之對應於頂面的角12a之底面的角上形成底面電極18a，在對應於角12c之底面的角上形成底面電極18b。In the top surface of the semiconductor wafer 10, a top surface wiring 14a is formed to connect the corners 12a and 12b, and a top surface wiring 14b is formed to connect the corners 12c and 12d. An electronic circuit 16 is formed on the top surface of the semiconductor wafer 10. The electronic circuit 16 has an input terminal 16b that is connected to the top surface wiring 14a, and an output terminal 16a that is connected to the top surface wiring 14b. The bottom surface electrode 18a is formed at an angle of the bottom surface of the semiconductor wafer 10 corresponding to the bottom surface of the corner 12a, and the bottom surface electrode 18b is formed at an angle corresponding to the bottom surface of the corner 12c.
在半導體晶片10的角12a中，在側面上形成側面配線20a，在半導體晶片10的角12c中，在側面上形成側面配線20b。側面配線20a接續頂面配線14a及底面電極18a。側面配線20b接續頂面配線14b及底面電極18b。電子電路16的輸入端子16b經由頂面配線14a被接續至側面配線20a。輸出端子16a經由頂面配線14b被接續至側面配線20b。In the corner 12a of the semiconductor wafer 10, the side wiring 20a is formed on the side surface, and in the corner 12c of the semiconductor wafer 10, the side wiring 20b is formed on the side surface. The side wiring 20a is connected to the top surface wiring 14a and the bottom surface electrode 18a. The side wiring 20b is connected to the top surface wiring 14b and the bottom surface electrode 18b. The input terminal 16b of the electronic circuit 16 is connected to the side wiring 20a via the top surface wiring 14a. The output terminal 16a is connected to the side wiring 20b via the top surface wiring 14b.
圖3係繪示實施例1的半導體裝置之剖面圖。在搭載部22的表面上使用焊錫或導電漿安裝半導體晶片10。半導體晶片10係由成型樹脂24封裝。如此，因為可不使用導線配線而搭載半導體晶片10，故可縮小封裝的體積。3 is a cross-sectional view showing the semiconductor device of Embodiment 1. The semiconductor wafer 10 is mounted on the surface of the mounting portion 22 using solder or a conductive paste. The semiconductor wafer 10 is encapsulated by a molding resin 24. In this way, since the semiconductor wafer 10 can be mounted without using the wire harness, the volume of the package can be reduced.
圖4、5係繪示將實施例1的半導體晶片搭載於搭載部的情況之立體圖。在搭載部22的表面中，配置表面電極24a~24d以構成四角形。表面電極24b鄰接於表面電極24a。表面電極24c存在於表面電極24a的對角線上。表面電極24d存在於表面電極24b的對角線上。4 and 5 are perspective views showing a state in which the semiconductor wafer of the first embodiment is mounted on a mounting portion. The surface electrodes 24a to 24d are disposed on the surface of the mounting portion 22 to form a quadrangular shape. The surface electrode 24b is adjacent to the surface electrode 24a. The surface electrode 24c exists on the diagonal line of the surface electrode 24a. The surface electrode 24d exists on the diagonal of the surface electrode 24b.
表面配線26a被接續至表面電極24a、24b。電感器28被接續至表面電極24b及表面配線26a之間。因此，從表面配線26a經由電感器28傳送至表面電極24b的微波或毫米波的信號，相對於從表面配線26a傳送至表面電極24a的信號，其振幅及相位不同。又，表面配線26b被接續至表面電極24c、24d。The surface wiring 26a is connected to the surface electrodes 24a, 24b. The inductor 28 is connected between the surface electrode 24b and the surface wiring 26a. Therefore, the signal of the microwave or the millimeter wave transmitted from the surface wiring 26a to the surface electrode 24b via the inductor 28 is different in amplitude and phase with respect to the signal transmitted from the surface wiring 26a to the surface electrode 24a. Moreover, the surface wiring 26b is connected to the surface electrodes 24c and 24d.
在將半導體晶片10搭載於搭載部22時，如圖4所示，底面電極18a被接續至表面電極24a，且底面電極18b被接續至表面電極24c。或者，將半導體晶片10旋轉90度，如圖5所示，底面電極18a被接續至表面電極24b，且底面電極18b被接續至表面電極24d。When the semiconductor wafer 10 is mounted on the mounting portion 22, as shown in FIG. 4, the bottom surface electrode 18a is connected to the surface electrode 24a, and the bottom surface electrode 18b is connected to the surface electrode 24c. Alternatively, the semiconductor wafer 10 is rotated by 90 degrees. As shown in FIG. 5, the bottom electrode 18a is connected to the surface electrode 24b, and the bottom electrode 18b is connected to the surface electrode 24d.
接著，說明實施例1的半導體晶片的製造方法。圖6係繪示製造實施例1的半導體晶片之製程的立體圖。在半導體晶圓30上行列狀地形成複數個電子電路16。其次，在每個個別的電子電路16上形成頂面配線14a、14b。接著，在切割線32的交叉點上形成貫通孔34。使此貫通孔34的內部金屬化。其後，在半導體晶片10的底面形成底面電極18a、18b。然後，沿著切割線32切割半導體晶圓30，以使個別的半導體晶片10分離。此時，利用切斷貫通孔34，形成側面配線20a、20b。透過上面的製程，半導體晶片10被製造。Next, a method of manufacturing the semiconductor wafer of the first embodiment will be described. 6 is a perspective view showing a process of manufacturing the semiconductor wafer of Embodiment 1. A plurality of electronic circuits 16 are formed in the semiconductor wafer 30 in an ascending manner. Next, top surface wirings 14a, 14b are formed on each of the individual electronic circuits 16. Next, a through hole 34 is formed at the intersection of the dicing lines 32. The inside of the through hole 34 is made metallized. Thereafter, the bottom electrodes 18a and 18b are formed on the bottom surface of the semiconductor wafer 10. The semiconductor wafer 30 is then diced along the dicing lines 32 to separate the individual semiconductor wafers 10. At this time, the side wirings 20a and 20b are formed by cutting the through holes 34. Through the above process, the semiconductor wafer 10 is fabricated.
如上述說明，在實施例1中，在半導體晶片的角上形成側面配線。因此，如圖6所示，可由1個貫通孔形成4個半導體晶片的側面配線。所以，與在半導體晶片的邊上形成側面配線的情況相比，因為可將形成於晶圓面內的貫通孔的數目減少一半，且可增強晶圓的強度，所以容易製造。又，因為可將側面配線的面積從半個貫通孔的大小減少為四分之一個，所以可縮小晶片面積。As described above, in the first embodiment, the side wiring is formed on the corners of the semiconductor wafer. Therefore, as shown in FIG. 6, the side wiring of four semiconductor wafers can be formed by one through-hole. Therefore, compared with the case where the side wiring is formed on the side of the semiconductor wafer, since the number of through holes formed in the wafer surface can be reduced by half, and the strength of the wafer can be enhanced, it is easy to manufacture. Moreover, since the area of the side wiring can be reduced from the size of the half through hole to one quarter, the wafer area can be reduced.
又，如圖6所示，每個毗連的晶片之貫通孔的位置改變。相對於此，在實施例1中，頂面配線被形成以連接彼此鄰接的2個角，且電子電路係經由頂面配線被接續至側面配線。因此，舉例而言，不論是貫通孔34位於角12a中時或位於角12b中時，貫通孔34都經由頂面配線14a被接續至電子電路16。所以，因為在各晶片上可使用共同的表面佈局，比起對每個晶片改變佈局的情況，可使設計工作更加省力。Further, as shown in Fig. 6, the position of the through hole of each of the adjacent wafers is changed. On the other hand, in the first embodiment, the top surface wiring is formed to connect the two corners adjacent to each other, and the electronic circuit is connected to the side wiring via the top surface wiring. Therefore, for example, when the through hole 34 is located in the corner 12a or in the corner 12b, the through hole 34 is connected to the electronic circuit 16 via the top surface wiring 14a. Therefore, because a common surface layout can be used on each wafer, the design work can be made more labor-saving than when the layout is changed for each wafer.
又，目前為止係根據想得到的半導體裝置的特性，而必須個別地準備形成有必要的阻抗之表面配線的搭載部。相對於此，在實施例1中，透過將半導體晶片如圖4所示或如圖5所示搭載於搭載部，可改變信號的振幅及相位。因此，使用相同的半導體晶片及搭載部可得到不同特性的半導體裝置。In addition, it has been necessary to separately prepare a mounting portion for forming a surface wiring having a necessary impedance in accordance with the characteristics of the semiconductor device to be obtained. On the other hand, in the first embodiment, the amplitude and phase of the signal can be changed by transmitting the semiconductor wafer to the mounting portion as shown in FIG. 4 or as shown in FIG. 5. Therefore, a semiconductor device having different characteristics can be obtained by using the same semiconductor wafer and the mounting portion.
再者，在實施例1中，雖然係說明在半導體晶片的2個角上形成側面配線的半導體裝置，但不限定於此，也可在半導體晶片的1個、3個或4個角上形成側面配線。又，可使用陶瓷封裝等取代成型樹脂。Further, in the first embodiment, a semiconductor device in which side wirings are formed on two corners of a semiconductor wafer is described. However, the present invention is not limited thereto, and may be formed on one, three or four corners of the semiconductor wafer. Side wiring. Further, a molding resin or the like can be used instead of the molding resin.
又，在實施例1中，雖然使用電感器28做為阻抗變換電路，但不限於此，也可使用電阻器、電容器、線等可變換阻抗者。Further, in the first embodiment, the inductor 28 is used as the impedance conversion circuit. However, the present invention is not limited thereto, and a resistor, a capacitor, a line, or the like may be used.
又，雖然說明將半導體晶片旋轉90度以搭載於搭載部的半導體裝置，但不限定於此，也可使半導體晶片的旋轉角度為60度或45度等任意的角度。In addition, although the semiconductor device in which the semiconductor wafer is rotated by 90 degrees to be mounted on the mounting portion is described, the present invention is not limited thereto, and the rotation angle of the semiconductor wafer may be an arbitrary angle such as 60 degrees or 45 degrees.
又，雖然說明對於1個底面電極存在2個可接續的表面電極之半導體裝置，可接續至1個底面電極的表面電極也可為3個以上，且在該表面電極及表面配線之間也可分別接續不同的電感器或電阻器等。Further, although a semiconductor device in which two surface electrodes are connected to one bottom electrode is described, the number of surface electrodes that can be connected to one bottom electrode may be three or more, and the surface electrode and the surface wiring may be provided between the surface electrodes and the surface wiring. Connect different inductors or resistors, etc. respectively.
圖7係繪示實施例2的半導體晶片之立體圖。半導體晶片10係具有彼此相對的頂面及底面與連接頂面及底面的側面。半導體晶片10的頂面係四角形。Fig. 7 is a perspective view showing the semiconductor wafer of the second embodiment. The semiconductor wafer 10 has a top surface and a bottom surface opposed to each other and a side surface connecting the top surface and the bottom surface. The top surface of the semiconductor wafer 10 is quadrangular.
在半導體晶片10的頂面中，沿著頂面的外周形成頂面配線14。在半導體晶片10的頂面形成電子電路16。電子電路16具有被接續至頂面配線14的輸入端子16b及被接續至打線墊36的輸出端子16a。在半導體晶片10的底面形成底面電極18。In the top surface of the semiconductor wafer 10, a top surface wiring 14 is formed along the outer circumference of the top surface. An electronic circuit 16 is formed on the top surface of the semiconductor wafer 10. The electronic circuit 16 has an input terminal 16b that is connected to the top surface wiring 14 and an output terminal 16a that is connected to the wire bonding pad 36. A bottom electrode 18 is formed on the bottom surface of the semiconductor wafer 10.
在半導體晶片10的側面形成側面配線20。側面配線20接續頂面配線14及底面電極18。電子電路16的輸入端子16b係經由頂面配線14被接續至側面配線20。The side wiring 20 is formed on the side surface of the semiconductor wafer 10. The side wiring 20 connects the top surface wiring 14 and the bottom surface electrode 18. The input terminal 16b of the electronic circuit 16 is connected to the side wiring 20 via the top surface wiring 14.
其次，說明實施例2的半導體晶片的製造方法。圖8係繪示製造實施例2的半導體晶片之製程的立體圖。在半導體晶圓30上行列狀地形成複數個電子電路16。其次，在每個個別的電子電路16上形成頂面配線14。接著，在切割線32上形成貫通孔34。使此貫通孔34的內部金屬化。其後，在半導體晶片10的底面形成底面電極18。然後，沿著切割線32切割半導體晶圓30，以使個別的半導體晶片10分離。此時，利用切斷貫通孔34，形成側面配線20。透過上面的製程，半導體晶片10被製造。Next, a method of manufacturing the semiconductor wafer of the second embodiment will be described. 8 is a perspective view showing a process of manufacturing the semiconductor wafer of Embodiment 2. A plurality of electronic circuits 16 are formed in the semiconductor wafer 30 in an ascending manner. Next, a top wiring 14 is formed on each of the individual electronic circuits 16. Next, a through hole 34 is formed in the dicing line 32. The inside of the through hole 34 is made metallized. Thereafter, the bottom surface electrode 18 is formed on the bottom surface of the semiconductor wafer 10. The semiconductor wafer 30 is then diced along the dicing lines 32 to separate the individual semiconductor wafers 10. At this time, the side wiring 20 is formed by cutting the through hole 34. Through the above process, the semiconductor wafer 10 is fabricated.
如上述說明，在實施例2中係被形成以連接半導體晶片10的頂面的4個邊及全部的4個角。因此，如圖8所示，在半導體晶片10的外周的任何地方形成側面配線20，側面配線20均電氣地接續至頂面配線14。因此，可提升側面配線20之位置的自由度。As described above, in the second embodiment, four sides and all four corners of the top surface of the semiconductor wafer 10 are formed. Therefore, as shown in FIG. 8, the side wiring 20 is formed anywhere on the outer circumference of the semiconductor wafer 10, and the side wirings 20 are electrically connected to the top wiring 14. Therefore, the degree of freedom of the position of the side wiring 20 can be improved.
再者，如上述，即使未在半導體晶片10的整個外周形成頂面配線14，頂面配線14的頂面的外周內之長度可為頂面的一邊以上。結果，因為可在形成頂面配線14的半導體晶片10的邊或角的任意位置上形成側面配線20，可提升側面配線20之位置的自由度。Further, as described above, even if the top surface wiring 14 is not formed on the entire outer circumference of the semiconductor wafer 10, the length in the outer circumference of the top surface of the top surface wiring 14 can be one side or more of the top surface. As a result, since the side wiring 20 can be formed at any position of the side or corner of the semiconductor wafer 10 on which the top wiring 14 is formed, the degree of freedom of the position of the side wiring 20 can be improved.
10．．．半導體晶片10. . . Semiconductor wafer
12a．．．角(第1角)12a. . . Corner (1st corner)
12b．．．角(第2角)12b. . . Corner (2nd corner)
12c．．．角(第3角)12c. . . Corner (3rd corner)
12d．．．角(第4角)12d. . . Corner (fourth corner)
14．．．頂面配線14. . . Top wiring
14a．．．頂面配線(第1頂面配線)14a. . . Top wiring (1st top wiring)
14b．．．頂面配線(第2頂面配線)14b. . . Top wiring (2nd top wiring)
16．．．電子電路16. . . electronic circuit
16a．．．輸出端子(第2端子)16a. . . Output terminal (2nd terminal)
16b．．．輸入端子(第1端子)16b. . . Input terminal (1st terminal)
18．．．底面電極18. . . Bottom electrode
18a．．．底面電極(第1底面電極)18a. . . Bottom electrode (first bottom electrode)
18b．．．底面電極(第2底面電極)18b. . . Bottom electrode (second bottom electrode)
20．．．側面配線20. . . Side wiring
20a．．．側面配線(第1側面配線)20a. . . Side wiring (first side wiring)
20b．．．側面配線(第2側面配線)20b. . . Side wiring (2nd side wiring)
22．．．搭載部twenty two. . . Mounting department
24a．．．表面電極(第1表面電極)24a. . . Surface electrode (first surface electrode)
24b．．．表面電極(第2表面電極)24b. . . Surface electrode (second surface electrode)
24c．．．表面電極(第3表面電極)24c. . . Surface electrode (third surface electrode)
24d．．．表面電極(第4表面電極)24d. . . Surface electrode (fourth surface electrode)
26a．．．表面配線(第1表面配線)26a. . . Surface wiring (first surface wiring)
26b．．．表面配線(第2表面配線)26b. . . Surface wiring (second surface wiring)
28．．．電感器(阻抗變換電路)28. . . Inductor (impedance conversion circuit)
圖1係繪示實施例1的半導體晶片之立體圖。1 is a perspective view showing a semiconductor wafer of Embodiment 1.
圖2係繪示實施例1的半導體晶片之立體圖。2 is a perspective view showing the semiconductor wafer of Embodiment 1.
圖3係繪示實施例1的半導體裝置之剖面圖。3 is a cross-sectional view showing the semiconductor device of Embodiment 1.
圖4係繪示將實施例1的半導體晶片搭載於搭載部的情況之立體圖。4 is a perspective view showing a state in which the semiconductor wafer of the first embodiment is mounted on a mounting portion.
圖5係繪示將實施例1的半導體晶片搭載於搭載部的情況之立體圖。FIG. 5 is a perspective view showing a state in which the semiconductor wafer of the first embodiment is mounted on a mounting portion.
圖6係繪示製造實施例1的半導體晶片之製程的立體圖。6 is a perspective view showing a process of manufacturing the semiconductor wafer of Embodiment 1.
圖7係繪示實施例2的半導體晶片之立體圖。Fig. 7 is a perspective view showing the semiconductor wafer of the second embodiment.
圖8係繪示製造實施例2的半導體晶片之製程的立體圖。8 is a perspective view showing a process of manufacturing the semiconductor wafer of Embodiment 2.
10．．．半導體晶片10. . . Semiconductor wafer
12a~12d．．．角12a~12d. . . angle
14a、14b．．．頂面配線14a, 14b. . . Top wiring
16．．．電子電路16. . . electronic circuit
16a．．．輸出端子16a. . . Output terminal
16b．．．輸入端子16b. . . Input terminal
18a．．．底面電極18a. . . Bottom electrode
20a、20b．．．側面電極20a, 20b. . . Side electrode
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009008970A JP5218087B2 (en) | 2009-01-19 | 2009-01-19 | Semiconductor device |
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|---|---|
| TW201029128A TW201029128A (en) | 2010-08-01 |
| TWI430413B true TWI430413B (en) | 2014-03-11 |
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| JP (1) | JP5218087B2 (en) |
| CN (1) | CN101783335B (en) |
| TW (1) | TWI430413B (en) |
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| DE112014003071T5 (en) * | 2014-06-09 | 2016-03-10 | Mitsubishi Electric Corporation | Manufacturing Method for Semiconductor Package and Semiconductor Package |
| JP7194518B2 (en) | 2018-05-31 | 2022-12-22 | 浜松ホトニクス株式会社 | Electronic component, method for manufacturing electronic component, electronic device |
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| JP3147666B2 (en) * | 1994-07-21 | 2001-03-19 | 株式会社村田製作所 | Multilayer electronic component and method of manufacturing the same |
| JPH10284935A (en) * | 1997-04-09 | 1998-10-23 | Murata Mfg Co Ltd | Voltage-controlled oscillator and its production |
| CN1204227A (en) * | 1997-05-12 | 1999-01-06 | 阿尔卑斯电气株式会社 | Printed circuit board |
| JPH11204519A (en) * | 1998-01-08 | 1999-07-30 | Matsushita Electron Corp | Semiconductor device and its manufacture |
| JP2001332579A (en) * | 2000-05-19 | 2001-11-30 | Advantest Corp | Semiconductor circuit device and method of manufacturing the same |
| JP3882521B2 (en) * | 2001-03-29 | 2007-02-21 | セイコーエプソン株式会社 | Mounting method of semiconductor device |
| JP2002359320A (en) * | 2001-06-01 | 2002-12-13 | Toyo Commun Equip Co Ltd | Outer electrode pattern of electronic component |
| JP2004221372A (en) * | 2003-01-16 | 2004-08-05 | Seiko Epson Corp | Semiconductor device, semiconductor module, method of manufacturing both the same and electronic apparatus |
| JP2005019730A (en) * | 2003-06-26 | 2005-01-20 | Kyocera Corp | Wiring substrate and electronic device using it |
| JP2005072050A (en) * | 2003-08-27 | 2005-03-17 | Citizen Watch Co Ltd | Electronic device substrate, electronic device, and manufacturing method thereof |
| JP4443397B2 (en) * | 2004-12-13 | 2010-03-31 | シチズン電子株式会社 | Optical semiconductor element, optical semiconductor device, and method of manufacturing optical semiconductor element |
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| JP2010165991A (en) | 2010-07-29 |
| TW201029128A (en) | 2010-08-01 |
| JP5218087B2 (en) | 2013-06-26 |
| CN101783335B (en) | 2012-04-11 |
| CN101783335A (en) | 2010-07-21 |
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