TWI591779B - Semiconductor package and manufacturing method thereof - Google Patents
Semiconductor package and manufacturing method thereof Download PDFInfo
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- TWI591779B TWI591779B TW101123545A TW101123545A TWI591779B TW I591779 B TWI591779 B TW I591779B TW 101123545 A TW101123545 A TW 101123545A TW 101123545 A TW101123545 A TW 101123545A TW I591779 B TWI591779 B TW I591779B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
Description
本發明關於一種半導體封裝及其製造方法，且特別是有關於一種半導體封裝及其半導體封裝製造方法，其為一種半導體晶片利用第二焊球而變更為連接於安裝板的形態，從而無需增加焊球的數量而增加外露的焊球數量，從而擴大實質的輸入/輸出引線數量。 The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package and a semiconductor package manufacturing method thereof, wherein a semiconductor wafer is changed to a connection pattern by using a second solder ball, thereby eliminating the need for additional soldering. The number of balls increases the number of exposed solder balls, thereby expanding the number of substantial input/output leads.
最近，隨著電子元件的發展與使用者的需求，對電子產品的需要越來越趨向小型化、輕量化及多功能化。隨著這樣的要求，搭載半導體元件的封裝技術中，能在最小的空間內安裝更多量的半導體晶片的多晶片封裝(multi chip package)及晶片級封裝(Chip Scale Package，CSP)成為主流。系統級封裝(System In Package,SiP)技術即為此種封裝技術的其中一種。 Recently, with the development of electronic components and the needs of users, the demand for electronic products has become increasingly smaller, lighter, and more multifunctional. With such a demand, in a packaging technology in which a semiconductor element is mounted, a multi-chip package and a chip scale package (CSP) capable of mounting a larger number of semiconductor wafers in a minimum space have become mainstream. System In Package (SiP) technology is one of such packaging technologies.
系統級封裝(SiP)為將由獨立的半導體晶片構成的多個電路安裝成為一個封裝的小型化技術，將兩種或多個半導體晶片排列或層疊於一個封裝中而使其作為一個完整的系統而運作的產品技術。由於系統級封裝(SiP)是將具有多種功能的個別元件內裝於一個封裝之內，因此電子產品的小型化得以實現，其為隨著電子產品的小型化及複雜化地加快進展從而一躍而起的封裝技術。 System-in-package (SiP) is a miniaturization technique in which a plurality of circuits composed of independent semiconductor wafers are mounted into one package, and two or more semiconductor wafers are arranged or stacked in one package to make them a complete system. Working product technology. Since system-in-package (SiP) is a component in which a plurality of functions are housed in one package, miniaturization of electronic products is realized, which is accompanied by an increase in the miniaturization and complication of electronic products. Packaging technology.
請參照第1圖及第2圖，第1圖為現有的凹型區朝下(Cavity Down)的系統級封裝(SiP)的縱向剖面圖，第2圖為用於說明現有的凹型區朝下的系統級封裝(SiP)而從印刷電路板的下部仰視的示意圖。 Please refer to FIG. 1 and FIG. 2 . FIG. 1 is a longitudinal sectional view of a conventional system-in-package (SiP) with a recessed area, and FIG. 2 is a view showing a conventional concave area facing downward. A schematic diagram of a system-in-package (SiP) looking up from the lower portion of the printed circuit board.
如第1圖及第2圖所示，現有的凹型區朝下的系統級封裝10包括：上 面形成多個導電圖案(conductive pattern)(未圖示)，而下面中間部分形成凹型區(cavity)11a的印刷電路板(Printed Circuit Board,PCB)11；安裝於所述印刷電路板11的所述凹型區(cavity)11a內的半導體晶片12；形成於所述印刷電路板11上面，並利用第一通孔(via)18電性連接安裝板3，利用第二通孔19電性連接所述半導體晶片12的被動元件13與晶體振盪器14等電子產品；以及為了從外部環境保護所述印刷電路板11的整個上面而罩住所述印刷電路板11的成型部(Molding Portion)15。 As shown in FIGS. 1 and 2, the conventional recessed-down system-level package 10 includes: a printed circuit board (PCB) 11 in which a plurality of conductive patterns (not shown) are formed, and a lower intermediate portion forms a concave portion 11a; and a printed circuit board 11 is mounted on the printed circuit board 11 a semiconductor wafer 12 in a recessed area 11a; formed on the printed circuit board 11 and electrically connected to the mounting board 3 by a first via 18, and electrically connected by the second through hole 19 An electronic product such as the passive element 13 of the semiconductor wafer 12 and the crystal oscillator 14 is included; and a molding portion 15 of the printed circuit board 11 is covered to protect the entire upper surface of the printed circuit board 11 from the outside.
除了所述印刷電路板11的凹型區11a的區域以外，所述印刷電路板11利用第一焊球16而安裝於安裝板3上面。所述第一焊球16連接於安裝板3的導電圖案3a。 The printed circuit board 11 is mounted on the mounting board 3 by the first solder balls 16 except for the area of the concave portion 11a of the printed circuit board 11. The first solder ball 16 is connected to the conductive pattern 3a of the mounting board 3.
所述半導體晶片12在其上面形成活性面12a，在其下面形成惰性面12b。所述半導體晶片12的惰性面12b設置成朝向安裝板(board)3的上面，並且可以利用所述第二焊球17而以電性連接所述印刷電路板11。 The semiconductor wafer 12 has an active surface 12a formed thereon, and an inert surface 12b is formed under the semiconductor wafer 12. The inert surface 12b of the semiconductor wafer 12 is disposed to face the upper surface of the mounting board 3, and the second solder ball 17 can be utilized to electrically connect the printed circuit board 11.
現有的凹型區朝下的系統級封裝10中，半導體晶片12安裝於凹型區11a內，並且利用所述第二焊球17而連接於所述印刷電路板11，因此第二焊球17完全不會外露。 In the conventional recessed-down system-in-package 10, the semiconductor wafer 12 is mounted in the recessed portion 11a, and is connected to the printed circuit board 11 by the second solder ball 17, so that the second solder ball 17 is completely absent. Will be exposed.
系統級封裝為將多個電路安裝為一個封裝的小型化技術，因此為了將多個半導體晶片12，即多個電子元件皆安裝於印刷電路板11的表面，需要對多個導電圖案及連接結構進行最優化的設計。 The system-in-package is a miniaturization technique in which a plurality of circuits are mounted as one package. Therefore, in order to mount a plurality of semiconductor wafers 12, that is, a plurality of electronic components, on the surface of the printed circuit board 11, a plurality of conductive patterns and connection structures are required. Optimize the design.
但是，習知技術的凹型區朝下的系統級封裝為面朝下(face down)的形態，半導體晶片12是利用第二焊球17而安裝於印刷電路板11上，由於第二焊球17具有不外露的結構而無法將第二焊球17作為輸入/輸出引線而使 用，因此對超小型及高性能封裝的設計帶來很大的限制與困難。 However, the recessed area-down system-level package of the prior art is in a face down form, and the semiconductor wafer 12 is mounted on the printed circuit board 11 by the second solder ball 17, due to the second solder ball 17 Has a non-exposed structure and cannot use the second solder ball 17 as an input/output lead It is used, so it brings great limitations and difficulties to the design of ultra-small and high-performance packages.
為了解決上述問題，本發明的目的在於提供一種半導體封裝及其半導體封裝製造方法，半導體晶片的活性面利用第二焊球而變更為連接於安裝板的面朝上(face up)形態，從而無需實際增加焊球而提高了外露的焊球的數量，擴大了實質性的輸入/輸出引線，由此可迅速處理輸出入信號，大幅提高性能的半導體封裝及其半導體封裝製造方法。 In order to solve the above problems, an object of the present invention is to provide a semiconductor package and a semiconductor package manufacturing method thereof, in which an active surface of a semiconductor wafer is changed to a face up form connected to a mounting board by a second solder ball, thereby eliminating The actual increase in solder balls increases the number of exposed solder balls and expands the substantial input/output leads, thereby rapidly processing the input and output signals, greatly improving the performance of the semiconductor package and its semiconductor package manufacturing method.
為了達到所述目的，根據本發明的半導體封裝如下：封裝基板安裝於上面形成導電圖案的安裝板上，半導體封裝的所述封裝基板上安裝有半導體晶片，其中，所述安裝板的上面形成導電圖案，所述封裝基板的下面中心部分形成凹型區(cavity)，在所述凹型區以外的封裝基板下面形成用於以電性連接所述安裝板的第一焊球，所述半導體晶片配置於所述凹型區之內，所述半導體晶片的惰性面粘貼於所述封裝基板的惰性面，所述半導體晶片的活性面利用第二焊球而以電性連接於所述安裝板。 In order to achieve the object, a semiconductor package according to the present invention is as follows: a package substrate is mounted on a mounting board on which a conductive pattern is formed, and a semiconductor wafer is mounted on the package substrate of the semiconductor package, wherein an upper surface of the mounting board forms a conductive a pattern, a lower central portion of the package substrate forms a concave cavity, and a first solder ball for electrically connecting the mounting board is formed under the package substrate outside the concave portion, the semiconductor wafer is disposed on The inert surface of the semiconductor wafer is adhered to the inert surface of the package substrate, and the active surface of the semiconductor wafer is electrically connected to the mounting board by a second solder ball.
所述半導體晶片的所述活性面利用所述第二焊球而形成為安裝於所述安裝板的面朝上(face up)的形態，從而擴大了輸入/輸出引線的數量。 The active surface of the semiconductor wafer is formed into a face up shape mounted on the mounting board by the second solder ball, thereby enlarging the number of input/output leads.
所述封裝基板上形成用於連接所述第一焊球的多個通孔，所述封裝基板的上面安裝以電性連接於所述安裝板的電子元件，所述電子元件包括被動元件或晶體振盪器。 Forming a plurality of through holes for connecting the first solder balls on the package substrate, the upper surface of the package substrate being mounted to electrically connect to the electronic components of the mounting board, the electronic components including passive components or crystals Oscillator.
所述印刷電路板上形成罩住所述印刷電路板的成型部。 A molded portion covering the printed circuit board is formed on the printed circuit board.
所述第一焊球及所述第二焊球在同一個平面上以相同的高度連接於所述安裝板的導電圖案。 The first solder ball and the second solder ball are connected to the conductive pattern of the mounting board at the same height on the same plane.
另一方面，根據本發明的半導體封裝製造方法，用以在安裝板的上面安裝封裝基板並且在所述封裝基板安裝半導體晶片，在所述封裝基板的下面中心部分形成凹型區(cavity)，在所述凹型區以外的封裝基板下面形成用於以電性連接所述安裝板的第一焊球，將所述半導體晶片的惰性面粘貼於所述封裝基板的惰性面(凹型區的上面)，利用第二焊球而將所述半導體晶片的活性面與所述安裝板以電性進行連接，以擴大實質性的輸入/輸出引線的數量。 In another aspect, a semiconductor package manufacturing method according to the present invention is for mounting a package substrate on a mounting board and mounting a semiconductor wafer on the package substrate, and forming a concave portion at a lower central portion of the package substrate, Forming a first solder ball for electrically connecting the mounting board to the underside of the package substrate, and attaching an inert surface of the semiconductor wafer to an inert surface of the package substrate (on the upper surface of the concave region), The active surface of the semiconductor wafer is electrically connected to the mounting board using a second solder ball to expand the number of substantial input/output leads.
如上所述，本發明在封裝基板的下面所形成的凹型區內配置有半導體晶片，半導體晶片的活性面利用第二焊球而變更為安裝於安裝板的面朝上(face up)形態，從而無需實際增加焊球而能提高外露的焊球的數量，由此擴大了實質性的輸入/輸出引線而能夠處理超高速的輸出入信號處理，並可以實現最小型化、最輕量化。 As described above, in the present invention, a semiconductor wafer is disposed in a concave region formed on the lower surface of the package substrate, and the active surface of the semiconductor wafer is changed to a face up form mounted on the mounting board by the second solder ball, thereby The number of exposed solder balls can be increased without actually increasing the solder balls, thereby expanding the substantial input/output leads and handling ultra-high-speed input/output signal processing, and minimizing and miniaturizing.
以下，參照附圖，對根據本發明的較佳實施例中半導體封裝及其半導體封裝製造方法進行詳細的說明。 Hereinafter, a semiconductor package and a method of manufacturing the same according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
參考第3圖、第4圖以及第5圖，第3圖為根據本發明的較佳實施例中半導體封裝的縱向剖面圖；第4圖為根據本發明的較佳實施例中半導體封裝，其為從印刷電路板下部的仰視示意圖；以及第5圖為根據本發明的較佳實施例中半導體封裝與習知技術的半導體封裝作比較的縱向剖面圖。 Referring to Figures 3, 4 and 5, Figure 3 is a longitudinal cross-sectional view of a semiconductor package in accordance with a preferred embodiment of the present invention; and Figure 4 is a semiconductor package in accordance with a preferred embodiment of the present invention. A bottom view of the lower portion of the printed circuit board; and FIG. 5 is a longitudinal cross-sectional view of the semiconductor package in accordance with a preferred embodiment of the present invention as compared to a conventional semiconductor package.
如第3圖及第4圖所示，根據本發明的實施例中半導體封裝100，可以是將相同結構或異質結構的晶片疊層，也可以是將邏輯晶片置於中間並在邏輯晶片的兩面分別具有已安裝記憶體晶片的結構，皆可以實現本發明的 系統級封裝。 As shown in FIG. 3 and FIG. 4, the semiconductor package 100 according to the embodiment of the present invention may be a wafer stack of the same structure or a heterostructure, or may be placed in the middle of the logic wafer and on both sides of the logic wafer. The structure having the memory chip mounted thereon can realize the present invention. System level package.
基本上，習知技術的封裝製造方法需要依據導體晶片的類別而分別執行封裝工程，當考慮到由晶圓所得到的半導體晶片的數量時，對所有半導體晶片進行封裝需要較長時間，最近被提出一種方法，即在晶圓(Wafer)狀態下優先進行封裝工程，之後再沿著晶圓的切割線(scribe line)進行切割，最後再製作各個封裝。 Basically, the packaging manufacturing method of the prior art requires separate packaging engineering according to the type of the conductor wafer. When considering the number of semiconductor wafers obtained by the wafer, it takes a long time to package all the semiconductor wafers, and recently A method is proposed in which a package process is prioritized in a wafer state, followed by dicing along a scribe line of the wafer, and finally each package is fabricated.
利用如上所述的方法而製作出來的封裝稱為晶圓片級封裝(Wafer Level Package)，而且以晶圓片級製作封裝的情況下，由於封裝整體的大小與晶片的大小相近，因此稱為晶圓片級晶片規模封裝(Wafer Level Chip Size Package,WLCSP)。 The package fabricated by the method described above is called a wafer level package, and when the package is fabricated at the wafer level, since the size of the package as a whole is similar to the size of the wafer, it is called Wafer Level Chip Size Package (WLCSP).
本發明的較佳實施例中所述的半導體晶片120例如是邏輯晶片或記憶體晶片，並且這樣的半導體晶片120可以是上述所述的晶圓片級晶片規模封裝(WLCSP)形態的晶片或者是凸起的晶粒(die)形態的晶片。但是，本發明並不限於此，也可以是晶片單位、晶圓單位或封裝單位的半導體元件。 The semiconductor wafer 120 described in the preferred embodiment of the present invention is, for example, a logic wafer or a memory wafer, and such a semiconductor wafer 120 may be a wafer in the form of a wafer level wafer scale package (WLCSP) as described above or A raised die in the form of a wafer. However, the present invention is not limited thereto, and may be a semiconductor element of a wafer unit, a wafer unit, or a package unit.
根據本發明的較佳實施例中半導體封裝100，在其上面具備形成導電圖案110a的封裝基板110。 According to a preferred embodiment of the present invention, the semiconductor package 100 is provided with a package substrate 110 on which a conductive pattern 110a is formed.
所述封裝基板110的下面中心部分形成四型區(cavity)111，在所述凹型區111以外的封裝基板110下面形成用於以電性連接所述安裝板3的第一焊球112，亦即所述第一焊球112設置於所述凹型區111週邊的封裝基板110下面。 The lower central portion of the package substrate 110 forms a four-type cavity 111, and a first solder ball 112 for electrically connecting the mounting board 3 is formed under the package substrate 110 outside the recessed area 111. That is, the first solder ball 112 is disposed under the package substrate 110 around the concave region 111.
在一實施例中，所述封裝基板110的凹型區111可以利用從顯微機械加工(micro-machining)到微型機電系統(Micro Electro Mechanical System, MEMS)等技術進行微細的加工，以於封裝基板110的中心部去除了一部分的惰性區域，以形成任意尺寸大小之區域。 In an embodiment, the concave region 111 of the package substrate 110 can utilize micro-machining to a micro electro mechanical system (Micro Electro Mechanical System, Techniques such as MEMS) are finely processed to remove a portion of the inert region at the center of the package substrate 110 to form an area of any size.
根據本發明的較佳實施例中半導體封裝100具有配置於所述凹型區111之內的所述半導體晶片120。 The semiconductor package 100 has a semiconductor wafer 120 disposed within the recessed region 111 in accordance with a preferred embodiment of the present invention.
所述半導體晶片120的惰性面120b粘貼於所述封裝基板110的惰性面(凹型區的上面)111a，所述半導體晶片120的活性面120a利用第二焊球121以電性連接所述安裝板3。 The inert surface 120b of the semiconductor wafer 120 is adhered to the inert surface (the upper surface of the concave region) 111a of the package substrate 110, and the active surface 120a of the semiconductor wafer 120 is electrically connected to the mounting board by the second solder ball 121. 3.
亦即，所述半導體晶片120為惰性面120b朝向封裝基板110，而其活性面120a朝向安裝板3的面朝上(face up)結構，並且被安裝於安裝板3的上面。這時，半導體晶片120的活性面120a利用第二焊球121而連接於安裝板3，從而以電性連接於所述安裝板3。 That is, the semiconductor wafer 120 has the inert surface 120b facing the package substrate 110, and its active surface 120a faces the face up structure of the mounting board 3, and is mounted on the upper surface of the mounting board 3. At this time, the active surface 120a of the semiconductor wafer 120 is connected to the mounting board 3 by the second solder balls 121, thereby being electrically connected to the mounting board 3.
其中，上述的活性面120a是指形成於半導體晶片120內的電路圖案(電路佈線)中至少一部分被外露並且能夠實現資料的輸入與輸出的介面。上述的惰性面120b是指電路圖案並未外露且不能實現實際的資料的輸入與輸出的介面。 The active surface 120a described above refers to an interface in which at least a part of a circuit pattern (circuit wiring) formed in the semiconductor wafer 120 is exposed and data can be input and output. The above-mentioned inert surface 120b refers to an interface in which the circuit pattern is not exposed and the actual data input and output cannot be realized.
所述半導體晶片120的惰性面120b黏貼於封裝基板110的惰性面(凹型區的上面)111a，這時黏貼部件160可以使用環氧(epoxy)、聚醯亞胺(polyimide)或兩面膠其中任意一種。 The inert surface 120b of the semiconductor wafer 120 is adhered to the inert surface (the upper surface of the concave portion) 111a of the package substrate 110. At this time, the adhesive member 160 may use any one of epoxy, polyimide or double-sided adhesive. .
所述第一焊球112及所述第二焊球121在同一平面上以相同的高度連接所述安裝板3的導電圖案3a。 The first solder ball 112 and the second solder ball 121 are connected to the conductive pattern 3a of the mounting board 3 at the same height on the same plane.
而且，所述封裝基板110上形成至少一個用於連接所述第一焊球112的通孔113，所述封裝基板110的上面安裝有用於以電性連接於所述安裝板 3的被動元件130及晶體振盪器140。所述被動元件130及晶體振盪器140僅為電子元件中的一個舉例，可以根據需要而替換為其他電子元件。 Moreover, at least one through hole 113 for connecting the first solder ball 112 is formed on the package substrate 110, and the upper surface of the package substrate 110 is mounted for electrically connecting to the mounting board. Passive component 130 and crystal oscillator 140 of 3. The passive component 130 and the crystal oscillator 140 are only one of the electronic components, and may be replaced with other electronic components as needed.
所述半導體晶片120的導電圖案利用通孔113而以電性連接安裝於封裝基板110的上部的被動元件130及晶體振盪器140，所述第二焊球121中的一部分具備與被動元件130及晶體振盪器140以電性進行連接的功能，其餘部份的第二焊球121具備可作為將資料進行輸入與輸出的輸入/輸出引線的功能。 The conductive pattern of the semiconductor wafer 120 is electrically connected to the passive component 130 and the crystal oscillator 140 mounted on the upper portion of the package substrate 110 by using the via 113, and a part of the second solder ball 121 is provided with the passive component 130 and The crystal oscillator 140 has a function of electrically connecting, and the remaining portion of the second solder ball 121 has a function as an input/output lead for inputting and outputting data.
並且，該封裝基板110係為印刷電路板，並且所述印刷電路板110上形成用於罩住所述印刷電路板110的上部的成型部150。所述成型部150為作為絕緣體的樹脂而成，屬於周知的常用技術，因此予以省略。 Further, the package substrate 110 is a printed circuit board, and a molding portion 150 for covering an upper portion of the printed circuit board 110 is formed on the printed circuit board 110. The molded portion 150 is made of a resin as an insulator, and is a well-known conventional technique, and thus will be omitted.
第4圖為根據本發明的較佳實施例中半導體封裝100，其為從印刷電路板110下部的仰視示意圖，與第2圖的習知技術半導體封裝相比，第4圖的安裝板3的中間部分也配置有第二焊球121而由此可以確認外露的全部焊球數量有所增加。即，相比習知技術的凹型區朝下的系統級封裝10，雖然全部焊球的數量並沒有增加，但能夠作為輸入與輸出的輸入/輸出引線而運作的實質焊球的數量將會有所增加。 4 is a bottom view of a semiconductor package 100 in accordance with a preferred embodiment of the present invention, which is a bottom view of the lower portion of the printed circuit board 110, compared to the prior art semiconductor package of FIG. The middle portion is also provided with the second solder ball 121, whereby it can be confirmed that the number of all exposed solder balls is increased. That is, although the number of all solder balls does not increase compared to the recessed area down system type package 10 of the prior art, the number of substantial solder balls that can operate as input/output leads of the input and output will have Increased.
因此，根據本發明的較佳的實施例中半導體封裝100為面朝上(face up)形態，並且所述半導體晶片120的所述活性面120a利用所述第二焊球121而連接到所述安裝板3，從而可以實現輸入/輸出引線的數量的實質性增加。 Therefore, in a preferred embodiment of the present invention, the semiconductor package 100 is in a face up configuration, and the active surface 120a of the semiconductor wafer 120 is connected to the second solder ball 121. The board 3 is mounted so that a substantial increase in the number of input/output leads can be achieved.
另一方面，第5圖為根據本發明的較佳實施例中半導體封裝與習知技術的半導體封裝作比較的縱向剖面圖，第5圖的(a)圖為用於說明習知技術的半導體封裝的信號路徑的示意剖面圖，第5圖的(b)圖為用於說明根據本 發明的較佳實施例中半導體封裝的信號路徑的示意剖面圖。 5 is a longitudinal cross-sectional view of a semiconductor package in comparison with a conventional semiconductor package in accordance with a preferred embodiment of the present invention, and FIG. 5(a) is a view showing a semiconductor of the prior art. A schematic cross-sectional view of the signal path of the package, and (b) of FIG. 5 is for explaining A schematic cross-sectional view of a signal path of a semiconductor package in a preferred embodiment of the invention.
如第5圖的(a)圖所示，習知技術的半導體封裝結構的外部信號路徑中，由於信號路徑(請參照箭頭所示)是由半導體晶片12、第二焊球17、第二通孔19、第一通孔18、第一焊球16及導電圖案3a構成。因此實際上第二焊球17無法具備輸入/輸出引線的功能，因此輸入/輸出引線的數量只能被限制為第一焊球16。 As shown in FIG. 5(a), in the external signal path of the conventional semiconductor package structure, the signal path (shown by the arrow) is composed of the semiconductor wafer 12, the second solder ball 17, and the second pass. The hole 19, the first through hole 18, the first solder ball 16 and the conductive pattern 3a are formed. Therefore, the second solder ball 17 cannot actually have the function of the input/output lead, and therefore the number of input/output leads can only be limited to the first solder ball 16.
相反地，如第5圖的(b)圖所示，根據本發明的較佳實施例中半導體封裝，其信號路徑(請參照箭頭)包括：由半導體晶片120、第二焊球121、導電圖案3a構成的第一路徑；以及由被動組件130及晶體振盪器140、通孔113、第一焊球112、及導電圖案3a構成的第二路徑。 In contrast, as shown in FIG. 5(b), in the semiconductor package according to the preferred embodiment of the present invention, the signal path (please refer to the arrow) includes: the semiconductor wafer 120, the second solder ball 121, and the conductive pattern. A first path formed by 3a; and a second path formed by the passive component 130 and the crystal oscillator 140, the via 113, the first solder ball 112, and the conductive pattern 3a.
而且，根據本發明的較佳的實施例中半導體封裝的內部信號路徑，半導體晶片120利用第二焊球121、導電圖案3a、第一焊球112及通孔113而以電性連接被動元件130與晶體振盪器140。 Moreover, in accordance with the internal signal path of the semiconductor package in the preferred embodiment of the present invention, the semiconductor wafer 120 is electrically connected to the passive component 130 by using the second solder ball 121, the conductive pattern 3a, the first solder ball 112, and the via 113. With crystal oscillator 140.
如上所述，本發明的半導體封裝中，隨著外部信號路徑的多元化，實際上不僅是第一焊球112，還有第二焊球121也能作為輸入/輸出引線之用。因此相比習知技術的半導體封裝，無需實際增加焊球就能提高作為輸入/輸出引線而運作的焊球的數量，有效增加輸入/輸出引線，從而能夠迅速處理輸出入信號，能大幅提高性能。 As described above, in the semiconductor package of the present invention, as the external signal path is diversified, not only the first solder ball 112 but also the second solder ball 121 can be used as the input/output lead. Therefore, compared with the conventional semiconductor package, the number of solder balls operating as input/output leads can be increased without actually increasing the solder balls, and the input/output leads can be effectively increased, so that the input and output signals can be processed quickly, and the performance can be greatly improved. .
另一方面，根據本發明的較佳的實施例的半導體封裝製造方法，在所述凹型區(cavity)111以外的封裝基板110下面形成用於以電性連接所述安裝板3的第一焊球112，將所述半導體晶片120的惰性面120b粘貼於所述封裝基板110的下面，利用第二焊球121而將所述半導體晶片120的活性面 120a以電性連接於所述安裝板3，從而擴大輸入/輸出引線的數量。 On the other hand, according to the semiconductor package manufacturing method of the preferred embodiment of the present invention, a first solder for electrically connecting the mounting board 3 is formed under the package substrate 110 other than the cavity 111. The ball 112 is attached to the underside of the package substrate 110 by the inert surface 120b of the semiconductor wafer 120, and the active surface of the semiconductor wafer 120 is formed by the second solder ball 121. 120a is electrically connected to the mounting board 3, thereby expanding the number of input/output leads.
如上所述，本發明在封裝基板的下面所形成的凹型區內配置有半導體晶片，半導體晶片的活性面利用第二焊球而變更為安裝於安裝板的面朝上(face up)形態，從而無需實際增加焊球而能增加外露的焊球的數量，由此擴大了實質性的輸入/輸出引線，故能夠處理超高速的輸出入信號處理，還可以實現最小型化、最輕量化。 As described above, in the present invention, a semiconductor wafer is disposed in a concave region formed on the lower surface of the package substrate, and the active surface of the semiconductor wafer is changed to a face up form mounted on the mounting board by the second solder ball, thereby The actual number of exposed solder balls can be increased without actually adding solder balls, thereby expanding the substantial input/output leads, so that ultra-high-speed input/output signal processing can be handled, and the minimum and the minimum weight can be realized.
雖然本發明已用較佳實施例揭露如上，然其並非用以限定本發明，本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the invention has been described above in terms of the preferred embodiments, the invention is not intended to limit the invention, and the invention may be practiced without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.
3‧‧‧安裝板 3‧‧‧Installation board
3a‧‧‧導電圖案 3a‧‧‧ conductive pattern
10‧‧‧系統級封裝 10‧‧‧System-in-Package
11‧‧‧印刷電路板 11‧‧‧Printed circuit board
11a‧‧‧凹型區 11a‧‧‧ concave area
12‧‧‧半導體晶片 12‧‧‧Semiconductor wafer
12a‧‧‧活性面 12a‧‧‧active surface
12b‧‧‧惰性面 12b‧‧‧Inert surface
13‧‧‧被動元件 13‧‧‧ Passive components
14‧‧‧晶體振盪器 14‧‧‧ crystal oscillator
15‧‧‧成型部 15‧‧‧Forming Department
16‧‧‧第一焊球 16‧‧‧First solder ball
17‧‧‧第二焊球 17‧‧‧Second solder ball
18‧‧‧第一通孔 18‧‧‧First through hole
19‧‧‧第二通孔 19‧‧‧Second through hole
100‧‧‧半導體封裝 100‧‧‧Semiconductor package
110‧‧‧封裝基板 110‧‧‧Package substrate
110a‧‧‧導電圖案 110a‧‧‧ conductive pattern
111‧‧‧凹型區 111‧‧‧ concave area
111a‧‧‧封裝基板的惰性面 111a‧‧‧Inert surface of package substrate
112‧‧‧第一焊球 112‧‧‧First solder ball
113‧‧‧通孔 113‧‧‧through hole
120‧‧‧半導體晶片 120‧‧‧Semiconductor wafer
120a‧‧‧活性面 120a‧‧‧active surface
120b‧‧‧惰性面 120b‧‧‧Inert surface
121‧‧‧第二焊球 121‧‧‧Second solder ball
130‧‧‧被動元件 130‧‧‧ Passive components
140‧‧‧晶體振盪器 140‧‧‧ crystal oscillator
150‧‧‧成型部 150‧‧‧Forming Department
160‧‧‧黏貼部件 160‧‧‧Adhesive parts
第1圖為習知技術的凹型區朝下的系統級封裝的縱向剖面圖；第2圖為習知技術的凹型區朝下的系統級封裝，其為從印刷電路板下部的仰視示意圖；第3圖為根據本發明的較佳實施例中半導體封裝的縱向剖面圖；第4圖為根據本發明的較佳實施例中半導體封裝，其為從印刷電路板下部的仰視示意圖；以及第5圖為根據本發明的較佳實施例中半導體封裝與習知技術的半導體封裝作比較的縱向剖面圖。 1 is a longitudinal cross-sectional view of a system-in-package with a recessed area facing down in the prior art; and FIG. 2 is a bottom-down system-in-package of a recessed area of the prior art, which is a bottom view from the lower portion of the printed circuit board; 3 is a longitudinal cross-sectional view of a semiconductor package in accordance with a preferred embodiment of the present invention; and FIG. 4 is a bottom view of the lower portion of the printed circuit board in accordance with a preferred embodiment of the present invention; and FIG. A longitudinal cross-sectional view of a semiconductor package in accordance with a preferred embodiment of the present invention as compared to a conventional semiconductor package.
3‧‧‧安裝板 3‧‧‧Installation board
3a‧‧‧導電圖案 3a‧‧‧ conductive pattern
100‧‧‧半導體封裝 100‧‧‧Semiconductor package
110‧‧‧封裝基板 110‧‧‧Package substrate
110a‧‧‧導電圖案 110a‧‧‧ conductive pattern
111‧‧‧凹型區 111‧‧‧ concave area
111a‧‧‧封裝基板的惰性面 111a‧‧‧Inert surface of package substrate
112‧‧‧第一焊球 112‧‧‧First solder ball
113‧‧‧通孔 113‧‧‧through hole
120‧‧‧半導體晶片 120‧‧‧Semiconductor wafer
120a‧‧‧活性面 120a‧‧‧active surface
120b‧‧‧惰性面 120b‧‧‧Inert surface
121‧‧‧第二焊球 121‧‧‧Second solder ball
130‧‧‧被動元件 130‧‧‧ Passive components
140‧‧‧晶體振盪器 140‧‧‧ crystal oscillator
150‧‧‧成型部 150‧‧‧Forming Department
160‧‧‧粘貼部件 160‧‧‧Paste parts
Claims (9)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020110065246A KR101222474B1 (en) | 2011-07-01 | 2011-07-01 | Semiconductor package and manufacturing method thereof |
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| Publication Number | Publication Date |
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| TW201304096A TW201304096A (en) | 2013-01-16 |
| TWI591779B true TWI591779B (en) | 2017-07-11 |
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| KR (1) | KR101222474B1 (en) |
| CN (1) | CN102856264B (en) |
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| JP3372169B2 (en) * | 1996-06-07 | 2003-01-27 | 株式会社東芝 | Semiconductor package |
| KR100549312B1 (en) | 2000-10-10 | 2006-02-02 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
| TWI278947B (en) | 2004-01-13 | 2007-04-11 | Samsung Electronics Co Ltd | A multi-chip package, a semiconductor device used therein and manufacturing method thereof |
| US7897503B2 (en) * | 2005-05-12 | 2011-03-01 | The Board Of Trustees Of The University Of Arkansas | Infinitely stackable interconnect device and method |
| JP2007150181A (en) | 2005-11-30 | 2007-06-14 | Matsushita Electric Ind Co Ltd | Laminated packaged structure |
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| TWI416700B (en) * | 2009-12-29 | 2013-11-21 | Chipmos Technologies Inc | Chip-stacked package structure and method for manufacturing the same |
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| CN102856264A (en) | 2013-01-02 |
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