CN101783335A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- CN101783335A CN101783335A CN 200910159615 CN200910159615A CN101783335A CN 101783335 A CN101783335 A CN 101783335A CN 200910159615 CN200910159615 CN 200910159615 CN 200910159615 A CN200910159615 A CN 200910159615A CN 101783335 A CN101783335 A CN 101783335A
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- face
- wiring
- bight
- semiconductor chip
- surface electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention can obtain a semiconductor device that can be easily produced and can reduce the chip area. The semiconductor chip has a top surface, a bottom surface and a lateral surface connecting the top surface and the bottom surface. Bottom surface electrodes are formed on the bottom surface of the semiconductor chip. Lateral surface wiring is formed on the lateral surface of the corner of the semiconductor chip. The lateral surface wiring is connected to the electronic circuit and the bottom surface electrodes.
Description
Technical field
The present invention relates to form the semiconductor device of side wiring, relate in particular to the semiconductor device that to make and to dwindle chip area easily in the side of semiconductor chip.
Background technology
Install in the semiconductor device of semiconductor chip in the equipped section, for the electronic circuit and the electrode of equipped section that connects semiconductor chip, and employing wire-bonded (wirebonding), flip-chip (flip chip), side wiring etc.Be located at the through hole on the line of cut of semiconductor wafer by cut-out, the side wiring is formed on the side of semiconductor chip (for example, with reference to patent documentation 1: Japanese kokai publication hei 6-120294 communique).
All the time, on the limit of semiconductor chip, form the side wiring.Thereby, form the side wiring of 2 semiconductor chips by 1 through hole.Therefore, must form many through holes, because the strength reduction of wafer is difficult to make at semiconductor wafer.In addition, there is the problem of chip area increase in the area of side wiring greatly to the amount of 1/2 through hole.
In addition, in the end face formation end face wiring of semiconductor chip, to connect the wiring of electronic circuit and side.In the past, the end face periphery length that is routed in end face was roughly identical with the side wiring.Thereby in case the position change of side wiring, the side wiring just can not be connected with the end face wiring, has therefore reduced the position freedom of side wiring.
Summary of the invention
The present invention forms in order to solve above-mentioned problem design, and its first purpose is the semiconductor device that obtains making easily and dwindling chip area.Second purpose is the semiconductor device that obtains improving the position freedom that connects up the side.
The semiconductor device of first invention is characterized in that possessing: the side that semiconductor chip, this semiconductor chip have end face and bottom surface and be connected described end face and described bottom surface; Electronic circuit is formed on described end face; Bottom-side electrodes is formed on described bottom surface; And the side wiring, in the bight of described semiconductor chip, be formed on described side, connect described electronic circuit and described bottom-side electrodes.
The semiconductor device of second invention is characterized in that possessing: the side that semiconductor chip, this semiconductor chip have end face and bottom surface and be connected described end face and described bottom surface; End face wiring at described end face, forms along the periphery of described end face; Electronic circuit is formed on described end face, is connected with described end face wiring; Bottom-side electrodes is formed on described bottom surface; And side wiring, be formed on the described side of described semiconductor chip, connect described end face wiring and described bottom-side electrodes, described end face is routed in the length of periphery of described end face more than one side of described end face.
(invention effect)
By first invention, can access the semiconductor device that to make and to dwindle chip area easily.By second invention, can improve the position freedom of side wiring.
Description of drawings
Fig. 1 is the oblique view of the semiconductor chip of expression execution mode 1.
Fig. 2 is the oblique view of the semiconductor chip of expression execution mode 1.
Fig. 3 is the cutaway view of the semiconductor device of expression execution mode 1.
Fig. 4 is illustrated in the oblique view of appearance that the semiconductor chip of execution mode 1 is carried in the equipped section.
Fig. 5 is illustrated in the oblique view of appearance that the semiconductor chip of execution mode 1 is carried in the equipped section.
Fig. 6 is the oblique view of the operation of the expression semiconductor chip of making execution mode 1.
Fig. 7 is the oblique view of the semiconductor chip of expression execution mode 2.
Fig. 8 is the oblique view of the operation of the expression semiconductor chip of making execution mode 2.
(symbol description)
10 semiconductor chips; 12a bight (first bight); 12b bight (second bight); 12c bight (third angle portion); 12d bight (the 4th bight); The wiring of 14 end faces; 14a end face wiring (wiring of first end face); 14b end face wiring (wiring of second end face); 16 electronic circuits; 16a lead-out terminal (second terminal); 18 bottom-side electrodes; 18a bottom-side electrodes (first surface electrode); 18b bottom-side electrodes (second surface electrode); The wiring of 20 sides; 20a side wiring (the first side electrode); 20b side wiring (second surface electrode); 22 equipped sections; 24a surface electrode (first surface electrode); 24b surface electrode (second surface electrode); 24c surface electrode (the 3rd surface electrode); 24d surface electrode (the 4th surface electrode); 26a surface wiring (first surface wiring); 26b surface wiring (second surface wiring); 28 inductors (impedance inverter circuit).
Embodiment
Execution mode 1
Fig. 1, Fig. 2 are the oblique views of the semiconductor chip of expression execution mode 1.Semiconductor chip 10 has end face respect to one another with the bottom surface and be connected end face and the side of bottom surface.The end face of semiconductor chip 10 be have bight 12a, with the bight 12b of bight 12a adjacency, the quadrangle that is present in the bight 12c on the diagonal of bight 12a and is present in the bight 12d on the diagonal of bight 12b.
At the end face of semiconductor chip 10, form end face wiring 14a, with connection bight 12a and bight 12b, and form end face wiring 14b, to connect bight 12c and bight 12d.End face at semiconductor chip 10 forms electronic circuit 16.Electronic circuit 16 has input terminal 16b that is connected with end face wiring 14a and the lead-out terminal 16a that is connected with end face wiring 14b.Bight in the bottom surface corresponding with the bight 12a of semiconductor chip 10 end faces forms bottom-side electrodes 18a, and forms bottom-side electrodes 18b in the bight of the bottom surface corresponding with bight 12c.
Fig. 3 is the cutaway view of the semiconductor device of expression execution mode 1.Utilize scolding tin or conductive paste (paste), 22 mounted on surface semiconductor chips 10 in the equipped section.Semiconductor chip 10 utilizes mold pressing resin 24 to encapsulate.So need not to utilize harness wiring and can carry semiconductor chip 10, therefore can be with the packaging part small sizeization.
Fig. 4, Fig. 5 are illustrated in the oblique view of appearance that the semiconductor chip of execution mode 1 is carried in the equipped section.22 surfaces in the equipped section constitute configuration surface electrode 24a～24d quadrangularly.Surface electrode 24b and surface electrode 24a adjacency.Surface electrode 24c is present on the diagonal of surface electrode 24a.Surface electrode 24d is present on the diagonal of surface electrode 24b.
22 when carrying semiconductor chips 10 in the equipped section, and as shown in Figure 4, bottom-side electrodes 18a is connected with surface electrode 24a and bottom-side electrodes 18b is connected with surface electrode 24c.Perhaps, semiconductor chip 10 is revolved turn 90 degrees, as shown in Figure 5, bottom-side electrodes 18a is connected with surface electrode 24b and bottom-side electrodes 18b is connected with surface electrode 24d.
Then, the manufacture method to the semiconductor chip of execution mode 1 describes.Fig. 6 is the oblique view of the operation of the expression semiconductor chip of making execution mode 1.On semiconductor wafer 30, form a plurality of electronic circuits 16 with rectangular ground.Then, form end face wiring 14a, 14b by each electronic circuit 16.Then, the intersection point at line of cut 32 forms through hole 34.With these through hole 34 internal metallization.Then, form bottom- side electrodes 18a, 18b in semiconductor chip 10 bottom surfaces.Then, cut off semiconductor wafer 30, each semiconductor chip 10 is separated along line of cut 32.At this moment form side wiring 20a, 20b by cutting off through hole 34.Make semiconductor chip 10 by above operation.
As the above explanation of doing, in execution mode 1, form the side wiring in the bight of semiconductor chip.Therefore, as shown in Figure 6, can form the side wiring of 4 semiconductor chips by 1 through hole.Thereby, compare with the occasion that forms the side wiring on the limit of semiconductor chip, can strengthen the intensity of wafer with the decreased number that is formed on the through hole in the wafer face to half, therefore make easily.In addition, the area of side wiring 1/4 can be reduced to from 1/2 through hole, chip area can be dwindled.
In addition, as shown in Figure 6, the position of through hole can change on each adjacent chip.Relative with it, in execution mode 1, the end face wiring forms with the ground, 2 bights that connection is adjacent to each other, and electronic circuit is connected to the side wiring via the end face wiring.Thereby for example not only through hole 34 still is in the occasion of bight 12b in the occasion of bight 12a, and through hole 34 all is connected to electronic circuit 16 via end face wiring 14a.Thereby, can adopt common surface placement at each chip, therefore compare with the occasion that changes layout at each chip, design more laborsaving.
In addition, in the past according to the characteristic of the semiconductor device of wanting to obtain, must prepare the equipped section of the surface wiring of the required impedance of formation to each semiconductor device.Relative with it, in execution mode 1, can be according to being that Fig. 4 carries semiconductor chip like that in the equipped section, still Fig. 5 carries like that, and the amplitude and the phase place of change signal.Thereby, can use identical semiconductor chip and equipped section to obtain having the semiconductor device of different qualities.
In addition, in execution mode 1,2 bights at semiconductor chip are formed the semiconductor device that connects up the side and be illustrated, but be not limited to this, can be in 1,3 or 4 bights formation side wirings of semiconductor chip.In addition, also can adopt ceramic package etc., to replace mold pressing resin.
In addition, in execution mode 1, use inductor 28 as impedance inverter circuit, but be not limited to this, can adopt resistance, capacitor, the line etc. can the transforming impedance device.
In addition, turn 90 degrees the semiconductor device that carries in the equipped section back and be illustrated, be not limited to this, make the anglec of rotation of semiconductor chip reach that 60 degree or 45 degree etc. are arbitrarily angled also can semiconductor chip is revolved.
In addition, the semiconductor device that has 2 surface electrodes that can connect for 1 bottom-side electrodes has been described, but for 1 bottom-side electrodes exist the surface electrode that can connect more than 3 also can, connect different respectively inductors or resistance etc. between this surface electrode and the surface wiring and also can.
Execution mode 2
Fig. 7 is the oblique view of the semiconductor chip of expression execution mode 2.Semiconductor chip 10 has end face respect to one another with the bottom surface and be connected end face and the side of bottom surface.The end face of semiconductor chip 10 is a quadrangle.
At the end face of semiconductor chip 10, form end face wiring 14 along the periphery of end face.End face at semiconductor chip 10 forms electronic circuit 16.Electronic circuit 16 has and end face wiring 14 input terminal 16b that are connected and the lead-out terminal 16a that is connected with wire pad 36.Bottom surface at semiconductor chip 10 forms bottom-side electrodes 18.
Then, the manufacture method to the semiconductor chip of execution mode 2 describes.Fig. 8 is the oblique view of the operation of the expression semiconductor chip of making execution mode 2.On semiconductor wafer 30, form a plurality of electronic circuits 16 with rectangular.Then, form end face wiring 14 by each electronic circuit 16.Then, on line of cut 32, form through hole 34.Internal metallization with this through hole 34.Then, form bottom-side electrodes 18 in the bottom surface of semiconductor chip 10.Then, cut off semiconductor wafer 30, each semiconductor chip 10 is separated along line of cut 32.At this moment form side wiring 20 by cutting off through hole 34.Produce semiconductor chip 10 by above operation.
As the above explanation of doing, in execution mode 2,4 limits of semiconductor chip 10 end faces are all formed with 4 bights with being connected.Therefore, as shown in Figure 8, regardless of which position that side wiring 20 is formed on semiconductor chip 10 peripheries, side wiring 20 all is electrically connected with end face wiring 14.Thereby, can improve the position freedom of side wiring 20.
In addition, as mentioned above, even do not form end face wiring 14, as long as end face wiring 14 is more than the one side at end face of the length on the periphery of end face in the whole periphery of semiconductor chip 10.Thereby, can form side wiring 20 on the limit of the semiconductor chip 10 that forms end face wiring 14 or the optional position in bight, therefore can improve the position freedom of side wiring 20.
Claims (5)
1. semiconductor device is characterized in that possessing:
The semiconductor chip that has end face and bottom surface and be connected the side of described end face and described bottom surface;
Be formed on the electronic circuit of described end face;
Be formed on the bottom-side electrodes of described bottom surface; And
Connecting up in the side, is formed on the described side in the bight of described semiconductor chip, connects described electronic circuit and described bottom-side electrodes.
2. semiconductor device as claimed in claim 1 is characterized in that:
Also possess the end face wiring of 2 bights ground formation that is adjacent to each other that in described end face, connects described end face,
Described electronic circuit is connected to the wiring of described side via described end face wiring.
3. semiconductor device as claimed in claim 2 is characterized in that:
Described end face be have first bight, with second bight of the described first bight adjacency, the quadrangle that is present in the third angle portion on the diagonal in described first bight and is present in the 4th bight on the diagonal in described second bight,
Described end face wiring has second end face wiring of connecting up with first end face of described second bight ground formation and be connected the formation of described third angle portion and described the 4th bight ground in described first bight of connection,
Described electronic circuit has the first terminal that is connected with described first end face wiring and second terminal that is connected with described second end face wiring,
Described bottom-side electrodes has first bottom-side electrodes in the bight that is formed on the described bottom surface corresponding with described first bight and is formed on second bottom-side electrodes with the bight of described third angle portion corresponding described bottom surface,
The wiring of described side has wiring of first side and the wiring of second side, wherein, the wiring of described first side is formed on the described side in described first bight of described semiconductor chip, connect described first end face wiring and described first bottom-side electrodes, the wiring of described second side is formed on the described side of the described third angle portion of described semiconductor chip, connects described second end face wiring and described second bottom-side electrodes.
4. semiconductor device as claimed in claim 3 is characterized in that also possessing:
The equipped section is installed described semiconductor chip from the teeth outwards;
First to fourth surface electrode, the surface configuration in described equipped section becomes the formation quadrangle;
The first surface wiring is connected with described first surface electrode and described second surface electrode;
Impedance inverter circuit is connected between described second surface electrode and the described surface wiring, and transforming impedance; And
The second surface wiring is connected with described the 3rd surface electrode and described the 4th surface electrode,
Described second surface electrode and described first surface electrode adjacency,
Described the 3rd surface electrode is present on the diagonal of described first surface electrode,
Described the 4th surface electrode is present on the diagonal of described second surface electrode,
Described first bottom-side electrodes is connected with described first surface electrode and described second bottom-side electrodes is connected with described the 3rd surface electrode, perhaps, described first bottom-side electrodes is connected with described second surface electrode and described second bottom-side electrodes is connected with described the 4th surface electrode.
5. semiconductor device is characterized in that possessing:
The semiconductor chip that has end face and bottom surface and be connected the side of described end face and described bottom surface;
The end face wiring that in described end face, forms along the periphery of described end face;
The electronic circuit that is formed on described end face and is connected with described end face wiring;
Be formed on the bottom-side electrodes of described bottom surface; And
Be formed on the described side of described semiconductor chip and connect described end face wiring and connect up with the side of described bottom-side electrodes,
Described end face is routed in length on the periphery of described end face more than one side of described end face.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009-008970 | 2009-01-19 | ||
| JP2009008970A JP5218087B2 (en) | 2009-01-19 | 2009-01-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101783335A true CN101783335A (en) | 2010-07-21 |
| CN101783335B CN101783335B (en) | 2012-04-11 |
Family
ID=42523246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910159615 Active CN101783335B (en) | 2009-01-19 | 2009-07-17 | Semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP5218087B2 (en) |
| CN (1) | CN101783335B (en) |
| TW (1) | TWI430413B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9953844B2 (en) * | 2014-06-09 | 2018-04-24 | Mitsubishi Electric Corporation | Manufacturing method of semiconductor package |
| JP7194518B2 (en) * | 2018-05-31 | 2022-12-22 | 浜松ホトニクス株式会社 | Electronic component, method for manufacturing electronic component, electronic device |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3147666B2 (en) * | 1994-07-21 | 2001-03-19 | 株式会社村田製作所 | Multilayer electronic component and method of manufacturing the same |
| JPH10284935A (en) * | 1997-04-09 | 1998-10-23 | Murata Mfg Co Ltd | Voltage-controlled oscillator and its production |
| CN1204227A (en) * | 1997-05-12 | 1999-01-06 | 阿尔卑斯电气株式会社 | Printed circuit board |
| JPH11204519A (en) * | 1998-01-08 | 1999-07-30 | Matsushita Electron Corp | Semiconductor device and its manufacture |
| JP2001332579A (en) * | 2000-05-19 | 2001-11-30 | Advantest Corp | Semiconductor circuit device and method of manufacturing the same |
| JP3882521B2 (en) * | 2001-03-29 | 2007-02-21 | セイコーエプソン株式会社 | Mounting method of semiconductor device |
| JP2002359320A (en) * | 2001-06-01 | 2002-12-13 | Toyo Commun Equip Co Ltd | Outer electrode pattern of electronic component |
| JP2004221372A (en) * | 2003-01-16 | 2004-08-05 | Seiko Epson Corp | Semiconductor device, semiconductor module, method of manufacturing both the same and electronic apparatus |
| JP2005019730A (en) * | 2003-06-26 | 2005-01-20 | Kyocera Corp | Wiring substrate and electronic device using it |
| JP2005072050A (en) * | 2003-08-27 | 2005-03-17 | Citizen Watch Co Ltd | Electronic device substrate, electronic device, and manufacturing method thereof |
| JP4443397B2 (en) * | 2004-12-13 | 2010-03-31 | シチズン電子株式会社 | Optical semiconductor element, optical semiconductor device, and method of manufacturing optical semiconductor element |
-
2009
- 2009-01-19 JP JP2009008970A patent/JP5218087B2/en active Active
- 2009-03-17 TW TW98108539A patent/TWI430413B/en active
- 2009-07-17 CN CN 200910159615 patent/CN101783335B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TW201029128A (en) | 2010-08-01 |
| TWI430413B (en) | 2014-03-11 |
| CN101783335B (en) | 2012-04-11 |
| JP2010165991A (en) | 2010-07-29 |
| JP5218087B2 (en) | 2013-06-26 |
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