JP7131933B2 - Packages for semiconductor devices and semiconductor devices - Google Patents

Packages for semiconductor devices and semiconductor devices Download PDF

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JP7131933B2
JP7131933B2 JP2018048236A JP2018048236A JP7131933B2 JP 7131933 B2 JP7131933 B2 JP 7131933B2 JP 2018048236 A JP2018048236 A JP 2018048236A JP 2018048236 A JP2018048236 A JP 2018048236A JP 7131933 B2 JP7131933 B2 JP 7131933B2
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frame
conductive portion
opening
semiconductor device
device package
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JP2019161109A (en
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広次 高橋
健太 黒田
一考 高木
亮太 鈴木
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Toshiba Corp
Toshiba Infrastructure Systems and Solutions Corp
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本発明の実施形態は、半導体装置用パッケージおよび半導体装置に関する。 TECHNICAL FIELD Embodiments of the present invention relate to semiconductor device packages and semiconductor devices.

半導体素子を収納するパッケージは、半導体素子を接合する金属ベース板と、内部を封止するためのセラミック部品と、を含む。 A package for housing a semiconductor device includes a metal base plate for bonding the semiconductor device and a ceramic component for sealing the inside.

たとえば、高周波半導体素子は、伝送線路に接続されるために矩形で薄い形状が用いられる。 For example, a high-frequency semiconductor element is rectangular and thin in shape to be connected to a transmission line.

しかしながら、セラミックベース板と金属ベース板とは互いに異なる線膨張率を有する。回路基板に実装後にパッケージや半田層にクラックが生じることを抑制するためにはパッケージの大きさに限界がある。 However, the ceramic base plate and the metal base plate have different coefficients of linear expansion. There is a limit to the size of the package in order to prevent cracks from occurring in the package and the solder layer after being mounted on the circuit board.

特開２００７－２４２９０８号公報Japanese Patent Application Laid-Open No. 2007-242908

キャビティサイズが広げられ、反りが低減可能な半導体装置用パッケージおよび半導体装置を提供する。 Provided are a package for a semiconductor device and a semiconductor device with a widened cavity size and reduced warpage.

実施形態の半導体装置用パッケージは、セラミック積層体と、信号経路と、金属ベース部と、を有する。前記セラミック積層体は、中央部に第１開口部を有する第１枠体と、前記第１枠体上に設けられかつ中央部に第２開口部を有する第２枠体と、を有する。前記第２枠体は、前記第１開口部と前記第２開口部とが重なるように積層され、前記第１枠体には、その上面から下面に連通する第１貫通孔が設けられる。前記第２枠体には、その上面から下面に連通する第２貫通孔が設けられ、前記第２枠体の前記上面に平行な平面視において、前記第２貫通孔は、前記第１貫通孔よりも外周側に設けられ、前記第２開口部のサイズは前記第１開口部のサイズよりも大きい。前記信号経路は、外部端子導電部と、中間配線導電部と、内部端子導電部と、第１導体ビアと、第２導体ビアと、を有する。前記外部端子導電部は前記第１枠体の前記下面に設けられ、前記中間配線導電部は前記第１枠体と前記第２枠体との間に設けられ、前記内部端子導電部は前記第２枠体の前記上面に設けられ、前記第１導体ビアは、前記第１貫通孔内に設けられ、前記外部端子導電部と前記中間配線導電部とを接続し、前記第２導体ビアは、前記第２貫通孔内に設けられ、前記中間配線導電部と前記内部端子導電部とを接続する。前記金属ベース板は、第１開口部にはめ込まれる第１部分と前記第２開口部にはめ込まれる第２部分とを有し、前記第２部分の上面であるチップ実装面が前記第１部分の下面よりも広い。前記金属ベース板の前記チップ実装面は、前記第２枠体の前記上面よりも下のレベルに位置する。
A semiconductor device package according to an embodiment includes a ceramic laminate, a signal path, and a metal base portion. The ceramic laminate has a first frame having a first opening in the center and a second frame provided on the first frame and having a second opening in the center. A said 2nd frame is laminated|stacked so that a said 1st opening and a said 2nd opening may overlap, The said 1st frame is provided with the 1st through-hole which communicates from the upper surface to the lower surface . The second frame is provided with a second through hole that communicates from the upper surface to the lower surface thereof, and in a plan view parallel to the upper surface of the second frame, the second through hole corresponds to the first through hole. The size of the second opening is larger than the size of the first opening. The signal path has an outer terminal conductive portion, an intermediate wiring conductive portion, an inner terminal conductive portion, a first conductor via, and a second conductor via. The external terminal conductive portion is provided on the lower surface of the first frame, the intermediate wiring conductive portion is provided between the first frame and the second frame, and the internal terminal conductive portion is provided on the first frame. 2. The first conductor via is provided on the upper surface of the frame body, the first conductor via is provided in the first through hole, and connects the external terminal conductive portion and the intermediate wiring conductive portion, and the second conductor via is , provided in the second through hole to connect the intermediate wiring conductive portion and the internal terminal conductive portion . The metal base plate has a first portion that is fitted into the first opening and a second portion that is fitted into the second opening, and the chip mounting surface, which is the top surface of the second portion, is the first portion. wider than the underside. The chip mounting surface of the metal base plate is located at a level lower than the top surface of the second frame.

図１（ａ）は第１の実施形態にかかる半導体装置用パッケージの模式平面図、図１（ｂ）はＡ－Ａ線に沿った模式断面図、である。FIG. 1(a) is a schematic plan view of the semiconductor device package according to the first embodiment, and FIG. 1(b) is a schematic cross-sectional view taken along line AA. 図２（ａ）はセラミック積層体の第１領域の模式下面図、図２（ｂ）は第１領域の模式上面図、図２（ｃ）はセラミック積層体の第２領域の模式下面図、図２（ｄ）は第２領域の模式上面図、である。2(a) is a schematic bottom view of the first region of the ceramic laminate, FIG. 2(b) is a schematic top view of the first region, FIG. 2(c) is a schematic bottom view of the second region of the ceramic laminate, FIG. 2D is a schematic top view of the second region. 製造方法のうち、セラミック積層体を形成する工程を説明する模式斜視図である。It is a schematic perspective view explaining the process of forming a ceramic laminated body among manufacturing methods. 図４（ａ）は第１の実施形態の変形例にかかる半導体装置用パッケージの模式平面図、図４（ｂ）はＡ－Ａ線に沿った模式断面図、である。FIG. 4A is a schematic plan view of a semiconductor device package according to a modification of the first embodiment, and FIG. 4B is a schematic cross-sectional view taken along line AA. セラミック積層体を３層重ねる構成を表す。It represents a configuration in which three layers of ceramic laminates are stacked. 図６（ａ）は第１の実施形態の半導体装置用パッケージを用いた半導体装置の模式平面図、図６（ｂ）はＡ－Ａ線に沿った模式断面図である。FIG. 6A is a schematic plan view of a semiconductor device using the semiconductor device package of the first embodiment, and FIG. 6B is a schematic cross-sectional view along line AA.

以下、図面を参照しつつ本発明の実施形態について説明する。
図１（ａ）は第１の実施形態にかかる半導体装置用パッケージの模式平面図、図１（ｂ）はＡ－Ａ線に沿った模式断面図、である。
半導体装置用パッケージ５は、セラミック積層体５０と、信号経路２０と、金属ベース板３０と、を有する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1(a) is a schematic plan view of the semiconductor device package according to the first embodiment, and FIG. 1(b) is a schematic cross-sectional view taken along line AA.
The semiconductor device package 5 has a ceramic laminate 50 , a signal path 20 and a metal base plate 30 .

セラミック積層体５０は、中央部に第１開口部を有する第１領域５１と、第１領域５１上に設けられかつ中央部に第２開口部を有する第２領域５２と、を含む。 The ceramic laminate 50 includes a first region 51 having a first opening in the center and a second region 52 provided on the first region 51 and having a second opening in the center.

第１領域５１には第１貫通孔が設けられ、第２領域５２には第１貫通孔よりも外周側に設けられた第２貫通孔が設けられる。また、第１領域５１と第２領域５２とは、平面視で同一の外形を有することができる。枠形の内の少なくと１辺に平行な方向（Ｘ軸）に沿って第２開口部の長さＤ２は第１開口部の長さＤ１よりも大きい。なお、Ｘ軸に直交するＹ軸に沿った第２開口部の長さは、Ｙ軸に沿った第１開口部の長さ以上とすることが好ましい。 A first through-hole is provided in the first region 51 , and a second through-hole is provided in the second region 52 on the outer peripheral side of the first through-hole. Also, the first region 51 and the second region 52 can have the same outer shape in plan view. The length D2 of the second opening is greater than the length D1 of the first opening along the direction (X-axis) parallel to at least one side of the frame. In addition, it is preferable that the length of the second opening along the Y-axis perpendicular to the X-axis is equal to or longer than the length of the first opening along the Y-axis.

信号経路２０は、外部端子導電部２１と、中間配線導電部２３と、内部端子導電部２５と、第１導体ビア２２と、第２導体ビア２４と、を有する。なお、第１の実施形態において、信号経路２０は、少なくともＸ軸に平行方向とする。 The signal path 20 has an external terminal conductive portion 21 , an intermediate wiring conductive portion 23 , an internal terminal conductive portion 25 , a first conductor via 22 and a second conductor via 24 . In the first embodiment, the signal path 20 is at least parallel to the X-axis.

外部端子導電部２１は、第１領域５１の下面に設けられる。中間配線導電部２３は、第１領域５１と第２領域５２との間に配置される。内部端子導電部２５は、第２領域５２の上面に設けられる。第１導体ビア２３は、第１貫通孔内に設けられかつ外部端子導電部２１と中間配線導電部２３とを接続する。第２導体ビア２４は、第２貫通孔内に設けられかつ内部配線導電部２３と内部端子導電部２５とを接続する。 The external terminal conductive portion 21 is provided on the bottom surface of the first region 51 . The intermediate wiring conductive portion 23 is arranged between the first region 51 and the second region 52 . The internal terminal conductive portion 25 is provided on the upper surface of the second region 52 . The first conductor via 23 is provided in the first through hole and connects the external terminal conductive portion 21 and the intermediate wiring conductive portion 23 . The second conductor via 24 is provided in the second through hole and connects the internal wiring conductive portion 23 and the internal terminal conductive portion 25 .

金属ベース板３０は、第１開口部の内縁５１ｅと第２開口部の内縁５２ｅとにそれぞれ接合される外縁３１ａ、３２ａを有し、かつ第１領域５１の下面と同一平面を構成する下面を有する。金属ベース板３０は、セラミック積層体５０の第１領域５１の第１開口部にはめ込まれる第１部分３１と、第２領域５２の第２開口部にはめ込まれる第２部分３２と、が銀ロウや銀ナノ粒子を含む接合材などで接合されたものでも良いし、一体化されて段差を有するものでもよい。金属ベース板３０の下面は、外部端子導電部２１の下面と同一平面を構成する。 The metal base plate 30 has outer edges 31a and 32a joined to the inner edge 51e of the first opening and the inner edge 52e of the second opening, respectively, and has a lower surface flush with the lower surface of the first region 51. have. The metal base plate 30 has a first portion 31 fitted into the first opening of the first region 51 of the ceramic laminate 50 and a second portion 32 fitted into the second opening of the second region 52, both of which are soldered with silver. or a bonding material containing silver nanoparticles, or may be integrated to have a step. The bottom surface of the metal base plate 30 forms the same plane as the bottom surface of the external terminal conductive portion 21 .

図１（ａ）には、信号経路２５が４つ配置されている。なお、Ａ－Ａ線に直交するＹ軸方向に対向する枠形の２つの辺の側にそれぞれ３つ内部端子導電部２７が設けられている。内部端子導電部２７の構造は内部端子導電部２６と同一でもよい。また内部端子導電部２５を、たとえば、高周波信号の信号経路とし、内部端子導電部２７、２８を直流電源への接続経路としてもよい。 Four signal paths 25 are arranged in FIG. Three internal terminal conductive portions 27 are provided on each of two sides of the frame shape facing each other in the Y-axis direction orthogonal to line AA. The internal terminal conductive portion 27 may have the same structure as the internal terminal conductive portion 26 . Alternatively, the internal terminal conductive portion 25 may be used as, for example, a signal path for high-frequency signals, and the internal terminal conductive portions 27 and 28 may be used as connection paths to a DC power supply.

第１の実施形態のパッケージ５は、たとえば、高周波増幅半導体装置のパッケージとして用いることができる。もし、信号経路をチップ実装面上に配置すると、内部端子導電部に金属リードなどを接合することなる。このため、半導体素子や整合回路を設ける内部空間（キャビティ部）の容積が減少する。 The package 5 of the first embodiment can be used, for example, as a package for a high frequency amplifying semiconductor device. If the signal path is arranged on the chip mounting surface, metal leads or the like will be joined to the internal terminal conductive portions. Therefore, the volume of the internal space (cavity portion) in which the semiconductor element and the matching circuit are provided is reduced.

これに対して、第１の実施形態では、信号給電位置をチップ実装面７上に設けない。外部からの信号給電位置は、パッケージ５の下面に設けられた外部端子導電部２１とされる。パッケージ５は、実装基板に表面実装される。このため、信号経路２０はパッケージ７の下面から内部端子導電部２５までの間に垂直経路を有する。第２導体ビア２４は、第１導体ビア２２よりもチップ実装面７上で外周側に設けられる。このため、内部端子導電部２５においてチップへの信号給電位置は外部からの信号給電位置よりも外周側にすることができる。この結果、チップ実装面７の面積を広くすることが可能である。 In contrast, in the first embodiment, no signal feeding position is provided on the chip mounting surface 7 . An external terminal conductive portion 21 provided on the lower surface of the package 5 is used as a signal feeding position from the outside. The package 5 is surface-mounted on the mounting board. Therefore, the signal path 20 has a vertical path from the bottom surface of the package 7 to the internal terminal conductive portion 25 . The second conductor vias 24 are provided closer to the outer periphery than the first conductor vias 22 on the chip mounting surface 7 . Therefore, in the internal terminal conductive portion 25, the signal feeding position to the chip can be located on the outer peripheral side of the signal feeding position from the outside. As a result, it is possible to increase the area of the chip mounting surface 7 .

次に、半導体装置用パッケージの製造方法の一例を説明する。
図２（ａ）はセラミック積層体の第１領域の模式下面図、図２（ｂ）は第１領域の模式上面図、図２（ｃ）はセラミック積層体の第２領域の模式下面図、図２（ｄ）は第２領域の模式上面図、である。
図２（ａ）に表すように、枠状セラミックからなる第１領域５１の下面５１ａには、第１貫通孔５１ｄを含むようして、枠形の対向する位置に４つの外部端子導電部（たとえば導電性厚膜を含む）２１がパターニングされる。 Next, an example of a method for manufacturing a semiconductor device package will be described.
2(a) is a schematic bottom view of the first region of the ceramic laminate, FIG. 2(b) is a schematic top view of the first region, FIG. 2(c) is a schematic bottom view of the second region of the ceramic laminate, FIG. 2D is a schematic top view of the second region.
As shown in FIG. 2A, the lower surface 51a of the first region 51 made of frame-shaped ceramic includes a first through hole 51d, and four external terminal conductive portions ( 21, including for example a conductive thick film, is patterned.

図２（ｂ）に表すように、第１領域５１の上面５１ｂには、第１貫通孔５１ｄ内またはその内壁に外部端子導電部２１に接続する第１導体ビア２２が設けられる。さらに第１領域５１の上面５１ｂには第１導体ビア２２に接続する内部配線導電部２３（たとえば導電性厚膜を含む）がパターニングされる。 As shown in FIG. 2B, on the upper surface 51b of the first region 51, a first conductor via 22 connected to the external terminal conductive portion 21 is provided in the first through hole 51d or on the inner wall thereof. Furthermore, on the upper surface 51b of the first region 51, an internal wiring conductive portion 23 (including, for example, a conductive thick film) connected to the first conductor via 22 is patterned.

また、図２（ｃ）に表すように、枠状セラミックからなる第２領域５２には、第２貫通孔５２ｄが設けられる。 Further, as shown in FIG. 2(c), the second region 52 made of frame-shaped ceramic is provided with a second through hole 52d.

図２（ｄ）に表すように、第２領域５２の上面５２ｂには、第２貫通孔５２ｄ内またはその内壁に外部端子導電部に接続する第２導体ビア２４が設けられる。さらに第２領域５２の上面５２ｂには第２導体ビア２４に接続する内部端子導電部２５（たとえば導電性厚膜を含む）がパターニングされる。 As shown in FIG. 2D, the upper surface 52b of the second region 52 is provided with a second conductor via 24 connected to the external terminal conductive portion inside the second through hole 52d or on the inner wall thereof. Further, the upper surface 52 b of the second region 52 is patterned with an internal terminal conductive portion 25 (including, for example, a conductive thick film) connected to the second conductive via 24 .

第１領域５１および第２領域５２が重なるように位置を合わせて焼成してセラミック積層体５０を形成する。こののち、金属ベース板３０の外縁と、第１開口部５１ｃの内縁および第１開口部５２ｃの内縁と、を金属ベース板３０の外縁と、を銀ロウや銀ナノ粒子を含む接合材などを用いて接合する。必要に応じて、外部端子導電部２１、内部端子導電部２５、金属ベース板３０のそれぞれの表面に、たとえば、金メッキなどを行い保護層とする。 The ceramic laminate 50 is formed by sintering in alignment so that the first region 51 and the second region 52 overlap each other. After that, the outer edge of the metal base plate 30, the inner edge of the first opening 51c, and the inner edge of the first opening 52c are combined with the outer edge of the metal base plate 30, and a bonding material containing silver solder or silver nanoparticles is applied. Join with If necessary, the surfaces of the external terminal conductive portion 21, the internal terminal conductive portion 25, and the metal base plate 30 are plated with gold, for example, to form a protective layer.

図３は、セラミック積層体を形成する工程を説明する模式斜視図である。
第１領域５１、および第２領域５２を外形が重なるように位置を合わせて焼成してセラミック積層体５０を形成する。こののち、金属ベース板３０の外縁と、第１開口部５１ｃの内縁５１ｅおよび第２開口部５２ｃの内縁５２ｅと、を金属ベース板３０の外縁と、を銀ロウや銀ナノ粒子を含む接合材などを用いて接合する。必要に応じて、外部端子導電部、内部端子導電部、金属ベース板３０のそれぞれの表面に、たとえば、金メッキなどを行い保護層とする。 FIG. 3 is a schematic perspective view explaining the process of forming a ceramic laminate.
The first region 51 and the second region 52 are aligned so that their outer shapes overlap each other and fired to form the ceramic laminate 50 . After that, the outer edge of the metal base plate 30, the inner edge 51e of the first opening 51c and the inner edge 52e of the second opening 52c, and the outer edge of the metal base plate 30 are combined with a bonding material containing silver solder or silver nanoparticles. and so on. If necessary, the respective surfaces of the external terminal conductive portion, the internal terminal conductive portion, and the metal base plate 30 are plated with gold, for example, to form a protective layer.

金属ベース板３０は、たとえば、ＣｕＷ、ＣｕＭｏ、Ｃｕなどとすることができる。
セラミック積層体５０は、Ａｌ２Ｏ３などのセラミックとすることができる。セラミックベース板の表面に厚膜などからなる導電層などが設けられたのち、複数の領域は焼結される。焼結されたセラミック積層体５０と、金属ベース板３０とは、たとえば、銀ロウ（融点は、７８０～９００℃）などでロウ付けされる。９６％Ａｌ２Ｏ３の線膨張率は、６．４×１０－６／Ｋである。ＣｕＷの線膨張率は約６．４×１０－６／Ｋである。金属ベース板５０をＣｕＷからなるものとすると、線膨張率の差が小さいので、セラミックベース板にクラックが生じることを低減できる。 The metal base plate 30 can be made of, for example, CuW, CuMo, Cu, or the like.
The ceramic laminate 50 can be a ceramic such as Al2O3 . After a conductive layer made of a thick film or the like is provided on the surface of the ceramic base plate, a plurality of regions are sintered. The sintered ceramic laminate 50 and the metal base plate 30 are brazed with, for example, silver solder (melting point: 780-900° C.). The linear expansion coefficient of 96% Al 2 O 3 is 6.4×10 −6 /K. CuW has a linear expansion coefficient of about 6.4×10 −6 /K. If the metal base plate 50 is made of CuW, the difference in coefficient of linear expansion is small, so cracks in the ceramic base plate can be reduced.

図４（ａ）は第１の実施形態の変形例にかかる半導体装置用パッケージの模式平面図、図４（ｂ）はＡ－Ａ線に沿った模式断面図、である。
セラミック積層体５０は、第２領域５２上に設けられかつ中央部に第３開口部を有する第３領域５３をさらに有することができる。枠形の第３領域５３を設けることにより、半導体素子や回路基板を金属ベース板３０に接合し、ワイヤボンディングをする内部空間を設け、かつ蓋部をさらに接合することにより封止が可能となる。 FIG. 4A is a schematic plan view of a semiconductor device package according to a modification of the first embodiment, and FIG. 4B is a schematic cross-sectional view taken along line AA.
The ceramic laminate 50 can further have a third region 53 provided on the second region 52 and having a third opening in the center. By providing the frame-shaped third region 53, a semiconductor element or a circuit board is bonded to the metal base plate 30, an internal space for wire bonding is provided, and sealing is possible by further bonding a lid portion. .

図５は、セラミック積層体を３層重ねる構成を表す。
セラミック積層体５０の第３領域５３の第３開口部５３ｃには、第２領域５２の上面５２ｂに設けられた内部端子導電部２５が露出する。 FIG. 5 shows a configuration in which three layers of ceramic laminates are stacked.
The internal terminal conductive portion 25 provided on the upper surface 52b of the second region 52 is exposed through the third opening 53c of the third region 53 of the ceramic laminate 50 .

図６（ａ）は第１の実施形態の半導体装置用パッケージを用いた半導体装置の模式平面図、図６（ｂ）はＡ－Ａ線に沿った模式断面図である。
図６（ｂ）には、実装基板９０を例示してある。実施形態の半導体装置は、第１の実施形態の半導体装置用パッケージ５と、金属ベース板３０上であるチップ実装面７に接合された半導体素子７０、７２と、半導体素子７０、７２と内部端子導電部２５とを接続するボンディングワイヤ８０、８１、８２と、第３領域５３の上面を封止する蓋部６０と、を有する。半導体素子７０、７２は、たとえば、ＨＥＭＴ（High Electron Mobility Transistor）などとすることができる。 FIG. 6A is a schematic plan view of a semiconductor device using the semiconductor device package of the first embodiment, and FIG. 6B is a schematic cross-sectional view along line AA.
FIG. 6B illustrates the mounting board 90 . The semiconductor device of the embodiment includes the semiconductor device package 5 of the first embodiment, semiconductor elements 70 and 72 bonded to the chip mounting surface 7 on the metal base plate 30, the semiconductor elements 70 and 72 and internal terminals. It has bonding wires 80 , 81 , 82 that connect with the conductive portion 25 , and a lid portion 60 that seals the upper surface of the third region 53 . The semiconductor elements 70 and 72 can be HEMTs (High Electron Mobility Transistors), for example.

また、半導体装置は入力側整合回路７４、段間回路７６、および出力整合回路７８をさらに有することができる。入力端子導電部２１ａには入力信号が入力され入力信号経路を経由して内部端子導電部２５ａへ伝送される。半導体素子７２からの出力信号は、内部端子導電部２５ｂおよび出力信号経路を経由して出力端子導電部２１ｂに伝送される。 Also, the semiconductor device can further have an input side matching circuit 74 , an interstage circuit 76 and an output matching circuit 78 . An input signal is input to the input terminal conductive portion 21a and transmitted to the internal terminal conductive portion 25a via the input signal path. An output signal from semiconductor element 72 is transmitted to output terminal conductive portion 21b via internal terminal conductive portion 25b and an output signal path.

金属ベース板３０の下面はチップ実装面７のサイズよりも小さいので、パッケージ５の線膨張率と実装基板９０の線膨張率との差異により半田層９２に生じるクラックを低減できる。 Since the lower surface of the metal base plate 30 is smaller than the chip mounting surface 7, cracks occurring in the solder layer 92 due to the difference between the linear expansion coefficients of the package 5 and the mounting substrate 90 can be reduced.

第１の実施形態によれば、キャビティサイズが広げられ、線膨張率の差異により生じる反りが低減可能な半導体装置用パッケージが提供される。また、このパッケージに高周波半導体素子を搭載すると、キャビティサイズが大きく、信頼性が高められた高周波半導体装置が提供される。この高周波半導体装置は、レーダ装置や衛星通信地上局などに広く使用される According to the first embodiment, there is provided a semiconductor device package in which the cavity size is widened and the warpage caused by the difference in coefficient of linear expansion can be reduced. Moreover, when a high-frequency semiconductor element is mounted in this package, a high-frequency semiconductor device having a large cavity size and improved reliability is provided. This high-frequency semiconductor device is widely used in radar equipment, satellite communication ground stations, etc.

本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。 While several embodiments of the invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

５ 半導体装置用パッケージ、７ チップ実装面、２０ 信号経路、２１ 外部端子導電部、２２ 第１導体ビア、２３ 内部配線導電部、２４ 第２導体ビア、２５ 内部端子導電部、３０ 金属ベース部、３１ 第１部分、３２ 第２部分、５０ セラミック積層体、５１ 第１領域、５１ｃ 第１開口部、５１ｄ 第１貫通孔、５２ 第２領域、第２開口部 ５２ｃ, ５２ｄ 第２貫通孔、５３ 第３領域、５３ｃ 第３開口部、６０ 蓋部、８０、８１、８２ ボンディングワイヤ、７０、７２ 半導体素子
5 semiconductor device package, 7 chip mounting surface, 20 signal path, 21 external terminal conductive portion, 22 first conductor via, 23 internal wiring conductive portion, 24 second conductive via, 25 internal terminal conductive portion, 30 metal base portion, 31 first portion 32 second portion 50 ceramic laminate 51 first region 51c first opening 51d first through hole 52 second region second opening 52c, 52d second through hole 53 Third region 53c Third opening 60 Lid 80, 81, 82 Bonding wire 70, 72 Semiconductor element

Claims (7)

中央部に第１開口部を有する第１枠体と、前記第１枠体上に設けられかつ中央部に第２開口部を有する第２枠体と、を有する枠形のセラミック積層体であって、前記第２枠体は、前記第１開口部と前記第２開口部とが重なるように積層され、前記第１枠体には、その上面から下面に連通する第１貫通孔が設けられ、前記第２枠体には、その上面から下面に連通する第２貫通孔が設けられ、前記第２枠体の前記上面に平行な平面視において、前記第２貫通孔は、前記第１貫通孔よりも外周側に設けられ、前記第２開口部のサイズは前記第１開口部のサイズよりも大きい、セラミック積層体と、
外部端子導電部と、中間配線導電部と、内部端子導電部と、第１導体ビアと、第２導体ビアと、を有する信号経路であって、前記外部端子導電部は前記第１枠体の前記下面に設けられ、前記中間配線導電部は前記第１枠体と前記第２枠体との間に設けられ、前記内部端子導電部は前記第２枠体の前記上面に設けられ、前記第１導体ビアは、前記第１貫通孔内に設けられ、前記外部端子導電部と前記中間配線導電部とを接続し、前記第２導体ビアは、前記第２貫通孔内に設けられ、前記中間配線導電部と前記内部端子導電部とを接続する、信号経路と、
第１開口部にはめ込まれる第１部分と前記第２開口部にはめ込まれる第２部分とを有し、前記第２部分の上面であるチップ実装面が前記第１部分の下面よりも広い金属ベース板と、
を備え、
前記金属ベース板の前記チップ実装面は、前記第２枠体の前記上面よりも下のレベルに位置する半導体装置用パッケージ。 A frame-shaped ceramic laminate having a first frame having a first opening in the center and a second frame provided on the first frame and having a second opening in the center. The second frame is laminated such that the first opening overlaps the second opening, and the first frame is provided with a first through hole communicating from the upper surface to the lower surface. , the second frame is provided with a second through hole that communicates from the upper surface to the lower surface thereof, and in a plan view parallel to the upper surface of the second frame, the second through hole corresponds to the first through hole a ceramic laminate provided on the outer peripheral side of the hole , wherein the size of the second opening is larger than the size of the first opening;
A signal path having an external terminal conductive portion, an intermediate wiring conductive portion, an internal terminal conductive portion, a first conductive via, and a second conductive via, wherein the external terminal conductive portion The intermediate wiring conductive portion is provided on the lower surface, the intermediate wiring conductive portion is provided between the first frame and the second frame , the internal terminal conductive portion is provided on the upper surface of the second frame, and the internal terminal conductive portion is provided on the upper surface of the second frame . A first conductor via is provided in the first through-hole and connects the external terminal conductive portion and the intermediate wiring conductive portion, and a second conductor via is provided in the second through-hole and is connected to the front side. a signal path connecting the intermediate wiring conductive portion and the internal terminal conductive portion;
A metal base having a first portion fitted in the first opening and a second portion fitted in the second opening, wherein the chip mounting surface, which is the top surface of the second portion, is wider than the bottom surface of the first portion. a board;
with
A semiconductor device package, wherein the chip mounting surface of the metal base plate is located at a level lower than the upper surface of the second frame . 前記セラミック積層体は、前記第２枠体上に設けられかつ中央部に第３開口部を有する第３枠体を含み、
前記第３枠体は、前記第３開口部が前記第２開口部に重なるように、前記第２枠体上に積層され、前記内部端子導電部の少なくとも一部が前記第３開口部の底面に露出する、請求項１記載の半導体装置用パッケージ。 The ceramic laminate includes a third frame provided on the second frame and having a third opening in the center ,
The third frame is laminated on the second frame so that the third opening overlaps the second opening, and at least part of the internal terminal conductive portion is a bottom surface of the third opening. 2. The semiconductor device package according to claim 1, wherein the semiconductor device package is exposed to . 前記第１枠体と前記第２枠体と前記第３枠体とは、前記第２枠体の前記上面に平行な平面視において同一の外形を有する請求項２記載の半導体装置用パッケージ。 3. The semiconductor device package according to claim 2, wherein said first frame , said second frame and said third frame have the same outline when viewed in plan parallel to said upper surface of said second frame . 前記第２枠体の前記第２開口部は、前記第２枠体の前記上面に平行な平面視において、四角の形状を有し、
前記信号経路は、前記第２開口部を構成する４つの辺のうちの対向する２つの辺の外側にそれぞれ配置される請求項１～３のいずれか１つに記載の半導体装置用パッケージ。 the second opening of the second frame has a square shape in a plan view parallel to the upper surface of the second frame;
4. The semiconductor device package according to claim 1, wherein said signal paths are arranged outside two opposite sides of four sides forming said second opening . 前記セラミック積層体は焼結体を含む請求項１～４のいずれか１つに記載の半導体装置用パッケージ。 5. The semiconductor device package according to claim 1, wherein said ceramic laminate includes a sintered body. 前記セラミック積層体と前記金属ベース板とは銀ロウまたは銀ナノ粒子により接合された請求項１～５のいずれか１つに記載の半導体装置用パッケージ。 6. The semiconductor device package according to claim 1, wherein said ceramic laminate and said metal base plate are joined by silver brazing or silver nanoparticles. 請求項１～６のいずれか１つに記載の半導体装置用パッケージと、
前記金属ベース板の上面に接合された半導体素子と、
前記半導体素子と前記内部端子導電部とを接続するボンディングワイヤと、
前記半導体素子および前記ボンディングワイヤを封止する蓋部と、
を備えた半導体装置。 a semiconductor device package according to any one of claims 1 to 6;
a semiconductor element bonded to the upper surface of the metal base plate;
a bonding wire connecting the semiconductor element and the internal terminal conductive portion;
a lid that seals the semiconductor element and the bonding wire;
A semiconductor device with
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