TWI427640B - 使用多電壓域之電路中信號路徑延遲之自調整 - Google Patents

使用多電壓域之電路中信號路徑延遲之自調整 Download PDF

Info

Publication number
TWI427640B
TWI427640B TW098143418A TW98143418A TWI427640B TW I427640 B TWI427640 B TW I427640B TW 098143418 A TW098143418 A TW 098143418A TW 98143418 A TW98143418 A TW 98143418A TW I427640 B TWI427640 B TW I427640B
Authority
TW
Taiwan
Prior art keywords
voltage
delay
circuit
path
paths
Prior art date
Application number
TW098143418A
Other languages
English (en)
Chinese (zh)
Other versions
TW201040984A (en
Inventor
Chiaming Chai
Stephen Edward Liles
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of TW201040984A publication Critical patent/TW201040984A/zh
Application granted granted Critical
Publication of TWI427640B publication Critical patent/TWI427640B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)
TW098143418A 2008-12-17 2009-12-17 使用多電壓域之電路中信號路徑延遲之自調整 TWI427640B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/336,741 US7876631B2 (en) 2008-12-17 2008-12-17 Self-tuning of signal path delay in circuit employing multiple voltage domains

Publications (2)

Publication Number Publication Date
TW201040984A TW201040984A (en) 2010-11-16
TWI427640B true TWI427640B (zh) 2014-02-21

Family

ID=41559655

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098143418A TWI427640B (zh) 2008-12-17 2009-12-17 使用多電壓域之電路中信號路徑延遲之自調整

Country Status (8)

Country Link
US (1) US7876631B2 (ja)
EP (1) EP2380174B1 (ja)
JP (1) JP5355711B2 (ja)
KR (1) KR101259899B1 (ja)
CN (1) CN102246236B (ja)
BR (1) BRPI0922986A2 (ja)
TW (1) TWI427640B (ja)
WO (1) WO2010077776A1 (ja)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8930733B2 (en) 2009-06-12 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Separating power domains of central processing units
US8995207B2 (en) 2011-08-12 2015-03-31 Qualcomm Incorporated Data storage for voltage domain crossings
US20130227197A1 (en) * 2012-02-29 2013-08-29 Sandisk Technologies Inc. Multiple pre-driver logic for io high speed interfaces
US8638153B2 (en) * 2012-03-29 2014-01-28 Qualcomm Incorporated Pulse clock generation logic with built-in level shifter and programmable rising edge and pulse width
CN102723755A (zh) * 2012-06-14 2012-10-10 北京华大智宝电子系统有限公司 一种电池组信息采集管理结构
US9070433B1 (en) 2014-03-11 2015-06-30 International Business Machines Corporation SRAM supply voltage global bitline precharge pulse
US9418716B1 (en) * 2015-04-15 2016-08-16 Qualcomm Incorporated Word line and bit line tracking across diverse power domains
CN104868906A (zh) * 2015-05-26 2015-08-26 施文斌 集成电路和电压选择电路
US9954527B2 (en) * 2015-09-29 2018-04-24 Nvidia Corporation Balanced charge-recycling repeater link
KR102531863B1 (ko) * 2018-03-28 2023-05-11 삼성전자주식회사 반도체 메모리 장치의 홀드-마진을 제어하는 방법 및 시스템

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6031779A (en) * 1997-04-10 2000-02-29 Hitachi, Ltd. Dynamic memory
US6034920A (en) * 1998-11-24 2000-03-07 Texas Instruments Incorporated Semiconductor memory device having a back gate voltage controlled delay circuit
US20040133864A1 (en) * 2003-01-07 2004-07-08 International Business Machines Corporation Programmable delay method for hierarchical signal balancing
US20060214696A1 (en) * 2003-08-04 2006-09-28 Daniel Timmermans Voltage supply structure and method
US20060220721A1 (en) * 2005-04-04 2006-10-05 Nitin Vig Clock delay compensation circuit
US20080056031A1 (en) * 2002-03-15 2008-03-06 Nec Electronics Corporation Semiconductor memory
US7388774B1 (en) * 2007-10-16 2008-06-17 Juhan Kim SRAM including bottom gate transistor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04362810A (ja) * 1991-06-11 1992-12-15 Fuji Electric Co Ltd 論理信号遅延回路
JP2002109887A (ja) * 2000-09-29 2002-04-12 Hitachi Ltd 半導体集積回路
JP3908493B2 (ja) * 2001-08-30 2007-04-25 株式会社東芝 電子回路及び半導体記憶装置
US6831853B2 (en) * 2002-11-19 2004-12-14 Taiwan Semiconductor Manufacturing Company Apparatus for cleaning a substrate
US7355905B2 (en) * 2005-07-01 2008-04-08 P.A. Semi, Inc. Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage
KR100655084B1 (ko) * 2006-01-17 2006-12-08 삼성전자주식회사 센스앰프 인에이블 회로 및 이를 갖는 반도체 메모리 장치
US7542332B1 (en) * 2007-10-16 2009-06-02 Juhan Kim Stacked SRAM including segment read circuit
US7542348B1 (en) * 2007-12-19 2009-06-02 Juhan Kim NOR flash memory including bipolar segment read circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6031779A (en) * 1997-04-10 2000-02-29 Hitachi, Ltd. Dynamic memory
US6034920A (en) * 1998-11-24 2000-03-07 Texas Instruments Incorporated Semiconductor memory device having a back gate voltage controlled delay circuit
US20080056031A1 (en) * 2002-03-15 2008-03-06 Nec Electronics Corporation Semiconductor memory
US20040133864A1 (en) * 2003-01-07 2004-07-08 International Business Machines Corporation Programmable delay method for hierarchical signal balancing
US20060214696A1 (en) * 2003-08-04 2006-09-28 Daniel Timmermans Voltage supply structure and method
US20060220721A1 (en) * 2005-04-04 2006-10-05 Nitin Vig Clock delay compensation circuit
US7388774B1 (en) * 2007-10-16 2008-06-17 Juhan Kim SRAM including bottom gate transistor

Also Published As

Publication number Publication date
JP5355711B2 (ja) 2013-11-27
EP2380174B1 (en) 2016-03-23
KR20110106386A (ko) 2011-09-28
US20100148839A1 (en) 2010-06-17
TW201040984A (en) 2010-11-16
KR101259899B1 (ko) 2013-05-02
BRPI0922986A2 (pt) 2016-01-26
WO2010077776A1 (en) 2010-07-08
EP2380174A1 (en) 2011-10-26
JP2012512497A (ja) 2012-05-31
CN102246236A (zh) 2011-11-16
US7876631B2 (en) 2011-01-25
CN102246236B (zh) 2014-09-03

Similar Documents

Publication Publication Date Title
TWI427640B (zh) 使用多電壓域之電路中信號路徑延遲之自調整
US7327630B2 (en) Memory cell power switching circuit in semiconductor memory device and method for applying memory cell power voltage
US7834662B2 (en) Level shifter with embedded logic and low minimum voltage
JP3883126B2 (ja) 半導体集積回路装置、それが組み込まれた電子装置、及び消費電力低減方法
US9977480B2 (en) Selective coupling of power rails to a memory domain(s) in a processor-based system
US20030120962A1 (en) Method and apparatus for enabling a low power mode for a processor
US20120275236A1 (en) Method and Apparatus for Power Domain Isolation during Power Down
US20100085079A1 (en) Low Latency, Power-Down Safe Level Shifter
EP3069345B1 (en) System and method for reducing memory i/o power via data masking
US8102728B2 (en) Cache optimizations using multiple threshold voltage transistors
KR101482091B1 (ko) 저전력, 고수율 메모리를 위한 방법들 및 시스템들
US11493980B1 (en) Power controller communication latency mitigation
US6816994B2 (en) Low power buffer implementation
US8452993B2 (en) Circuits, systems, and methods for dynamically controlling a power supply configuration in response to load requirements from a digital circuit
KR20170092437A (ko) 초저전압 디지털 회로 및 그것의 동작 방법