TWI426593B - Chip for use with multi-chip stack package and its stack package structure - Google Patents
Chip for use with multi-chip stack package and its stack package structure Download PDFInfo
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- TWI426593B TWI426593B TW099139656A TW99139656A TWI426593B TW I426593 B TWI426593 B TW I426593B TW 099139656 A TW099139656 A TW 099139656A TW 99139656 A TW99139656 A TW 99139656A TW I426593 B TWI426593 B TW I426593B
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- 235000012431 wafers Nutrition 0.000 claims description 162
- 239000004065 semiconductor Substances 0.000 claims description 86
- 239000000853 adhesive Substances 0.000 claims description 18
- 230000001070 adhesive effect Effects 0.000 claims description 18
- 239000003292 glue Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 description 8
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- 229920005989 resin Polymers 0.000 description 5
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- 230000009471 action Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000009993 protective function Effects 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/24146—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Description
本發明是有關於一種用於多晶片堆疊封裝之晶片及其堆疊封裝結構，更詳而言之，是關於一種用於防止導電膠溢流而導致電性短路的晶片及其堆疊封裝結構。The present invention relates to a wafer for a multi-wafer stacked package and a stacked package structure thereof, and more particularly to a wafer for preventing electrical overcurrent caused by a conductive paste from overflowing and a stacked package structure thereof.
於晶片封裝製程中，晶片可藉由點膠技術而與基板完成電性連接，再由封裝膠體包覆晶片而完成封裝。於第20080303131、20090068790及20090230528號美國專利公開案中，皆已揭示之一種多晶片堆疊結構，舉例說明，請參閱第1圖及第2圖所繪示，分別係為習知多晶片堆疊結構之局部俯視圖及剖視圖，於習知多晶片堆疊結構中，於基板10之頂面設置有複數電性連接墊11，於各晶片20之頂面設置有複數電極墊21，於各晶片20之底面貼附有絕緣膠30，且各晶片20係以不妨礙施於電性連接墊11及電極墊21之點膠作業為原則下堆疊於基板10上，導電膠40電性連接基板10之電性連接墊11及各晶片20之電極墊21，並形成彼此相鄰之導電膠40，封膠50覆蓋基板10、晶片20、絕緣膠30及導電膠40。In the wafer packaging process, the wafer can be electrically connected to the substrate by a dispensing technique, and then encapsulated by the encapsulant to complete the package. A multi-wafer stack structure has been disclosed in US Patent Publication No. 20080303131, 20090068790, and No. 20090230528. For example, please refer to FIG. 1 and FIG. 2, which are respectively a part of a conventional multi-wafer stack structure. In the conventional multi-wafer stack structure, a plurality of electrical connection pads 11 are disposed on the top surface of the substrate 10, and a plurality of electrode pads 21 are disposed on the top surface of each of the wafers 20, and the bottom surface of each of the wafers 20 is attached. The insulating paste 30 is electrically stacked on the substrate 10 on the basis of the dispensing operation of the electrical connection pad 11 and the electrode pad 21, and the conductive adhesive 40 is electrically connected to the electrical connection pad 11 of the substrate 10. And the electrode pads 21 of each of the wafers 20, and the conductive paste 40 adjacent to each other is formed, and the sealant 50 covers the substrate 10, the wafer 20, the insulating paste 30, and the conductive paste 40.
惟，於習知晶片封裝結構中，呈半液態狀時之導電膠40容易在各晶片20之邊緣處溢流(如第1圖所示)，若任二相鄰之電極墊21之間之距離太近時，例如小於260um，在晶片20之邊緣處，容易發生相鄰導電膠40溢流而彼此連接，並導致電性短路，即任二相鄰之導電膠40因點膠時之物理溢流現象而彼此電性連接。尤其，當各晶片20中之各電極墊21距離越小時，電性短路之發生率愈高。如此，產生晶片組短路問題，使得產品報廢，或須進行重新點膠作業，因此浪費大量生產成本，令產品之良率及可靠度大幅降低。However, in the conventional chip package structure, the conductive paste 40 in a semi-liquid state easily overflows at the edge of each wafer 20 (as shown in FIG. 1), if any two adjacent electrode pads 21 are between When the distance is too close, for example, less than 260 um, at the edge of the wafer 20, the adjacent conductive paste 40 is easily overflowed and connected to each other, and causes an electrical short circuit, that is, the physical properties of any two adjacent conductive pastes 40 due to dispensing. The overflow phenomenon is electrically connected to each other. In particular, the smaller the distance between the electrode pads 21 in each of the wafers 20, the higher the incidence of electrical shorts. In this way, the chip group short circuit problem occurs, so that the product is scrapped or re-dispensing operation is required, thereby wasting a large amount of production cost, and the yield and reliability of the product are greatly reduced.
綜上所述，解決上述習知技術之缺失，以防止導電膠發生短路現象，實為目前亟欲解決之技術問題。In summary, solving the above-mentioned lack of the prior art to prevent the short circuit of the conductive adhesive is a technical problem that is currently being solved.
鑒於上述習知技術之缺點，本發明之主要目的在於提供一種用於多晶片堆疊封裝之晶片及其堆疊封裝結構，防止導電膠溢流而導致電性短路之情形，進而提升產品良率及可靠度。In view of the above disadvantages of the prior art, the main object of the present invention is to provide a wafer for a multi-wafer stack package and a stacked package structure thereof, which prevent the conductive glue from overflowing and cause an electrical short circuit, thereby improving product yield and reliability. degree.
為達上述及其他目的，本發明提供一種用於多晶片堆疊封裝之晶片，係包括：層狀本體，具有相對之作用面及非作用面，且該作用面上具有堆疊區及非堆疊區；複數電極墊，係設於該作用面之非堆疊區上；以及複數凹槽，係鄰近該些電極墊且位於該層狀本體之側邊。To achieve the above and other objects, the present invention provides a wafer for a multi-wafer stack package, comprising: a layered body having opposite active and non-active surfaces, and having a stacked area and a non-stacked area on the active surface; A plurality of electrode pads are disposed on the non-stacking regions of the active surface; and a plurality of recesses adjacent to the electrode pads and located on sides of the layered body.
具體而言，該些電極墊係呈線性排列，且各該凹槽亦形成於該非堆疊區之長邊，以分別對應相鄰之電極墊。另外，該凹槽貫穿該層狀本體。Specifically, the electrode pads are linearly arranged, and each of the grooves is also formed on a long side of the non-stacking region to respectively correspond to adjacent electrode pads. Additionally, the groove extends through the layered body.
本發明復提供一種多晶片堆疊封裝結構，係包括晶片承載件、半導體晶片、絕緣膠及導電膠。該晶片承載件上設置有複數電性連接墊。各該半導體晶片具有相對之作用面及非作用面，且彼此以作用面朝上自該些電性連接墊旁依序以錯位方式堆疊於該晶片承載件上，以使各該半導體晶片之作用面之一部分係外露出該堆疊於其上之半導體晶片，各該經堆疊之半導體晶片之外露作用面上設有複數電極墊，且各該半導體晶片鄰近該些電極墊之側邊形成有對應該些電極墊之複數凹槽。該絕緣膠設於該晶片承載件與該堆疊於晶片承載件上之半導體晶片之間。該導電膠電性連接該電性連接墊及該半導體晶片上之對應該電性連接墊之電極墊，以藉由該導電膠使該半導體晶片電性連接該晶片承載件，並由各該凹槽阻擋同一晶片上之相鄰兩電極墊之間的導電膠彼此連接。The present invention provides a multi-wafer stacked package structure including a wafer carrier, a semiconductor wafer, an insulating paste, and a conductive paste. A plurality of electrical connection pads are disposed on the wafer carrier. Each of the semiconductor wafers has opposite active and non-active surfaces, and is stacked on the wafer carrier in a staggered manner from the side of the electrical connection pads in order to make the semiconductor wafers function. One of the faces exposes the semiconductor wafer stacked thereon, and each of the stacked semiconductor wafers is provided with a plurality of electrode pads on the exposed surface, and each of the semiconductor wafers is formed adjacent to the sides of the electrode pads. A plurality of recesses of the electrode pads. The insulating paste is disposed between the wafer carrier and the semiconductor wafer stacked on the wafer carrier. The conductive adhesive is electrically connected to the electrical connection pad and the electrode pad of the semiconductor wafer corresponding to the electrical connection pad, so that the semiconductor chip is electrically connected to the wafer carrier by the conductive adhesive, and each of the concave The trench blocks the conductive paste between adjacent electrode pads on the same wafer from being connected to each other.
於一實施樣態中，該些電性連接墊係呈線性排列，並對應該半導體晶片之外露作用面邊緣，詳言之，各該電性連接墊係分別對應於堆疊在晶片承載件上之半導體晶片之該些電極墊旁。In an embodiment, the electrical connection pads are linearly arranged and correspond to the exposed surface of the semiconductor wafer. In detail, each of the electrical connection pads corresponds to the stacked on the wafer carrier. Next to the electrode pads of the semiconductor wafer.
又，該些電極墊係呈線性排列，且各該凹槽亦形成於該外露作用面之長邊，以分別對應相鄰之電極墊。另外，該凹槽貫穿該半導體晶片。Moreover, the electrode pads are linearly arranged, and each of the grooves is also formed on a long side of the exposed active surface to respectively correspond to adjacent electrode pads. Additionally, the recess extends through the semiconductor wafer.
特別地，在前述之多晶片堆疊封裝結構中，該些半導體晶片可彼此以階梯狀方式堆疊，此外，於另一實施樣態中，該些半導體晶片彼此以鋸齒狀方式堆疊，但不限於此些實施樣態，其亦可以階梯狀方式搭配鋸齒狀方式而堆疊。In particular, in the foregoing multi-wafer stacked package structure, the semiconductor wafers may be stacked in a stepped manner with each other. Further, in another embodiment, the semiconductor wafers are stacked in a zigzag manner with each other, but are not limited thereto. In some implementations, they can also be stacked in a stepped manner in a zigzag manner.
實質上，在此處，介於該晶片承載件及疊接在該晶片承載件上之該半導體晶片之間之絕緣膠厚度大於任二相疊接之該半導體晶片之間之絕緣膠厚度。Essentially, here, the thickness of the insulating glue between the wafer carrier and the semiconductor wafer stacked on the wafer carrier is greater than the thickness of the insulating paste between the semiconductor wafers of any two phases.
相較於習知技術，本發明之用於多晶片堆疊封裝之晶片及其堆疊封裝結構，任二相鄰之導電膠係藉由該些凹槽導引導電膠，並阻擋同一晶片上之相鄰兩電極墊之間的導電膠彼此連接，從而在該半導體晶片之邊緣處，避免發生因溢流黏接所導致之電性短路，據此，限制點膠時之物理溢流現象，能有效防止呈半液態狀時之導電膠在各該半導體晶片之邊緣處溢流，因而解決先前技術中之晶片短路問題，如此，不會造成產品報廢且無須進行重新點膠作業，以此而能提升產品之良率及可靠度。Compared with the prior art, the wafer for multi-wafer stacked package and the stacked package structure thereof of the present invention, any two adjacent conductive adhesives guide the conductive adhesive through the grooves, and block the phase on the same wafer The conductive adhesive between the adjacent two electrode pads is connected to each other, so that an electrical short circuit caused by overflow bonding is avoided at the edge of the semiconductor wafer, thereby limiting the physical overflow phenomenon during dispensing, which can effectively Preventing the conductive paste in a semi-liquid state from overflowing at the edge of each of the semiconductor wafers, thereby solving the problem of the wafer short circuit in the prior art, so that the product is not scrapped and no re-dispensing operation is required, thereby improving Product yield and reliability.
以下是藉由特定的具體實例說明本發明之技術內容，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。The following is a description of the technical contents of the present invention by way of specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the disclosure of the present specification.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered.
本發明提供一種用於多晶片堆疊封裝之晶片，請參照第3圖至第5圖所繪示，分別係為本發明之用於多晶片堆疊封裝之晶片之局部俯視圖、本發明之用於多晶片堆疊封裝之晶片之一實施例之局部側剖視圖以及本發明之用於多晶片堆疊封裝之晶片之另一實施例之局部側剖視圖，在一實施樣態中，該用於多晶片堆疊封裝之晶片係包括層狀本體2、複數電極墊210及複數凹槽220。The present invention provides a wafer for a multi-wafer stack package, which is illustrated in FIGS. 3 to 5, which are respectively partial top views of a wafer for a multi-wafer stacked package of the present invention, and the present invention is used for multiple A partial side cross-sectional view of one embodiment of a wafer of wafer-stacked packages and a partial side cross-sectional view of another embodiment of a wafer for multi-wafer stacked packages of the present invention, in one embodiment, for multi-wafer stack packaging The wafer system includes a layered body 2, a plurality of electrode pads 210, and a plurality of grooves 220.
首先，如第3圖及第4圖所示，該層狀本體2係例如為快閃記憶體晶片，該層狀本體2具有相互對應之作用面201及非作用面202，且該作用面201上具有堆疊區203及非堆疊區204，該些電極墊210係設於該作用面201之非堆疊區204上，該些凹槽220係分別對應該些電極墊210並鄰近該些電極墊210而形成於該層狀本體2之側邊。First, as shown in FIG. 3 and FIG. 4, the layered body 2 is, for example, a flash memory chip, and the layered body 2 has mutually acting active surfaces 201 and non-active surfaces 202, and the active surface 201 The electrode pad 210 is disposed on the non-stacking region 204 of the active surface 201. The recesses 220 respectively correspond to the electrode pads 210 and adjacent to the electrode pads 210. It is formed on the side of the layered body 2.
進一步說明之，該層狀本體2上之該些電極墊210係彼此鄰近地呈線性排列，但不直接連接或接觸，該些電極墊210並係設於該層狀本體2之作用面201之非堆疊區204之長邊，並間隔該作用面201之邊緣有一段距離，在此處，該些凹槽220係設於該層狀本體2之作用面201之非堆疊區204之長邊之側邊並貫穿該層狀本體2，且該些凹槽220如同該些電極墊210一般係彼此鄰近地呈線性排列，但不直接連通。Further, the electrode pads 210 on the layered body 2 are linearly arranged adjacent to each other, but are not directly connected or contacted. The electrode pads 210 are disposed on the active surface 201 of the layered body 2. The long sides of the non-stacking regions 204 are spaced apart from each other by a distance from the edge of the active surface 201. Here, the recesses 220 are disposed on the long sides of the non-stacking regions 204 of the active surface 201 of the layered body 2. The side edges extend through the layered body 2, and the grooves 220 are generally linearly arranged adjacent to each other as the electrode pads 210, but are not in direct communication.
特別地，該些凹槽220係可為藉由雷射切割製程而形成者，但不以此種製程為限制，其亦可藉由一般機械加工而形成，又，該些凹槽220通常係在該些電極墊210已形成之後，於切割晶圓製程期間所加工形成，但並非限制在此時間點。In particular, the grooves 220 may be formed by a laser cutting process, but are not limited by such a process, and may also be formed by general machining. Moreover, the grooves 220 are usually After the electrode pads 210 have been formed, they are processed during the dicing wafer process, but are not limited at this point in time.
於一實施例中，如第4圖所示，該凹槽220形成在該層狀本體2之側邊並貫穿該層狀本體2，在此處，其側向斷面之形狀係如圖所示為梯形，而於另一實施例中，如第5圖所示，該凹槽220形成在層狀本體2之側邊並貫穿該層狀本體2，在此處，其側向斷面之形狀係如圖所示為矩形，然而，該凹槽220之側向斷面之形狀並不會被加以限制，其亦可為多邊形、圓弧形、波浪形等或其組合。In an embodiment, as shown in FIG. 4, the groove 220 is formed on the side of the layered body 2 and penetrates the layered body 2, where the shape of the lateral section is as shown in the figure. Shown as a trapezoid, in another embodiment, as shown in FIG. 5, the groove 220 is formed on the side of the layered body 2 and penetrates the layered body 2, where the lateral section is The shape is rectangular as shown in the figure, however, the shape of the lateral section of the groove 220 is not limited, and may be a polygon, a circular arc, a wave, or the like, or a combination thereof.
據此，當以本發明之用於多晶片堆疊封裝之晶片用於堆疊複數晶片後，進行導電膠之點膠作業(dispensing process)時，藉由各該凹槽220之槽壁阻擋同一晶片上相鄰兩電極墊210之間的導電膠彼此連接，詳言之，導電膠之一部分可順流至對應該電極墊210之凹槽220中，以防止導電膠在層狀本體2之邊緣處發生溢流，避免溢流現象所造成之電性短路，進而提升產品良率及可靠度。According to this, when the wafer for multi-wafer stacked package of the present invention is used for stacking a plurality of wafers, the dispensing process of the conductive paste is performed, and the groove walls of the grooves 220 are blocked on the same wafer. The conductive paste between the adjacent two electrode pads 210 is connected to each other. In detail, a portion of the conductive paste can flow down into the recess 220 corresponding to the electrode pad 210 to prevent the conductive paste from overflowing at the edge of the layered body 2. Flow, avoiding electrical short circuit caused by overflow phenomenon, thereby improving product yield and reliability.
本發明復提供一種多晶片堆疊封裝結構，請參照第6圖至第9圖所繪示，分別係為本發明之多晶片堆疊封裝結構之局部俯視圖、本發明之多晶片堆疊封裝結構之一實施例之局部側剖視圖、本發明之多晶片堆疊封裝結構之另一實施例之局部側剖視圖以及本發明之多晶片堆疊封裝結構之再一實施例之局部側剖視圖，在一實施樣態中，該多晶片堆疊封裝結構係包括晶片承載件100、複數半導體晶片200、絕緣膠300、導電膠400及封裝樹脂500。The present invention provides a multi-wafer stack package structure, which is shown in FIGS. 6 to 9 respectively, which is a partial top view of the multi-wafer stack package structure of the present invention, and an implementation of the multi-wafer stack package structure of the present invention. A partial side cross-sectional view of another embodiment, a partial side cross-sectional view of another embodiment of the multi-wafer stacked package structure of the present invention, and a partial side cross-sectional view of still another embodiment of the multi-wafer stacked package structure of the present invention, in an embodiment, The multi-wafer stacked package structure includes a wafer carrier 100, a plurality of semiconductor wafers 200, an insulating paste 300, a conductive paste 400, and an encapsulating resin 500.
首先，如第6圖及第7圖所示，於該晶片承載件100上設置有複數電性連接墊110，其具有導電性質，該晶片承載件100上之該些電性連接墊110係彼此鄰近地呈線性排列，但不直接連接或接觸。First, as shown in FIG. 6 and FIG. 7, a plurality of electrical connection pads 110 are disposed on the wafer carrier 100, and the electrical connection pads 110 on the wafer carrier 100 are connected to each other. Arranged linearly adjacent, but not directly connected or in contact.
各該半導體晶片200具有相互對應之作用面201及非作用面202，該絕緣膠300設於該些半導體晶片200之間，較佳地，該絕緣膠300預先貼附於各該半導體晶片200之非作用面202，且各該半導體晶片200彼此以作用面201朝上及自該電性連接墊110旁依序以錯位方式堆疊於該晶片承載件100上，以使各該半導體晶片200之作用面201之一部分係外露出該堆疊於其上之半導體晶片200。Each of the semiconductor wafers 200 has an active surface 201 and an inactive surface 202. The insulating paste 300 is disposed between the semiconductor wafers 200. Preferably, the insulating paste 300 is pre-attached to each of the semiconductor wafers 200. The non-active surface 202, and each of the semiconductor wafers 200 are stacked on the wafer carrier 100 in a staggered manner with the active surface 201 facing upward and from the electrical connection pad 110, so that the semiconductor wafers 200 function. A portion of the face 201 exposes the semiconductor wafer 200 stacked thereon.
復進一步說明，該些半導體晶片200的平面尺寸約略相同，該與晶片承載件100黏接之半導體晶片200設置在鄰近該電性連接墊110之位置，上層之該些半導體晶片200則分別以一預先設定的距離依序偏移下層之該半導體晶片200而相互堆疊，且該些半導體晶片200不致遮蔽該電性連接墊110。Further, the planar dimensions of the semiconductor wafers 200 are approximately the same, the semiconductor wafers 200 bonded to the wafer carrier 100 are disposed adjacent to the electrical connection pads 110, and the semiconductor wafers 200 of the upper layers are respectively The predetermined distance is sequentially offset from the underlying semiconductor wafer 200 and stacked on each other, and the semiconductor wafers 200 are not shielded from the electrical connection pads 110.
另外，各該經堆疊之半導體晶片200之外露作用面201上設有複數電極墊210，各該半導體晶片200上之該些電極墊210係彼此鄰近地呈線性排列，該些電極墊210並設於該外露作用面201之長邊，因此，各該電性連接墊110設於該晶片承載件100上之位置係分別對應於堆疊在晶片承載件100上之半導體晶片200之該些電極墊210旁，此外，該些電性連接墊110並對應該半導體晶片200之外露作用面201邊緣。In addition, a plurality of electrode pads 210 are disposed on the exposed surface 201 of each of the stacked semiconductor wafers 200. The electrode pads 210 on each of the semiconductor wafers 200 are linearly arranged adjacent to each other, and the electrode pads 210 are disposed in parallel. On the long side of the exposed active surface 201, the positions of the electrical connection pads 110 on the wafer carrier 100 correspond to the electrode pads 210 of the semiconductor wafer 200 stacked on the wafer carrier 100, respectively. In addition, in addition, the electrical connection pads 110 and the semiconductor wafer 200 are exposed to the edge of the active surface 201.
詳言之，各該半導體晶片200之作用面201上對應該些電性連接墊110之同側處設置有該些電極墊210，且該些電極墊210曝露於該半導體晶片200之上方空間，意即上層之該半導體晶片200不致遮蔽下層之該半導體晶片的該些電極墊210，此時，該些電性連接墊110係設置於該晶片承載件100上未黏接該半導體晶片200之區域，該些電極墊210係設置於該半導體晶片200上未堆疊其他該半導體晶片200之區域。In detail, the electrode pads 210 are disposed on the same side of the active surface of the semiconductor chip 200 corresponding to the electrical connection pads 110, and the electrode pads 210 are exposed to the space above the semiconductor wafer 200. That is, the semiconductor wafer 200 of the upper layer does not block the electrode pads 210 of the semiconductor wafer of the lower layer. At this time, the electrical connection pads 110 are disposed on the wafer carrier 100 where the semiconductor wafer 200 is not bonded. The electrode pads 210 are disposed on a region of the semiconductor wafer 200 on which the other semiconductor wafers 200 are not stacked.
並且，各該半導體晶片200鄰近該些電極墊210之外露作用面201之側邊形成有對應該些電極墊210之複數凹槽220，換言之，該些凹槽220係形成於各該半導體晶片200之外露作用面201之長邊之側邊，且該些凹槽220係彼此鄰近地線性排列但不連通。In addition, each of the semiconductor wafers 200 is formed with a plurality of recesses 220 corresponding to the electrode pads 210 adjacent to the sides of the exposed surface 201 of the electrode pads 210. In other words, the recesses 220 are formed on the respective semiconductor wafers 200. The sides of the long sides of the exposed surface 201 are exposed, and the grooves 220 are linearly arranged adjacent to each other but are not in communication.
於一實施例中，如第7圖所示，該凹槽220形成在該半導體晶片200之側邊並貫穿該半導體晶片200，在此處，其側向斷面之形狀係如圖所示為梯形，而於另一實施例中，如第8圖所示，該凹槽220形成在半導體晶片200之邊緣並貫穿該半導體晶片200，在此處，其側向斷面之形狀係如圖所示為矩形，然而，該凹槽220之側向斷面之形狀並不會被加以限制，其亦可為多邊形、圓弧形、波浪形等或其組合。In an embodiment, as shown in FIG. 7, the recess 220 is formed on the side of the semiconductor wafer 200 and penetrates the semiconductor wafer 200. Here, the shape of the lateral cross section is as shown in the figure. Trapezoidal, and in another embodiment, as shown in FIG. 8, the recess 220 is formed at the edge of the semiconductor wafer 200 and extends through the semiconductor wafer 200, where the shape of the lateral cross section is as shown in the figure. It is shown as a rectangle. However, the shape of the lateral section of the groove 220 is not limited, and may be a polygon, a circular arc, a wave, or the like, or a combination thereof.
進一步詳細說明該絕緣膠300的設定位置及結構型態，該絕緣膠300介於該晶片承載件100與該堆疊於晶片承載件100上之半導體晶片200之間，亦即，該絕緣膠300黏接於該晶片承載件100及疊接在該晶片承載件100的該半導體晶片200之間，其用以將該晶片承載件100及該底部半導體晶片200相互黏合而固定構形，並加以阻斷其之間的電性連接，且同時，該絕緣膠300介於任二相疊接的該半導體晶片200之間，亦即，該絕緣膠300復黏接於任二相疊接的該半導體晶片200之間，其用以將該些半導體晶片200相互黏合而固定構形，並加以阻斷其之間的電性連接。The position and the configuration of the insulating adhesive 300 are further described in detail. The insulating adhesive 300 is interposed between the wafer carrier 100 and the semiconductor wafer 200 stacked on the wafer carrier 100, that is, the insulating adhesive 300 is adhered. Connected between the wafer carrier 100 and the semiconductor wafer 200 stacked on the wafer carrier 100, the wafer carrier 100 and the bottom semiconductor wafer 200 are bonded to each other to be fixed and blocked. The electrical connection between the semiconductor wafers 200 and the two layers of the semiconductor wafer 200 are overlapped, that is, the insulating adhesive 300 is bonded to the semiconductor wafers of any two phases. Between 200, the semiconductor wafers 200 are bonded to each other to fix the configuration, and the electrical connection therebetween is blocked.
此外，由於該晶片承載件100之表面不完全平整，令介於該晶片承載件100及該底部半導體晶片200之間的該絕緣膠300，其厚度需較厚，例如，25um，但不以此數值為限定，而介於任二相疊接的該半導體晶片200之間的絕緣膠300厚度相對上則可較薄，例如，10 um，但不以此數值為限定，此時，介於該晶片承載件100及疊接在該晶片承載件100上之該半導體晶片200之間之絕緣膠300厚度大於任二相疊接之該半導體晶片200之間之絕緣膠300厚度。In addition, since the surface of the wafer carrier 100 is not completely flat, the thickness of the insulating paste 300 between the wafer carrier 100 and the bottom semiconductor wafer 200 needs to be thick, for example, 25 um, but not The value is limited, and the thickness of the insulating paste 300 between any two of the semiconductor wafers 200 stacked may be relatively thin, for example, 10 um, but not limited by this value. The thickness of the insulating paste 300 between the wafer carrier 100 and the semiconductor wafer 200 stacked on the wafer carrier 100 is greater than the thickness of the insulating paste 300 between the semiconductor wafers 200 of any two phases.
該導電膠400係以點膠方式而電性連接該電性連接墊110及各該半導體晶片200上之對應該電性連接墊110之電極墊210，以藉由該導電膠400使該些半導體晶片200均電性連接該晶片承載件100。The conductive adhesive 400 is electrically connected to the electrical connection pads 110 and the electrode pads 210 of the respective semiconductor wafers 200 corresponding to the electrical connection pads 110 to make the semiconductors by the conductive adhesive 400. The wafer 200 is electrically connected to the wafer carrier 100.
其中，如第6圖及第7圖所示，各條導電膠400之可順流至對應該電極墊210之凹槽220中，使得任二相鄰之該導電膠400藉由該些凹槽220分別被加以導引，並藉由各該凹槽220槽壁阻擋同一晶片上之相鄰兩電極墊210之間的導電膠彼此連接，據此，從而在該半導體晶片200之邊緣處，避免該導電膠400發生因溢流黏接而導致其與電性連接其他電性連接墊110及電極墊210電性連接之短路情形。Wherein, as shown in FIG. 6 and FIG. 7 , each of the conductive adhesives 400 can flow into the recesses 220 corresponding to the electrode pads 210 , so that any two adjacent conductive pastes 400 pass through the recesses 220 . They are respectively guided and connected to each other by the conductive glue between the adjacent two electrode pads 210 on the same wafer by the groove walls of the grooves 220, thereby avoiding the edge of the semiconductor wafer 200. The conductive adhesive 400 is short-circuited due to overflow bonding, which is electrically connected to the other electrical connection pads 110 and the electrode pads 210.
具體而言，以此實施例作說明，任二相鄰之導電膠400彼此不會電性連接，其係藉由該些凹槽220容納部份導電膠400而不會在該半導體晶片200之邊緣處互相溢流黏接，據此，限制點膠時之物理溢流現象，能有效防止呈半液態狀時之導電膠400在各該半導體晶片200之邊緣處溢流，因而解決先前技術中之晶片短路問題，如此，不會造成產品報廢且無須進行重新點膠作業，以此而能提升產品之良率及可靠度。Specifically, in this embodiment, any two adjacent conductive pastes 400 are not electrically connected to each other, and the recesses 220 receive a portion of the conductive paste 400 without being in the semiconductor wafer 200. The edges are overlapped and adhered to each other, thereby limiting the physical overflow phenomenon during dispensing, and the conductive paste 400 in the semi-liquid state can be effectively prevented from overflowing at the edges of the respective semiconductor wafers 200, thereby solving the prior art. The problem of short-circuiting the wafer, so that the product will not be scrapped and no need to re-dispense, thereby improving the yield and reliability of the product.
此外，該封裝樹脂500係覆蓋該晶片承載件100、半導體晶片200、絕緣膠300及導電膠400，俾以該封裝樹脂700具有的保護功能和對外的整體絕緣功效，提升安全性，其中，覆蓋方式可藉由封裝模壓方式而達成。In addition, the encapsulating resin 500 covers the wafer carrier 100, the semiconductor wafer 200, the insulating adhesive 300, and the conductive adhesive 400, thereby improving the safety by the protective function of the encapsulating resin 700 and the external overall insulating effect, wherein the covering is improved. The method can be achieved by a package molding method.
再者，於一種實施樣態中，如第8圖所示，係顯示具有第5圖所示之凹槽220半導體晶片200彼此以階梯狀方式堆疊，因此，形成單邊懸空之階梯狀多晶片堆疊結構。Furthermore, in one embodiment, as shown in FIG. 8, the semiconductor wafers 200 having the recesses 220 shown in FIG. 5 are stacked in a stepped manner with each other, thereby forming a stepped multi-chip floating on one side. Stack structure.
於另一種實施樣態中，如第9圖所示，該些半導體晶片200彼此以鋸齒狀方式堆疊，然，並非限制於此些實施樣態，堆疊方式亦可為階梯狀方式及鋸齒狀方式之搭配混合。In another embodiment, as shown in FIG. 9, the semiconductor wafers 200 are stacked in a zigzag manner, but the method is not limited to the embodiments, and the stacking manner may be a stepped manner or a zigzag manner. Mix and match.
綜上所述，相較於習知技術，本發明之用於多晶片堆疊封裝之晶片及多晶片堆疊封裝結構，任二相鄰之導電膠400係藉由該些凹槽220導引導電膠400，並阻擋同一晶片上之相鄰兩電極墊210之間的導電膠400彼此連接，從而在該半導體晶片200之邊緣處，避免發生因溢流黏接所導致之電性短路，因而解決先前技術中之晶片短路問題，如此，不會造成產品報廢且無須進行重新點膠作業，以此而能提升產品之良率及可靠度。In summary, in the wafer and multi-wafer stack package structure of the multi-wafer stack package of the present invention, any two adjacent conductive pastes 400 guide the conductive paste by the grooves 220. 400, and blocking the conductive paste 400 between the adjacent two electrode pads 210 on the same wafer to be connected to each other, thereby avoiding an electrical short circuit caused by overflow bonding at the edge of the semiconductor wafer 200, thus solving the previous The short-circuit problem of the wafer in the technology, so that the product will not be scrapped and no need to re-dispense, thereby improving the yield and reliability of the product.
上述實施例僅例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修飾與改變。因此，本發明之權利保護範圍，應如後述之申請專利範圍所列。The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.
2．．．層狀本體2. . . Layered body
10．．．基板10. . . Substrate
11．．．電性連接墊11. . . Electrical connection pad
20．．．晶片20. . . Wafer
21．．．電極墊twenty one. . . Electrode pad
30．．．絕緣膠30. . . Insulating glue
40．．．導電膠40. . . Conductive plastic
50．．．封膠50. . . Plastic closures
100．．．晶片承載件100. . . Wafer carrier
110．．．電性連接墊110. . . Electrical connection pad
200．．．半導體晶片200. . . Semiconductor wafer
201．．．作用面201. . . Action surface
202．．．非作用面202. . . Non-active surface
203．．．堆疊區203. . . Stacking area
204．．．非堆疊區204. . . Non-stacking area
210．．．電極墊210. . . Electrode pad
220．．．凹槽220. . . Groove
300．．．絕緣膠300. . . Insulating glue
400．．．導電膠400. . . Conductive plastic
500．．．封裝樹脂500. . . Encapsulation resin
第1圖係為習知晶片封裝結構之局部俯視圖；Figure 1 is a partial plan view of a conventional chip package structure;
第2圖係為習知晶片封裝結構之局部側剖視圖；Figure 2 is a partial side cross-sectional view of a conventional chip package structure;
第3圖係為本發明之用於多晶片堆疊封裝之晶片之局部俯視圖；3 is a partial plan view of a wafer for a multi-wafer stacked package of the present invention;
第4圖係為本發明之用於多晶片堆疊封裝之晶片之一實施例之局部側剖視圖；4 is a partial side cross-sectional view showing an embodiment of a wafer for a multi-wafer stacked package of the present invention;
第5圖係為本發明之用於多晶片堆疊封裝之晶片之另一實施例之局部側剖視圖；Figure 5 is a partial side cross-sectional view showing another embodiment of the wafer for a multi-wafer stacked package of the present invention;
第6圖係為本發明之多晶片堆疊封裝結構之局部俯視圖；Figure 6 is a partial plan view of the multi-wafer stacked package structure of the present invention;
第7圖係為本發明之多晶片堆疊封裝結構之一實施例之局部側剖視圖；Figure 7 is a partial side cross-sectional view showing an embodiment of the multi-wafer stacked package structure of the present invention;
第8圖係為本發明之多晶片堆疊封裝結構之另一實施例之局部側剖視圖；以及Figure 8 is a partial side cross-sectional view showing another embodiment of the multi-wafer stacked package structure of the present invention;
第9圖係為本發明之多晶片堆疊封裝結構之再一實施例之局部側剖視圖。Figure 9 is a partial side cross-sectional view showing still another embodiment of the multi-wafer stacked package structure of the present invention.
100．．．晶片承載件100. . . Wafer carrier
110．．．電性連接墊110. . . Electrical connection pad
200．．．半導體晶片200. . . Semiconductor wafer
201．．．作用面201. . . Action surface
202．．．非作用面202. . . Non-active surface
210．．．電極墊210. . . Electrode pad
220．．．凹槽220. . . Groove
300．．．絕緣膠300. . . Insulating glue
400．．．導電膠400. . . Conductive plastic
500．．．封裝樹脂500. . . Encapsulation resin
Claims (13)
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| TW099139656A TWI426593B (en) | 2010-11-18 | 2010-11-18 | Chip for use with multi-chip stack package and its stack package structure |
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| TWI426593B true TWI426593B (en) | 2014-02-11 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009027067A (en) * | 2007-07-23 | 2009-02-05 | Alps Electric Co Ltd | Manufacturing method of semiconductor device, and semiconductor device |
| US20090068790A1 (en) * | 2007-09-07 | 2009-03-12 | Vertical Circuits, Inc. | Electrical Interconnect Formed by Pulsed Dispense |
| US20090230528A1 (en) * | 2008-03-12 | 2009-09-17 | Vertical Circuits, Inc. | Support Mounted Electrically Interconnected Die Assembly |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009027067A (en) * | 2007-07-23 | 2009-02-05 | Alps Electric Co Ltd | Manufacturing method of semiconductor device, and semiconductor device |
| US20090068790A1 (en) * | 2007-09-07 | 2009-03-12 | Vertical Circuits, Inc. | Electrical Interconnect Formed by Pulsed Dispense |
| US20090230528A1 (en) * | 2008-03-12 | 2009-09-17 | Vertical Circuits, Inc. | Support Mounted Electrically Interconnected Die Assembly |
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| TW201222770A (en) | 2012-06-01 |
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