TWI480988B - Plate structure for package, package substrate, semiconductor package and fabrication method thereof - Google Patents

Description

Package substrate plate structure, package substrate, semiconductor package and manufacturing method thereof

The present invention relates to a semiconductor package and a method of fabricating the same. More specifically, the present invention is a semiconductor package having a recess on the periphery of the package substrate and having an overflow prevention material, and a method of fabricating the same.

Nowadays, with the trend of technology development, electronic products tend to be light and thin, making the space application of semiconductor packages as the core components of electronic products more important. Therefore, it is still necessary to continuously improve and overcome the process technology of semiconductor packages. In order to meet the trend of light and thin modern technology products.

The semiconductor package is packaged on a package, and a batch-type process is used, that is, a die-attach and an underfill of a plurality of semiconductor wafers are usually performed on the entire surface of the package substrate. ), and finally the singulation step. However, because the distance between any two adjacent semiconductor wafers is too small, when the underfill is filled, the underfill material is likely to be improperly overflowed to the periphery, which affects the yield of the finished product.

For a method of improving the improper overflow of the underfill material, please refer to U.S. Patent Nos. 7,927,925 and 8,008,073, or as shown in Fig. 1, which are respectively coated on the bottom filling material region 102a of the top surface 102 of the package substrate 10 and its periphery. The hydrophilic particulate powder and the hydrophobic particulate powder have hydrophilicity and hydrophobicity respectively with the underfill material distribution region 102a and its periphery to reduce the improper overflow of the underfill material 12 to the periphery of the underfill material distribution region 102a.

However, the foregoing method needs to be carried out according to different package substrates or semiconductor wafers. With different hydrophilic or hydrophobic particle powders, the complexity of the packaging process is increased, and this method cannot completely solve the problem of improper overflow of the underfill material.

Therefore, how to overcome the above problems of the prior art is an important issue.

In order to solve the problems of the above-mentioned prior art, the present invention discloses a semiconductor package, comprising: a package substrate having opposite top and bottom surfaces, and an electrical circuit is formed on the top surface, and the top is formed on the top surface A recess is formed on the periphery of the surface; at least one semiconductor wafer is electrically connected to the top surface of the package substrate by a flip chip; and an underfill material is formed between the package substrate and the semiconductor wafer.

The present invention further provides a semiconductor package comprising: a package substrate having opposite top and bottom surfaces, wherein the top surface is formed with an electrical line and a solder resist layer covering the electrical line, the substrate periphery And forming a recess; at least one semiconductor wafer electrically connected to a top surface of the package substrate; and an underfill material formed between the package substrate and the semiconductor wafer.

The present invention provides a package substrate plate structure, comprising: a plurality of arrays of package substrates; and a connection portion for connecting the package substrates, and the connection portion is between the two adjacent package substrates A cutting line is defined, and a recess is formed at each of the cutting lines.

The present invention further provides a package substrate having opposite top and bottom surfaces, and the periphery of the top surface has a recess and is disposed on the package substrate An electrical circuit is formed on the top surface.

The invention further provides a method for fabricating a semiconductor package, comprising: providing a package structure of the package substrate, flip-chip bonding a plurality of semiconductor wafers onto the package substrate; forming an underfill material between each of the semiconductor wafers and the package substrate And cutting the sheet along the cutting line to divide into a plurality of semiconductor packages.

In the above method for fabricating a semiconductor package, a solder resist layer is formed on one surface of the board, and the solder resist layer is provided with a solder resist layer recess along the cutting line of the board to be recessed by the solder resist layer. The groove serves as the recess.

In the above method of fabricating a semiconductor package, the recess is formed by mechanical cutting, laser peeling or chemical etching. In addition, the underfill material is filled between the semiconductor wafer and the package substrate by dispensing. Further, the material forming the underfill material is an epoxy resin or an epoxy resin doped with a filler.

In the above method of fabricating a semiconductor package, each of the semiconductor packages includes a semiconductor wafer or a plurality of the semiconductor wafers, and when the semiconductor wafer is plural, the recesses extend to between adjacent semiconductor wafers.

In the foregoing semiconductor package and the method of manufacturing the same, the top surface of the package substrate is formed with a plurality of first electrical contact pads electrically connected to the bumps on the semiconductor wafer, and the bottom surface of the package substrate has a plurality of second electrical contacts a pad, and the second electrical contact pads have solder balls thereon. In addition, the package substrate has a plurality of conductive holes, and the conductive holes are electrically connected to the top surface and the bottom surface.

According to the above, the present invention forms a concave portion at the cutting portion on the sheet, so that the overflow portion of the underfill material is introduced into the concave portion, and the concave portion is sucked by the concave portion. Receiving a portion of the overflow underfill material to avoid improper overflow of the underfill material, and the present invention can thereby reduce the distance between the semiconductor wafer and the semiconductor wafer, thereby further improving the use rate of the package substrate, and the present invention has no conventional technology. Restrictions need to be designed for different package substrates or semiconductor wafers.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms used in the specification, such as "upper", "top", "bottom" and "a", are used for convenience of description and are not intended to limit the scope of the invention. Changes or adjustments to a relationship are considered to be within the scope of the invention, without departing from the scope of the invention.

First embodiment

The first embodiment of the semiconductor package of the present invention and a method of manufacturing the same will be described in detail below in conjunction with FIGS. 2A to 2F.

As shown in FIG. 2A, which is a top view of a semiconductor package of the present invention, a board 20' having a plurality of package substrates 20 is provided. A cutting line T (shown by a broken line) is defined between the two adjacent package substrates 20, wherein the cutting line T may be linear, polygonal, zigzag or curved.

Referring to FIG. 2B , which is a cross-sectional view taken along line 2A of FIG. 2A , the board 20 ′ is connected to each of the package substrates 20 by a connecting portion 21 , and The connecting portion 21 is defined in the figure between the two adjacent package substrates 20 and defines the cutting line T. The package substrate 20 has an opposite top surface 202 and a bottom surface 204. The top surface 202 of the package substrate 20 Forming a plurality of first electrical contact pads 22a and second electrical contact pads 22b with the bottom surface 204, respectively, and cutting the plate 20' by mechanical cutting, laser ablation (Laser Ablation) or chemical etching. The concave portion 23 is formed at the line T, but the manner of forming the concave portion 23 is not limited thereto, and the width of the concave portion 23 is smaller than or equal to the width of the cutting line T (not shown). In addition, the cross-sectional shape of the concave portion 23 is a square, a rectangle, a rectangle, or a semi-circular arc shape (not shown), but is not limited thereto. In addition, the package substrate 20 has a plurality of conductive holes (not shown), and the conductive holes are electrically connected to the top surface 202 and the bottom surface 204, and the material of the package substrate 20 is a laminate substrate. A substrate obtained by polymerizing Bismaleimide Triazine (BT) or a substrate containing Ajinomoto build-up film (ABF).

As shown in FIG. 2C, the semiconductor wafer 26 is electrically connected to each of the package substrates 20, and the bumps 24 are formed on the semiconductor wafer 26 to electrically connect the semiconductor wafers 26. The first electrical contact pad 22a is waitable.

As shown in FIG. 2D, the process is continued from the process of FIG. 2C, and a material such as an epoxy resin or an epoxy-containing mixed filler (Filler) is formed on each of the package substrates 20 by means of dispensing. 28, and the bottom filling material 28 is filled between the semiconductor wafer 26 and the package substrate 20, and the overflow portion of the underfill material 28 flows into the concave portion 23 along the edge of the concave portion 23, that is, the concave portion 23 can absorb the portion The underfill material 28 is overflowed. Therefore, the underfill material 28 does not improperly overflow to the periphery, and affects the overall semiconductor packaging process. In addition, the depth of the recess 23 is greater than or equal to 2 of the maximum particle size of the filler. The filler is cerium oxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ ) particles.

As shown in FIG. 2E, the process of continuing from the 2D drawing can be performed along the cutting line T according to the process requirements on the semiconductor package to divide into a plurality of packages having the semiconductor wafer 26. And soldering the solder ball 24' to the second electrical contact pad 22b of the bottom surface 204 of the package substrate 20; or, as shown in FIG. 2F, dividing into a plurality of packages having the plurality of semiconductor wafers 26 The recesses 23 are spaced apart from each other between the semiconductor wafers 26; or, as shown in the second and second FIGS. 2F' and 2F", the recesses 23 are not provided between the packages of the semiconductor wafers 26. Further, in the 2F In the figure, the underfill materials 28 between the packages of the semiconductor wafers 26 may be separated from each other and not connected; or the underfill materials 28 between the packages of the semiconductor wafers 26 may be connected to each other, such as the 2F. As shown, it can be configured according to the process requirements on the semiconductor package.

Alternatively, in another implementation method, as shown in FIGS. 2D' and 2E', the encapsulant 29 may be molded on the package substrate 20, The semiconductor wafer 26 and the underfill material 28 are coated such that the semiconductor wafer 26 and the underfill material 28 are not in contact with the external environment, and the sheet 20' is cut along the cutting line T.

Second embodiment

3A to 3G are schematic cross-sectional views showing a semiconductor package of the present invention and a second embodiment thereof.

As shown in FIG. 3A, a board 30' having a plurality of package substrates 30 is provided, and each of the package substrates 30 is connected by a connecting portion 31, and the connecting portion 31 is shown in the figure to be adjacent to the package substrate 30. A portion of the portion between the top surface 302 and the bottom surface 304 of the package substrate 30 is formed with a plurality of first electrical contact pads 32a and second electrical contact pads 32b, respectively. And forming a solder resist layer 35 on the top surface 302 of the package substrate 30 and the first electrical contact pads 32a, and exposing a portion of the first electrical contact pads 32a, and the top surface 302 of the package substrate 30 An electrical circuit (not shown) can be formed in the upper layer. In addition, the package substrate 30 has a plurality of conductive holes (not shown), and the conductive holes are electrically connected to the top surface 302 and the bottom surface 304.

As shown in FIG. 3B, the process is continued from the process of FIG. 3A, and a solder resist layer is formed on the solder resist layer 35 by mechanical cutting, laser stripping or chemical etching along the cutting line T of the sheet 30'. The recess 352 is formed by the solder resist layer recess 352 as a recess 33, wherein the cross-sectional shape of the recess 33 is square, rectangular, rectangular or semi-circular (not shown), but not limited thereto. The width of the recess 33 is greater than the width of the cutting line T (not shown).

As shown in Figure 3C, the process is continued from the process of Figure 3B. The semiconductor substrate 36 is electrically connected to the mounting substrate 30, and bumps 34 are formed on the semiconductor wafer 36 to electrically connect the first electrical contact pads 32a.

As shown in FIG. 3D, the process is continued from the process of FIG. 3C, and the underfill material 38 is formed on the package substrate 30 by dispensing as shown in FIG. 2D, and the underfill material 38 is filled into the semiconductor. The wafer 36 is interposed between the wafer 36 and the package substrate 30, and the overflow portion of the underfill material 38 flows into the recess 33 along the edge of the recess 33 to absorb the partially overflowed underfill material 38.

It is to be noted that the semiconductor wafer 36 can be disposed on the package substrate 30 in a non-centered manner, for example, slightly offset to the right, so that a large space is exposed on the left side to facilitate the dispensing of the semiconductor wafer 36 from the semiconductor wafer 36. The filling step of the underfill material 38 is performed on the left side, but it will be understood by those of ordinary skill in the art to which the present invention pertains, and therefore will not be described or illustrated herein.

As shown in FIG. 3E, the process is continued from the process of FIG. 3D, and is cut into a plurality of semiconductor packages having the semiconductor wafer 36, but may be divided into a plurality of semiconductor wafers 36 as shown in FIG. 3F. The semiconductor package is spaced apart from each of the semiconductor wafers 36 by a recess 33 having a depth equal to the thickness of the solder resist layer 35, and is not limited to the above. Solder balls 34' may be attached to the second electrical contact pads 32b of the bottom surface 304 of the package substrate 30.

Alternatively, in another embodiment, as shown in FIG. 3E′, the depth of the recess 33 may be made smaller than the thickness of the solder resist layer 35; or as shown in FIG. 3E”, the depth of the recess 33 may be greater than The thickness of the solder layer 35.

Alternatively, in another implementation method, as shown in FIG. 3F', the depth of the recess 33 between the semiconductor packages of each of the semiconductor wafers 36 may be made smaller than the thickness of the solder resist layer 35; or as shown in FIG. 3F" It is shown that the depth of the recess 33 is greater than the thickness of the solder resist layer 35, and the opened recess 33 can absorb the partially overflowed underfill material 38.

As shown in FIG. 3G, the semiconductor package having a plurality of the semiconductor wafers 36, for example, two semiconductor packages, is cut into a plurality of semiconductor packages 36, and the recesses 33 are formed on the sides of the semiconductor wafers 36. The recess 33 is not disposed between the semiconductor wafers 36, and the depth of the recess 33 on the side of the semiconductor package of each of the semiconductor wafers 36 is equal to the thickness of the solder resist 35.

Alternatively, in another embodiment, as shown in FIG. 3G', the depth of the recess 33 of the side of the semiconductor package of each of the semiconductor wafers 36 may be smaller than the thickness of the solder resist layer 35; or as the 3G" As shown in the figure, the depth of the recess 33 is made larger than the thickness of the solder resist layer 35, and the difference from the 3F is that there are no recesses in the two adjacent semiconductor wafers 36, but the semiconductor package of each of the semiconductor wafers 36. The side of the piece has a recess 33 that absorbs a portion of the underfill material 38 that overflows.

Therefore, according to the above process, the present invention can form the concave portion so that the groove can absorb the overflow portion of the underfill material, thereby avoiding the problem of improper overflow of the underfill material, and further shortening between the semiconductor wafers. The spacing is set to increase the usage of the package substrate. In addition, the recessed portion exposes the package substrate or does not expose the package substrate, but is not limited thereto, and the recess portion absorbs the portion overflowed by the underfill material.

In more detail, the cutting line T is used to perform accurate proof cutting in the groove, thereby avoiding structural damage or dimensional error of the semiconductor package during cutting.

The present invention provides a package substrate structure, such as FIGS. 2A and 2B, which includes a package array 20 of a plurality of arrays, and each of the package substrates 20 is connected by a connection portion 21, and the connection portion 21 is adjacent to the two. A portion between the package substrates 20 defines a cutting line T, and a recess 23 is formed at each of the cutting lines T.

The present invention further provides a semiconductor package having a top surface 202 and a bottom surface 204 on the package substrate 20, and an electrical circuit is formed on the top surface 202, and a recess 23 is formed on the periphery of the top surface 202, and the package is formed in the package. At least one semiconductor wafer 26 is electrically connected to the top surface 202 of the substrate 20, and the cross-sectional shape of the recess 23 is square, rectangular, rectangular or semi-circular, and the package substrate 20 and the semiconductor wafer 26 are The underfill and the recess 23 are formed with a material such as an underfill material 28 containing an epoxy resin or an epoxy-containing mixed filler. In addition, the semiconductor package may have a plurality of the semiconductor wafers 26, and the recesses 23 are spaced apart between the semiconductor wafers 26.

According to the foregoing semiconductor package, the package substrate 20 has an opposite top surface 202 and a bottom surface 204, and the top surface 202 of the package substrate has a recess 23 on the periphery thereof, and a plurality of first electrodes are formed on the top surface 202 of the package substrate 20. The semiconductor wafer 26 is electrically connected to the top surface 202 of the package substrate 20, and the semiconductor wafer 26 is formed with a plurality of bumps 24 on the top surface 202 of the package substrate 20. More in detail, The plurality of second electrical contact pads 22b of the bottom surface 204 of the package substrate 20 can be soldered to the solder balls 24' for electrical connection with the outside. Further, the package substrate 20 is a laminate substrate, a substrate obtained by polymerizing Bismaleimide Triazine (BT), or a substrate containing an Ajinomoto build up film (ABF). In addition, the package substrate 20 has a plurality of conductive holes (not shown) and the conductive holes are electrically connected to the top surface 202 and the bottom surface 204. The underfill material 28 is formed between the package substrate 20 and the semiconductor wafer 26.

The present invention provides a package substrate having opposing top and bottom surfaces 202 and 204, and a peripheral portion of the top surface 202 having a recess 23 and an electrical circuit formed on the top surface 202 of the package substrate 20.

According to the foregoing package substrate, a solder resist layer 35 is formed on the top surface 302 of the package substrate 30, and the solder resist layer 35 has a solder resist layer recess 352 to serve as the recess 33 by the solder resist layer recess 352. .

The present invention further provides another semiconductor package, comprising: a package substrate 30 having an opposite top surface 302 and a bottom surface 304, and the top surface 302 is formed with an electrical line and a solder resist layer covering the electrical line. 35. The periphery of the package substrate 30 is formed with a recess 33 for exposing the top surface 302. The at least one semiconductor chip 36 is electrically connected to the top surface 302 of the package substrate 30 by a flip chip, and forms a bottom. A charge material 38 is between the package substrate 30 and the semiconductor wafers 36.

Moreover, the solder resist layer 35 is provided with a solder resist layer recess 352 along the cutting line T of the sheet 30', so that the solder resist layer recess 352 serves as the recess portion 33, and the cross-sectional shape of the recess portion 33 is Square, rectangle, rectangle or semi-circular arc Forming a plurality of first electrical contact pads 32a on the top surface 302 of the package substrate, and electrically connecting the semiconductor wafers 36 on the top surface 302 of the package substrate 30, and on the top surface of the package substrate 30 302 is formed with a plurality of semiconductor wafers 36 having bumps 34. In more detail, the plurality of second electrical contact pads 32b of the bottom surface 304 of the package substrate 30 can be soldered to the solder balls 34' for electrical connection with the outside.

In addition, an underfill material 38 is formed between the semiconductor wafer 36 and the package substrate 30 and the recess 33, and the underfill material 38 is made of an epoxy resin or an epoxy resin mixed filler. It is a layer of cerium oxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ ). Moreover, the package substrate 30 has a plurality of conductive holes (not shown) and the conductive holes are electrically connected to the top surface 302 and the bottom surface 304. More specifically, the width of the recess is less than, greater than or equal to the twist of the cutting blade, and the depth of the recess 33 is less than, greater than or equal to the thickness of the solder resist layer.

In summary, the semiconductor package of the present invention and the method for manufacturing the same are mainly to form a concave portion on the periphery of the package substrate such that the overflow portion of the underfill material flows into the concave portion, that is, the concave portion absorbs the partially overflowed bottom. The material is filled to avoid adverse effects between the semiconductor wafer and the semiconductor wafer due to improper overflow, so the invention can effectively solve the problem of improper overflow of the underfill material, thereby improving the reliability of the product, and The material does not improperly overflow to the periphery, so the spacing between the semiconductor wafers can be reduced, thereby saving the area of the package substrate and increasing the utilization rate of the package substrate.

The above-described embodiments are merely illustrative of the effects of the present invention and are not intended to limit the present invention, and anyone skilled in the art can Modifications and variations of the above-described embodiments are made in the spirit and scope of the invention. In addition, the number of elements in the above-described embodiments is merely illustrative and is not intended to limit the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10, 20, 30‧‧‧ package substrate

102, 202, 302‧‧‧ top surface

102a‧‧‧Bottom filling material distribution area

12‧‧‧ bottom material

204, 304‧‧‧ bottom surface

20’, 30’‧‧‧ plates

21, 31‧‧‧ Linkage Department

22a, 32a‧‧‧ first electrical contact pads

22b, 32b‧‧‧second electrical contact pads

23, 33‧‧‧ recess

24, 34‧‧‧Bumps

24', 34'‧‧‧ solder balls

26, 36‧‧‧ semiconductor wafer

28, 38‧‧‧ bottom material

29‧‧‧Package colloid

35‧‧‧ solder mask

352‧‧‧solder layer groove

T‧‧‧ cutting line

1 is a schematic cross-sectional view showing a manner of improving the improper overflow of an underfill material in U.S. Patent Nos. 7,079,925 and 8,008,073; the second embodiment of the present invention is a semiconductor package of the present invention and a method for fabricating the same 2A is a plan view, 2D' and 2E' are respectively another implementation method of 2D and 2E, and 2F' and 2F" are other embodiments of FIG. 2F; And FIGS. 3A to 3G are schematic cross-sectional views showing a second embodiment of the semiconductor package of the present invention and a method of fabricating the same, and FIGS. 3E' and 3E' are diagrams of other embodiments of FIG. 3E, 3F' and 3F" The drawings are other embodiments of the 3F diagram, the 3F' and 3F" diagrams are other implementations of the 3F diagram, and the 3G' and 3G" diagrams are other implementations of the 3G diagram.

20‧‧‧Package substrate

202‧‧‧ top surface

204‧‧‧ bottom surface

22a‧‧‧First electrical contact pads

22b‧‧‧Second electrical contact pads

23‧‧‧ recess

24‧‧‧Bumps

24'‧‧‧ solder balls

26‧‧‧Semiconductor wafer

28‧‧‧ bottom material

Claims (15)

A semiconductor package comprising: a package substrate having opposite top and bottom surfaces, wherein an electrical circuit is formed on the top surface, and a recess is formed on a periphery of the top surface; at least one semiconductor wafer is The flip chip is electrically connected to the top surface of the package substrate; and the underfill material is formed between the package substrate and the semiconductor wafer. A semiconductor package includes: a package substrate having opposite top and bottom surfaces, wherein the top surface is formed with an electrical line and a solder resist layer covering the electrical line, and the periphery of the package substrate is formed a recessed portion; at least one semiconductor wafer electrically connected to the top surface of the package substrate; and an underfill material formed between the package substrate and the semiconductor wafer. The semiconductor package of claim 1 or 2, wherein a portion of the underfill material is formed in the recess. The semiconductor package of claim 1 or 2, wherein the material forming the underfill material is an epoxy resin or an epoxy resin doped with a filler. The semiconductor package of claim 4, wherein the recess has a depth greater than or equal to a maximum of the filler particle size. Doubled. The semiconductor package of claim 1 or 2, wherein the top surface of the package substrate has a plurality of first electrical contact pads, and the semiconductor wafer and the first electrical contact pads have Bump. A package substrate structure includes: a plurality of arrays of package substrates; and a connection portion for connecting the package substrates, wherein the connection portion defines a cutting line between any two adjacent package substrates And a recess is formed at each of the cutting lines. The package substrate sheet structure according to claim 7, wherein a solder resist layer is formed on each of the package substrates, and the solder resist layer has a solder resist layer recess to be made by the solder resist layer recess For this recess. A package substrate has opposite top and bottom surfaces, and a periphery of the top surface has a recess, and an electrical line is formed on a top surface of the package substrate. The package substrate of claim 9, wherein a solder resist layer is formed on a top surface of the package substrate, the solder resist layer having a solder resist layer recess to serve as the solder resist layer recess The recess. A method of fabricating a semiconductor package, comprising: providing a package substrate plate structure according to claim 7 of the patent application, flip-chip bonding a plurality of semiconductor wafers onto the package substrate; and each of the semiconductor wafer and the package substrate Forming an underfill material between; The sheet is cut along the recess to be divided into a plurality of semiconductor packages. The method of fabricating a semiconductor package according to claim 11, wherein a portion of the underfill material is formed in the recess. The method of fabricating a semiconductor package according to claim 11, wherein the recess is formed by mechanical cutting, laser ablation or chemical etching. The method of fabricating a semiconductor package according to claim 11, wherein the concave portion has a twist greater than, less than, or equal to a twist of the cutting blade for cutting the sheet. The method of manufacturing a semiconductor package according to claim 11, wherein the top surface of the plate has a solder resist layer, and the solder resist layer is provided with a solder resist groove along a cutting line of the plate. The recess of the solder resist layer is used as the recess.