JP2009027067A - Manufacturing method of semiconductor device, and semiconductor device - Google Patents

Manufacturing method of semiconductor device, and semiconductor device Download PDF

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JP2009027067A
JP2009027067A JP2007190570A JP2007190570A JP2009027067A JP 2009027067 A JP2009027067 A JP 2009027067A JP 2007190570 A JP2007190570 A JP 2007190570A JP 2007190570 A JP2007190570 A JP 2007190570A JP 2009027067 A JP2009027067 A JP 2009027067A
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semiconductor chip
wiring board
semiconductor
stacked
nth
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Shinji Murata
眞司 村田
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Alps Alpine Co Ltd
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Alps Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which can be made compact, and the semiconductor device. <P>SOLUTION: In the manufacturing method of the semiconductor device 1 according to the present invention, a wiring board 3 and three semiconductor chip 4 are stacked first so that a connection electrode 7 and a connection terminal 8 may be exposed. The connection electrode 7 and the connection terminal 8 are arranged on a straight line. Then, a thin film wiring 6 is linearly formed by sputtering. A mask (not shown) used for the sputtering has a stepped part or inclination part in a shape similar to that of a formation region (left linear stepped region) of the thin film wiring 6 formed with the wiring board 3 and three semiconductor chips 4 which are stacked shifting to the right, and also has a slit for thin film wiring formation at the stepped part or inclination part. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置の製造方法および半導体装置に係り、特に、メモリ基板に複数のメモリチップを積層実装してなるメモリーカードに好適に利用できる半導体装置の製造方法および半導体装置に関する。   The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly to a semiconductor device manufacturing method and a semiconductor device that can be suitably used for a memory card in which a plurality of memory chips are stacked and mounted on a memory substrate.

図１５は従来の半導体装置１０１の一例を示している。従来の半導体装置１０１は、図１５に示すように、半導体装置１０１の筐体１０２の内部に配設された配線板１０３の上面１０３ａに１個または複数個の半導体チップ１０４が積層されており、配線板１０３または半導体チップ１０４に形成された接続電極１０７または接続端子１０８をワイヤ１０６を用いたワイヤボンディングにより相互に接続して形成されていた（特許文献１を参照）。   FIG. 15 shows an example of a conventional semiconductor device 101. As shown in FIG. 15, the conventional semiconductor device 101 has one or more semiconductor chips 104 stacked on the upper surface 103 a of the wiring board 103 disposed inside the housing 102 of the semiconductor device 101. The connection electrodes 107 or the connection terminals 108 formed on the wiring board 103 or the semiconductor chip 104 are connected to each other by wire bonding using the wires 106 (see Patent Document 1).

特開２００５−２６８５３４号公報JP 2005-268534 A

しかしながら、接続電極１０７または接続端子１０８をワイヤボンディングより接続していたため、ワイヤボンディングに必要なスペース分だけ実装面積および実装体積が大きくなってしまい、半導体装置１０１の小型化が困難であるという問題があった。   However, since the connection electrode 107 or the connection terminal 108 is connected by wire bonding, a mounting area and a mounting volume are increased by a space necessary for wire bonding, and it is difficult to reduce the size of the semiconductor device 101. there were.

そこで、本発明はこれらの点に鑑みてなされたものであり、半導体装置を小型化することができる半導体装置の製造方法および半導体装置を提供することを本発明の目的としている。   Therefore, the present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device capable of downsizing the semiconductor device.

前述した目的を達成するため、本発明の半導体装置の製造方法は、その第１の態様として、上面に接続電極が形成された配線板の上面に第１の半導体チップを接続電極が露出するように積層する工程ａと、半導体チップを２個以上積層させる場合においては第（ｎ−１）の接続端子が上面に形成された第（ｎ−１）の半導体チップ（ｎ：２から半導体チップの積層合計枚数Ｎまでの間の任意の正の整数）の上面に第ｎの半導体チップを第（ｎ−１）の接続端子が露出するように積層させる１の積層工程をｎが２からＮまで順に行なう工程ｂと、第ｎの半導体チップの上面に形成された第ｎの接続端子を含むすべての接続端子および接続電極を接続させる薄膜配線と同形状のスリットが形成されたマスクを用いて配線板の上方から導電材料をスパッタまたは蒸着することにより薄膜配線を形成する工程ｃとを備えていることを特徴としている。   In order to achieve the above-described object, as a first aspect of the method for manufacturing a semiconductor device of the present invention, the first semiconductor chip is exposed on the upper surface of the wiring board on which the connection electrode is formed. And when stacking two or more semiconductor chips, the (n-1) th semiconductor chip (n: 2 to n) is formed with the (n-1) th connection terminal formed on the upper surface. 1 is a stacking process in which the nth semiconductor chip is stacked on the upper surface of any positive integer between N and the total number of stacked layers N so that the (n−1) th connection terminal is exposed. Wiring using step b, which is performed in order, and a mask in which slits having the same shape as the thin film wiring for connecting all the connection terminals including the nth connection terminals and the connection electrodes formed on the upper surface of the nth semiconductor chip are formed Remove conductive material from above the plate. Tsu it is characterized in that a step c for forming a thin film wiring by data or evaporation.

本発明の第１の態様の半導体装置の製造方法によれば、接続電極および全ての接続端子を接続する配線の接続としてワイヤボンディングの代わりに薄膜配線の形成を行なっているので、ワイヤボンディングに必要なスペース分だけ実装スペースを小さくすることができる。   According to the manufacturing method of the semiconductor device of the first aspect of the present invention, the thin film wiring is formed instead of the wire bonding as the connection of the wiring for connecting the connection electrode and all the connection terminals. As a result, the mounting space can be reduced by an appropriate amount of space.

本発明の第２の態様の半導体装置の製造方法は、第１の態様の半導体装置の製造方法において、配線板および半導体チップは、接着層を介して隣位する配線板または他の半導体チップに接着されており、接着層は、第（ｎ−１）の半導体チップもしくは配線板の上面から第ｎの半導体チップもしくは第１の半導体チップの上面の端部までの間において配線板の上方に面する方向に傾斜させた側面を有していることを特徴としている。   The method for manufacturing a semiconductor device according to a second aspect of the present invention is the method for manufacturing a semiconductor device according to the first aspect, wherein the wiring board and the semiconductor chip are connected to an adjacent wiring board or other semiconductor chip via an adhesive layer. The adhesive layer is bonded to the upper surface of the wiring board between the upper surface of the (n-1) th semiconductor chip or wiring board and the end of the upper surface of the nth semiconductor chip or first semiconductor chip. It is characterized by having a side surface that is inclined in the direction of the movement.

本発明の第２の態様の半導体装置の製造方法によれば、接着層の側面を傾斜させているので、配線板の上面および半導体チップの上面に薄膜配線を形成する際に接着層の側面にも同時に薄膜配線を形成することができる。   According to the method for manufacturing a semiconductor device of the second aspect of the present invention, since the side surface of the adhesive layer is inclined, the thin film wiring is formed on the side surface of the adhesive layer when the thin film wiring is formed on the upper surface of the wiring board and the upper surface of the semiconductor chip. At the same time, a thin film wiring can be formed.

本発明の第３の態様の半導体装置の製造方法は、第２の態様の半導体装置の製造方法において、すべての半導体チップは、それらをそれぞれ同一方向にずらして直線階段状に積層されており、接続電極およびすべての接続端子は、半導体チップの積層により生じた直線階段領域において直線上に配置されていることを特徴としている。   A method for manufacturing a semiconductor device according to a third aspect of the present invention is the method for manufacturing a semiconductor device according to the second aspect, wherein all the semiconductor chips are stacked in a linear staircase pattern by shifting them in the same direction. The connection electrodes and all the connection terminals are arranged on a straight line in a linear staircase region generated by stacking semiconductor chips.

本発明の第３の態様の半導体装置の製造方法によれば、半導体チップを同一方向以外の方向にそれぞれ積層するよりも、半導体チップの積層スペースを小さくすることができる。また、薄膜配線が直線状に形成されているので、薄膜配線の長さが最短になり、薄膜配線の電気的な損失を最小限に抑えることができる。   According to the semiconductor device manufacturing method of the third aspect of the present invention, the semiconductor chip stacking space can be made smaller than stacking the semiconductor chips in directions other than the same direction. In addition, since the thin film wiring is formed in a straight line, the length of the thin film wiring is minimized, and the electrical loss of the thin film wiring can be minimized.

本発明の第４の態様の半導体装置の製造方法は、第２または第３の態様の半導体装置の製造方法において、マスクは、最下層に積層された配線板から最上層に積層された第Ｎの半導体チップまでの間において配線板の上面、接着層の側面、第１の半導体チップの上面、接着層の側面、・・・、接着層の側面、第Ｎの半導体チップの上面の順に階段状に形成される薄膜配線の形成領域と同様の形状に形成された階段部にスリットを有していることを特徴としている。   The method for manufacturing a semiconductor device according to a fourth aspect of the present invention is the method for manufacturing a semiconductor device according to the second or third aspect, wherein the mask is an Nth layer stacked on the uppermost layer from a wiring board stacked on the lowermost layer. Steps in the order of the upper surface of the wiring board, the side surface of the adhesive layer, the upper surface of the first semiconductor chip, the side surface of the adhesive layer,..., The side surface of the adhesive layer, and the upper surface of the Nth semiconductor chip. The step portion formed in the same shape as the formation region of the thin film wiring formed in FIG.

本発明の第４の態様の半導体装置の製造方法によれば、薄膜配線の形成領域とマスクとのギャップが一定になるので、階段部のない平板状のマスクを用いて薄膜配線を形成した場合と比較して、形成精度の高い薄膜配線を形成することができる。   According to the method for manufacturing a semiconductor device of the fourth aspect of the present invention, since the gap between the thin film wiring forming region and the mask is constant, the thin film wiring is formed using a flat mask without a stepped portion. Compared with, thin film wiring with higher formation accuracy can be formed.

本発明の第５の態様の半導体装置の製造方法は、第３の態様の半導体装置の製造方法において、マスクは、最下層に積層された配線板から最上層に積層された第Ｎの半導体チップまでの間においてすべての半導体チップをそれぞれずらして積層させることにより半導体チップの全体に生じた傾斜と同程度の傾きをもって形成された傾斜部にスリットを有していることを特徴としている。   According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the third aspect of the method for manufacturing a semiconductor device, wherein the mask is an Nth semiconductor chip stacked on the uppermost layer from a wiring board stacked on the lowermost layer. In the meantime, all the semiconductor chips are stacked while being shifted from each other, and the slit is formed in the inclined portion formed with the same inclination as the inclination generated in the entire semiconductor chip.

本発明の第５の態様の半導体装置の製造方法によれば、薄膜配線の形成領域とマスクとのギャップが狭くなるので、傾斜部のない平板状のマスクを用いて薄膜配線を形成した場合と比較して、形成精度の高い薄膜配線を形成することができる。   According to the semiconductor device manufacturing method of the fifth aspect of the present invention, since the gap between the thin film wiring forming region and the mask is narrowed, the thin film wiring is formed using a flat mask without an inclined portion. In comparison, a thin film wiring with high formation accuracy can be formed.

また、本発明の半導体装置は、その第１の態様として、接続電極が上面に形成されている配線板と、配線板の上面に接続電極が露出するように積層されている第１の半導体チップと、半導体チップを２個以上積層させる場合においては第（ｎ−１）の接続端子が上面に形成された第（ｎ−１）の半導体チップ（ｎ：２から半導体チップの積層合計枚数Ｎまでの間の任意の正の整数）の上面に第（ｎ−１）の接続端子が露出するように積層されている第ｎの半導体チップと、配線板と第１の半導体チップとの間および第（ｎ−１）の半導体チップと第ｎの半導体チップとの間にそれぞれ介在しているとともに、第（ｎ−１）の半導体チップもしくは配線板の上面から第ｎの半導体チップもしくは第１の半導体チップの上面の端部までの間において配線板の上方に面する方向に傾斜させた側面を有している接着層と、導電材料をスパッタまたは蒸着することにより配線板の上面、接着層の側面、第１の半導体チップの上面、接着層の側面、・・・、接着層の側面、第Ｎの半導体チップの上面の順に連続して形成されており、第ｎの半導体チップの上面に形成された第ｎの接続端子を含むすべての接続端子および接続電極に接続している薄膜配線とを備えていることを特徴としている。   The semiconductor device according to the present invention includes, as a first aspect, a wiring board having connection electrodes formed on the upper surface, and a first semiconductor chip laminated so that the connection electrodes are exposed on the upper surface of the wiring board. In the case where two or more semiconductor chips are stacked, from the (n−1) th semiconductor chip (n: 2 to the total number N of stacked semiconductor chips) having the (n−1) th connection terminal formed on the upper surface. Between the wiring board and the first semiconductor chip, and between the first semiconductor chip and the nth semiconductor chip stacked so that the (n-1) th connection terminal is exposed on the upper surface of any positive integer between The nth semiconductor chip or the first semiconductor is interposed between the (n-1) semiconductor chip and the nth semiconductor chip, and from the upper surface of the (n-1) th semiconductor chip or the wiring board. Between the top edge of the chip An adhesive layer having a side surface inclined in a direction facing the upper side of the wiring board, and an upper surface of the wiring board, a side surface of the adhesive layer, an upper surface of the first semiconductor chip, and adhesion by sputtering or vapor-depositing a conductive material The side surfaces of the layers,..., The side surfaces of the adhesive layer, and the upper surface of the Nth semiconductor chip are sequentially formed, and all the layers including the nth connection terminals formed on the upper surface of the nth semiconductor chip are formed. And a thin film wiring connected to the connection terminal and the connection electrode.

本発明の第１の態様の半導体装置によれば、接続電極および全ての接続端子を接続する配線の接続としてワイヤボンディングの代わりに薄膜配線の形成を行なっているので、ワイヤボンディングに必要なスペース分だけ実装スペースを小さくすることができる。また、接着層の側面を傾斜させているので、配線板の上面および半導体チップの上面に薄膜配線を形成する際に接着層の側面も同時に薄膜配線を形成することができる。   According to the semiconductor device of the first aspect of the present invention, since the thin film wiring is formed instead of the wire bonding as the connection of the wiring for connecting the connection electrode and all the connection terminals, the space necessary for the wire bonding is obtained. Only the mounting space can be reduced. Further, since the side surface of the adhesive layer is inclined, the thin film wiring can be formed simultaneously on the side surface of the adhesive layer when the thin film wiring is formed on the upper surface of the wiring board and the upper surface of the semiconductor chip.

本発明の第２の態様の半導体装置は、第１の態様の半導体装置において、すべての半導体チップは、それらをそれぞれ同一方向にずらして直線階段状に積層されており、接続電極およびすべての接続端子は、半導体チップの積層により生じた直線階段領域において直線上に配置されていることを特徴としている。   A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein all the semiconductor chips are stacked in a linear step shape by shifting them in the same direction. The terminals are arranged on a straight line in a linear staircase region generated by stacking semiconductor chips.

本発明の第２の態様の半導体装置によれば、半導体チップを同一方向以外の方向にそれぞれ積層するよりも、半導体チップの積層スペースを小さくすることができる。また、薄膜配線が直線状に形成されているので、薄膜配線の長さが最短になり、薄膜配線の電気的な損失を最小限に抑えることができる。   According to the semiconductor device of the second aspect of the present invention, the stacking space of the semiconductor chips can be made smaller than stacking the semiconductor chips in directions other than the same direction. In addition, since the thin film wiring is formed in a straight line, the length of the thin film wiring is minimized, and the electrical loss of the thin film wiring can be minimized.

本発明の半導体装置の製造方法および半導体装置によれば、ワイヤボンディングに必要なスペースを除外した分だけ半導体装置の実装面積および実装体積を小さくすることができるので、半導体装置を小型化することができるという効果を奏する。   According to the method for manufacturing a semiconductor device and the semiconductor device of the present invention, the mounting area and the mounting volume of the semiconductor device can be reduced by the amount excluding the space necessary for wire bonding. There is an effect that can be done.

以下、図１から図１４を用いて、本発明の半導体装置およびその製造方法をその一実施形態により説明する。   Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to FIGS.

図１および図２は、本実施形態の半導体装置１を示している。本実施形態の半導体装置１は、図１および図２に示すように、樹脂製の筐体２の内部に、配線板３、半導体チップ４、接着層５および薄膜配線６を備えている。   1 and 2 show a semiconductor device 1 of this embodiment. As shown in FIGS. 1 and 2, the semiconductor device 1 of this embodiment includes a wiring board 3, a semiconductor chip 4, an adhesive layer 5, and a thin film wiring 6 inside a resin casing 2.

配線板３は、外部回路（図示せず）との接続に用いる外部電極９と、半導体チップ４に接続する接続電極７とを有している。この配線板３は矩形状に形成されている。外部電極９は配線板３の端辺３ｂ付近であってその下面３ｃに接続されている。接続電極７は配線板３の端辺３ｂ付近であってその上面３ａに接続されている。配線板３の上面３ａには半導体チップ４が積層される。   The wiring board 3 has an external electrode 9 used for connection to an external circuit (not shown) and a connection electrode 7 connected to the semiconductor chip 4. The wiring board 3 is formed in a rectangular shape. The external electrode 9 is connected to the lower surface 3c near the end 3b of the wiring board 3. The connection electrode 7 is connected to the upper surface 3a in the vicinity of the end 3b of the wiring board 3. A semiconductor chip 4 is stacked on the upper surface 3 a of the wiring board 3.

半導体チップ４は配線板３の上面３ａにおいてその高さ方向に３個積層されている。これらの半導体チップ４としては、配線板３よりも小さな矩形状に形成されたベアチップが用いられており、その上面４ａの端辺４ｂ周辺に矩形状の接続端子８が形成されている。本実施形態において、これら３個の半導体チップ４を積層下方から順に第１の半導体チップ４１、第２の半導体チップ４２および第３の半導体チップ４３と称し、それらの接続端子８を積層下方から順に第１の接続端子８１、第２の接続端子８２および第３の接続端子８３と称する。   Three semiconductor chips 4 are stacked in the height direction on the upper surface 3 a of the wiring board 3. As these semiconductor chips 4, bare chips formed in a rectangular shape smaller than the wiring board 3 are used, and rectangular connection terminals 8 are formed around the edge 4b of the upper surface 4a. In the present embodiment, these three semiconductor chips 4 are referred to as a first semiconductor chip 41, a second semiconductor chip 42, and a third semiconductor chip 43 in order from the bottom of the stack, and their connection terminals 8 are sequentially connected from the bottom of the stack. The first connection terminal 81, the second connection terminal 82, and the third connection terminal 83 are referred to.

ただし、本発明の半導体装置１において半導体チップ4の積層可能な個数は３個に限られず、１個から任意の積層合計枚数Ｎまでを選択することができる。その際は、積層下方からｎ番目の半導体チップ４を第ｎの半導体チップと称し、その上面に形成される接続端子８を第ｎの接続端子と称する。なお、ｎは２から積層合計枚数Ｎまでの間の任意の正の整数である。   However, the number of semiconductor chips 4 that can be stacked in the semiconductor device 1 of the present invention is not limited to three, and any number from one to a total number N of stacked layers can be selected. In that case, the nth semiconductor chip 4 from the bottom of the stack is referred to as the nth semiconductor chip, and the connection terminal 8 formed on the upper surface thereof is referred to as the nth connection terminal. Note that n is an arbitrary positive integer between 2 and the total number N of stacked layers.

第１の半導体チップ４１は、配線板３の上面３ａに接続電極７が露出するように積層されている。同様にして、第２の半導体チップ４２は第１の半導体チップ４１の上面４１ａに第１の接続端子８１が露出するように積層されており、第３の半導体チップ４３は第２の半導体チップ４２の上面４２ａに第２の接続端子８２が露出するように積層されている。   The first semiconductor chip 41 is stacked on the upper surface 3 a of the wiring board 3 so that the connection electrode 7 is exposed. Similarly, the second semiconductor chip 42 is stacked on the upper surface 41 a of the first semiconductor chip 41 so that the first connection terminals 81 are exposed, and the third semiconductor chip 43 is the second semiconductor chip 42. The second connection terminals 82 are laminated so as to be exposed on the upper surface 42a.

本実施形態の半導体チップ４の積層パターンは、同一形状の半導体チップ４を同一方向（図１および図２の右方）にずらして直線階段状に積層されたパターンになっている。そして、接続電極７およびすべての接続端子８は、半導体チップ４の積層により生じた直線階段領域において仮想の直線上に配置されている。ただし、半導体チップ４の積層パターンは接続電極７および接続端子８が露出するような積層パターンであればよいので、図１および図２に示すような同一方向にずらしたパターン以外の積層パターンであっても良い。   The stacked pattern of the semiconductor chips 4 according to the present embodiment is a pattern in which the semiconductor chips 4 having the same shape are shifted in the same direction (rightward in FIGS. 1 and 2) and stacked in a linear step shape. The connection electrode 7 and all the connection terminals 8 are arranged on a virtual straight line in a linear staircase region generated by stacking the semiconductor chips 4. However, since the laminated pattern of the semiconductor chip 4 may be a laminated pattern that exposes the connection electrodes 7 and the connection terminals 8, it is a laminated pattern other than the patterns shifted in the same direction as shown in FIGS. May be.

例えば、図３および図４に示すように、３個の半導体チップ４を大、中、小の３つの大きさに形成して、大きい半導体チップ４から順に半導体チップ４を配線板３に積層させても良い。それらの半導体チップ４の上面４ａは半導体装置１の右方および左方の両方（図３および図４を参照）において露出しているため、それらに形成される接続端子８を半導体装置１の右方および左方の両方に配置しても良い。   For example, as shown in FIGS. 3 and 4, three semiconductor chips 4 are formed in three sizes of large, medium, and small, and the semiconductor chips 4 are stacked on the wiring board 3 in order from the largest semiconductor chip 4. May be. Since the upper surfaces 4a of the semiconductor chips 4 are exposed on both the right and left sides of the semiconductor device 1 (see FIGS. 3 and 4), the connection terminals 8 formed on them are connected to the right side of the semiconductor device 1. It may be arranged on both the left side and the left side.

また、例えば、図５に示すように、半導体チップ４の長手方向を互い違いに積層させても良い。この場合、半導体チップ４の上面４ａのどの部分が露出するかは積層パターンにより異なるので、これらの半導体チップ４を積層させたときにそれらの上面４ａのうちの露出する部分に接続端子８を形成する。   Further, for example, as shown in FIG. 5, the longitudinal directions of the semiconductor chips 4 may be stacked alternately. In this case, which part of the upper surface 4a of the semiconductor chip 4 is exposed differs depending on the lamination pattern. Therefore, when these semiconductor chips 4 are laminated, the connection terminal 8 is formed on the exposed part of the upper surface 4a. To do.

接着層５は、図１および図２に示すように、配線板３と第１の半導体チップ４１との間、第１の半導体チップ４１と第２の半導体チップ４２との間および第２の半導体チップ４２と第３の半導体チップ４３との間にそれぞれ介在している。この接着層５は、フェノール硬化型樹脂などの液体樹脂を用いて形成されている。   As shown in FIGS. 1 and 2, the adhesive layer 5 is formed between the wiring board 3 and the first semiconductor chip 41, between the first semiconductor chip 41 and the second semiconductor chip 42, and the second semiconductor. Each is interposed between the chip 42 and the third semiconductor chip 43. The adhesive layer 5 is formed using a liquid resin such as a phenol curable resin.

また、この接着層５は、配線板３の上方に面する方向に傾斜させた側面５ａを有している。例えば、配線板３と第１の半導体チップ４１との間に介在する接着層５の側面５ａは、配線板３の上面３ａから第１の半導体チップ４１の上面４１ａの端辺（端部）４１ｂまでの間において傾斜している。   The adhesive layer 5 has a side surface 5 a that is inclined in a direction facing the upper side of the wiring board 3. For example, the side surface 5 a of the adhesive layer 5 interposed between the wiring board 3 and the first semiconductor chip 41 is from the upper surface 3 a of the wiring board 3 to the end (end) 41 b of the upper surface 41 a of the first semiconductor chip 41. It is inclined until.

同様に、第１の半導体チップ４１と第２の半導体チップ４２との間に介在する接着層５の側面５ａは第１の半導体チップ４１の上面４１ａから第２の半導体チップ４２の上面４２ａの端辺（端部）４２ｂまでの間において傾斜しており、第２の半導体チップ４２と第３の半導体チップ４３との間に介在する接着層５の側面５ａは第２の半導体チップ４２の上面４２ａから第３の半導体チップ４３の上面４３ａの端辺（端部）４３ｂまでの間において傾斜している。   Similarly, the side surface 5 a of the adhesive layer 5 interposed between the first semiconductor chip 41 and the second semiconductor chip 42 extends from the upper surface 41 a of the first semiconductor chip 41 to the end of the upper surface 42 a of the second semiconductor chip 42. The side surface 5a of the adhesive layer 5 is inclined between the side (end) 42b and is interposed between the second semiconductor chip 42 and the third semiconductor chip 43, and the upper surface 42a of the second semiconductor chip 42. To the end side (end portion) 43b of the upper surface 43a of the third semiconductor chip 43.

薄膜配線６は、すべての接続端子８および接続電極７に接続している。この薄膜配線６は薄膜形成法を用いて形成される。例えば、本実施形態の薄膜配線６は、導電材料をスパッタまたは蒸着することにより形成されている。また、本実施形態のすべての接続端子８および接続電極７は、図１および図２に示すように、半導体チップ４の積層により生じた直線階段領域において直線上に配置されている。言い換えると、この薄膜配線６は、配線板３の上面３ａ、接着層５の側面５ａ、第１の半導体チップ４１の上面４１ａ、接着層５の側面５ａ、第２の半導体チップ４２の上面４２ａ、接着層５の側面５ａ、第３の半導体チップ４３の上面４３ａの順に連続して直線状に形成されている。   The thin film wiring 6 is connected to all connection terminals 8 and connection electrodes 7. The thin film wiring 6 is formed using a thin film forming method. For example, the thin film wiring 6 of the present embodiment is formed by sputtering or vapor-depositing a conductive material. Further, all the connection terminals 8 and connection electrodes 7 of the present embodiment are arranged on a straight line in a linear staircase region generated by stacking the semiconductor chips 4 as shown in FIGS. 1 and 2. In other words, the thin film wiring 6 includes the upper surface 3a of the wiring board 3, the side surface 5a of the adhesive layer 5, the upper surface 41a of the first semiconductor chip 41, the side surface 5a of the adhesive layer 5, the upper surface 42a of the second semiconductor chip 42, The side surface 5 a of the adhesive layer 5 and the upper surface 43 a of the third semiconductor chip 43 are continuously formed in a linear shape.

次に、図６から図１０を用いて、本実施形態の半導体装置１の製造方法を説明する。   Next, a method for manufacturing the semiconductor device 1 of this embodiment will be described with reference to FIGS.

本実施形態の半導体装置１は、図６、図７および図８に示す順に、３つの工程を経て製造される。   The semiconductor device 1 of this embodiment is manufactured through three steps in the order shown in FIGS.

工程ａにおいては、図６に示すように、配線板３の上面３ａに第１の半導体チップ４１を積層する。後の工程において配線板３の上面３ａに形成された接続電極７と第１の半導体チップ４１の上面４１ａに形成された接続端子８１とを薄膜配線６により接続させるため、接続電極７が露出するように第１の半導体チップ４１を配線板３の上面３ａに積層する。   In step a, as shown in FIG. 6, the first semiconductor chip 41 is stacked on the upper surface 3 a of the wiring board 3. In a later process, the connection electrode 7 is exposed because the connection electrode 7 formed on the upper surface 3a of the wiring board 3 and the connection terminal 81 formed on the upper surface 41a of the first semiconductor chip 41 are connected by the thin film wiring 6. Thus, the first semiconductor chip 41 is stacked on the upper surface 3 a of the wiring board 3.

配線板３および半導体チップ４は、接着層５を介して接着されている。この接着層５は、前述した液体樹脂を用いて、配線板３の上面３ａから第１の半導体チップ４１の上面４１ａの端辺４１ｂまで傾斜した側面５ａを有するように塗布形成されている。接着層５の側面５ａは粘度の高い液体樹脂を用いて表面張力を利用して形成しても良いし、長方形状の接着層５を形成した後に側面５ａを研磨して傾斜させても良い。また、接着層５の側面５ａは平滑であることが好ましいが、上方または下方に湾曲しても良い。   The wiring board 3 and the semiconductor chip 4 are bonded via an adhesive layer 5. The adhesive layer 5 is applied and formed using the above-described liquid resin so as to have a side surface 5 a inclined from the upper surface 3 a of the wiring board 3 to the end side 41 b of the upper surface 41 a of the first semiconductor chip 41. The side surface 5a of the adhesive layer 5 may be formed using a liquid resin having a high viscosity by utilizing surface tension, or after the rectangular adhesive layer 5 is formed, the side surface 5a may be polished and inclined. The side surface 5a of the adhesive layer 5 is preferably smooth, but may be curved upward or downward.

工程ｂにおいては、図７に示すように、第１の半導体チップ４１の上面４１ａに第２の半導体チップ４２を積層させる。また、第２の半導体チップ４２の上面４２ａには第３の半導体チップ４３を積層させる。いずれの積層においても、第１の半導体チップ４１の上面４１ａに形成された第１の接続端子８１および第２の半導体チップ４２の上面４２ａに形成された第２の接続端子８２が露出するように第２の半導体チップ４２および第３の半導体チップ４３を積層させる。また、工程ａと同様、第１の半導体チップ４１と第２の半導体チップ４２との間および第２の半導体チップ４２と第３の半導体チップ４３との間に前述した傾斜の側面５ａを有する接着層５を塗布する。   In step b, as shown in FIG. 7, the second semiconductor chip 42 is stacked on the upper surface 41 a of the first semiconductor chip 41. A third semiconductor chip 43 is stacked on the upper surface 42 a of the second semiconductor chip 42. In any stack, the first connection terminal 81 formed on the upper surface 41a of the first semiconductor chip 41 and the second connection terminal 82 formed on the upper surface 42a of the second semiconductor chip 42 are exposed. The second semiconductor chip 42 and the third semiconductor chip 43 are stacked. Further, similarly to the step a, the bonding having the inclined side surface 5a described above between the first semiconductor chip 41 and the second semiconductor chip 42 and between the second semiconductor chip 42 and the third semiconductor chip 43. Layer 5 is applied.

ここで、本実施形態の３個の半導体チップ４は、図７に示すように、それらをそれぞれ同一方向（図７の右方）にずらして直線階段状に積層されていることが好ましい。また、接続電極７およびすべての接続端子８は、半導体チップ４の積層により生じた直線階段領域、すなわち配線板３の上面３ａの左端および半導体チップ４の上面４ａの左端においてそれらが直線上に配置されていることが好ましい。   Here, as shown in FIG. 7, it is preferable that the three semiconductor chips 4 of the present embodiment are stacked in a linear step shape by shifting them in the same direction (rightward in FIG. 7). Further, the connection electrodes 7 and all the connection terminals 8 are arranged in a straight line at the straight staircase region generated by the stacking of the semiconductor chips 4, that is, the left end of the upper surface 3a of the wiring board 3 and the left end of the upper surface 4a of the semiconductor chip 4. It is preferable that

なお、本実施形態の半導体装置１は半導体チップ４を３個積層させているために工程ｂを行なうが、仮に１個の半導体チップ４のみを配線板３の上面３ａに積層させる場合は工程ｂを行なう必要はない。また、本実施形態と同様に半導体チップ４を２個以上積層させる場合においては、図示はしないが、第（ｎ−１）の半導体チップの上面に第ｎの半導体チップを積層させる積層工程をｎが２から積層合計枚数Ｎまで順に行なう。その際、前述と同様、接続電極７およびすべての接続端子８（第１の接続端子８１から第（ｎ−１）の接続端子までの接続端子８）を露出させるように半導体チップ４を積層させる。なお、第ｎの半導体チップに形成された第ｎの接続端子８はその上方に半導体チップ４が積層されないので露出した状態になっている。   The semiconductor device 1 of the present embodiment performs step b because three semiconductor chips 4 are stacked. However, if only one semiconductor chip 4 is stacked on the upper surface 3a of the wiring board 3, the process b is performed. There is no need to do. Further, in the case where two or more semiconductor chips 4 are stacked as in the present embodiment, although not shown, a stacking step of stacking the nth semiconductor chip on the upper surface of the (n−1) th semiconductor chip is n. Are sequentially performed from 2 to the total number N of stacked layers. At that time, as described above, the semiconductor chip 4 is laminated so that the connection electrode 7 and all the connection terminals 8 (the connection terminals 8 from the first connection terminal 81 to the (n−1) th connection terminal) are exposed. . Note that the nth connection terminal 8 formed on the nth semiconductor chip is exposed because the semiconductor chip 4 is not stacked thereabove.

工程ｃにおいては、図８に示すように、スリット１１が形成されたマスク１０を用いて、配線板３の上方から導電材料をスパッタすることにより薄膜配線６を形成する。スパッタの代わりに蒸着により薄膜配線６を形成しても良い。本実施形態の薄膜配線６は図２に示すように直線状（正確には直線階段状）に形成される。そのため、マスク１０のスリット１１は、薄膜配線６を配線板３の上方から見た形状と同形状の直線状に形成されている。   In step c, as shown in FIG. 8, the thin film wiring 6 is formed by sputtering a conductive material from above the wiring board 3 using the mask 10 in which the slits 11 are formed. The thin film wiring 6 may be formed by vapor deposition instead of sputtering. As shown in FIG. 2, the thin film wiring 6 of this embodiment is formed in a straight line shape (precisely, a straight staircase shape). Therefore, the slit 11 of the mask 10 is formed in a straight line having the same shape as the shape of the thin film wiring 6 viewed from above the wiring board 3.

ここで、本実施形態のマスク１０は、図９に示すように、薄膜配線６の対向位置に形成された階段部１２にスリット１１を有していることが好ましい。また、この階段部１２の形状としては、最下層に積層された配線板３から最上層に積層された第３の半導体チップ４３までの間において配線板３の上面３ａ、接着層５の側面５ａ、第１の半導体チップ４１の上面４１ａ、接着層５の側面５ａ、第２の半導体チップ４２の上面４２ａ、接着層５の側面５ａ、第３の半導体チップ４３の上面３ａの順に階段状に形成される薄膜配線６の形成領域と同様の形状に形成されていることが好ましい。   Here, as shown in FIG. 9, the mask 10 of the present embodiment preferably has a slit 11 in a stepped portion 12 formed at a position facing the thin film wiring 6. Further, the shape of the staircase portion 12 is such that the upper surface 3a of the wiring board 3 and the side surface 5a of the adhesive layer 5 between the wiring board 3 stacked in the lowermost layer and the third semiconductor chip 43 stacked in the uppermost layer. The upper surface 41a of the first semiconductor chip 41, the side surface 5a of the adhesive layer 5, the upper surface 42a of the second semiconductor chip 42, the side surface 5a of the adhesive layer 5, and the upper surface 3a of the third semiconductor chip 43 are formed stepwise. Preferably, the thin film wiring 6 is formed in the same shape as the region where the thin film wiring 6 is formed.

薄膜配線６の形成領域の具体例としては、図１および図２に示すような直線階段状の形成領域であったり、図３および図４に示すような左右に分かれて形成された直線階段状の形成領域であったり、図５に示すようなジグザグ階段状の形成領域などが挙げられる。本実施形態の工程ａおよび工程ｂにおいては、図７に示すように、半導体チップ４を同一方向にずらして積層させているので、薄膜配線６の形成領域は直線階段状になる。   As a specific example of the formation region of the thin film wiring 6, it is a linear staircase formation region as shown in FIGS. 1 and 2, or a straight staircase shape divided into left and right as shown in FIG. 3 and FIG. Or a zigzag step-like formation region as shown in FIG. In step a and step b of the present embodiment, as shown in FIG. 7, the semiconductor chips 4 are stacked while being shifted in the same direction, so that the formation region of the thin film wiring 6 has a linear staircase shape.

本実施形態の半導体チップ４の積層パターンのように半導体チップ４を同一方向にずらして積層させる場合、図７に示すように、半導体チップ４の全体に生じた傾斜が一定の角度になりやすい。そこで、本実施形態のマスク１０においては、図１０に示すように、スリット１１が薄膜配線６の対向位置に形成された傾斜部１３に形成されていてもよい。この傾斜部１３は、最下層に積層された配線板３から最上層に積層された第３の半導体チップ４３までの間において半導体チップ４の全体に生じた傾斜と同程度の傾きをもって形成されていることが好ましい。   When the semiconductor chips 4 are stacked while being shifted in the same direction as in the stacked pattern of the semiconductor chips 4 of this embodiment, the inclination generated in the entire semiconductor chip 4 tends to be a constant angle as shown in FIG. Therefore, in the mask 10 of the present embodiment, as shown in FIG. 10, the slit 11 may be formed in the inclined portion 13 formed at the position facing the thin film wiring 6. The inclined portion 13 is formed with an inclination similar to the inclination generated in the entire semiconductor chip 4 between the wiring board 3 stacked in the lowermost layer and the third semiconductor chip 43 stacked in the uppermost layer. Preferably it is.

次に、図１から図１４を用いて、本実施形態の半導体装置１およびその製造方法の作用を説明する。   Next, the operation of the semiconductor device 1 and the manufacturing method thereof according to the present embodiment will be described with reference to FIGS.

本実施形態の半導体装置１においては、図１および図２に示すように、配線板３の接続電極７および半導体チップ４の接続端子８が露出するように配線板３および３個の半導体チップ４が積層されている。ここで、従来においては、接続電極７および全ての接続端子８が図１５に示すようなワイヤボンディングにより接続されていたが、本実施形態の半導体装置１においては、図１および図２に示すように、これらの接続電極７および接続端子８が薄膜配線６により接続されている。そのため、ワイヤボンディングに必要なスペース分だけ実装スペースを小さくすることができる。   In the semiconductor device 1 of the present embodiment, as shown in FIGS. 1 and 2, the wiring board 3 and the three semiconductor chips 4 so that the connection electrodes 7 of the wiring board 3 and the connection terminals 8 of the semiconductor chip 4 are exposed. Are stacked. Here, conventionally, the connection electrode 7 and all the connection terminals 8 are connected by wire bonding as shown in FIG. 15, but in the semiconductor device 1 of this embodiment, as shown in FIG. 1 and FIG. In addition, the connection electrode 7 and the connection terminal 8 are connected by the thin film wiring 6. Therefore, the mounting space can be reduced by the space necessary for wire bonding.

また、３個の半導体チップ４は、図１および図２に示すように、それらをそれぞれ同一方向（図１および図２においては右方）にずらして階段状に積層されている。そのため、図３および図４または図５に示すような半導体チップ４を同一方向にずらして積層する積層パターン以外の積層パターンでそれぞれ積層するよりも、半導体チップ４の積層スペースを小さくすることができる。   Further, as shown in FIGS. 1 and 2, the three semiconductor chips 4 are stacked in a staircase pattern by shifting them in the same direction (rightward in FIGS. 1 and 2). Therefore, the stacking space of the semiconductor chip 4 can be reduced as compared with the stacking pattern other than the stacking pattern in which the semiconductor chips 4 as illustrated in FIG. 3 and FIG. 4 or FIG. .

また、半導体チップ４を同一方向にずらして積層すると、半導体チップ４をずらした方向と反対の方向（図１および図２においては左方）に図１および図２に示すような直線階段領域が形成される。この直線階段領域に接続電極７および接続端子８を直線上に配置することにより、接続電極７および接続端子８を接続する薄膜配線６が直線状（正確には直線階段状）に形成されているので、薄膜配線６の長さが最短になり、薄膜配線６の電気的な損失を最小限に抑えることができる。   When the semiconductor chips 4 are shifted in the same direction and stacked, a linear staircase region as shown in FIGS. 1 and 2 is formed in the direction opposite to the direction in which the semiconductor chips 4 are shifted (leftward in FIGS. 1 and 2). It is formed. By arranging the connection electrode 7 and the connection terminal 8 on a straight line in the linear staircase region, the thin film wiring 6 for connecting the connection electrode 7 and the connection terminal 8 is formed in a straight line shape (precisely, a straight staircase shape). Therefore, the length of the thin film wiring 6 becomes the shortest, and the electrical loss of the thin film wiring 6 can be minimized.

また、本実施形態の半導体装置１は、図６、図７および図８の順に示すように、工程ａ、工程ｂおよび工程ｃを経て製造される。工程ａおよび工程ｂにおいては、配線板３および半導体チップ４が接着層５を介して隣位する配線板３または他の半導体チップ４に接着されている。   In addition, the semiconductor device 1 of the present embodiment is manufactured through a process a, a process b, and a process c as shown in the order of FIGS. In step a and step b, the wiring board 3 and the semiconductor chip 4 are bonded to the adjacent wiring board 3 or another semiconductor chip 4 via the adhesive layer 5.

仮に、図１１に示すように、接着層５を矩形状にしてその側面５ａの法線を積層方向と直交するように形成したとする。その場合、図１２に示すように、配線板３の上方からスパッタが行なわれるため、スパッタ方向と対向する配線板３の上面３ａおよび半導体チップ４の上面４ａにのみスパッタ粒子２０が付着し、スパッタ方向と対向していない接着層５の側面５ａおよび半導体チップ４の側面４ｃにはスパッタ粒子２０がほとんど付着しないことになる。つまり、薄膜配線６が部分的に形成されることになる。そのため、接着層５の側面５ａおよび半導体チップ４の側面４ｃにスパッタ粒子２０を付着させる場合、図１３に示すように、接着層５の側面５ａおよび半導体チップ４の側面４ｃがスパッタ方向と対向する位置になるまで積層された配線板３および半導体チップ４を傾けなければならない。   As shown in FIG. 11, it is assumed that the adhesive layer 5 is formed in a rectangular shape so that the normal line of the side surface 5a is perpendicular to the stacking direction. In this case, since sputtering is performed from above the wiring board 3 as shown in FIG. 12, the sputtered particles 20 adhere only to the upper surface 3a of the wiring board 3 and the upper surface 4a of the semiconductor chip 4 facing the sputtering direction, The sputtered particles 20 hardly adhere to the side surface 5a of the adhesive layer 5 and the side surface 4c of the semiconductor chip 4 that are not opposed to the direction. That is, the thin film wiring 6 is partially formed. Therefore, when the sputtered particles 20 are attached to the side surface 5a of the adhesive layer 5 and the side surface 4c of the semiconductor chip 4, as shown in FIG. 13, the side surface 5a of the adhesive layer 5 and the side surface 4c of the semiconductor chip 4 face the sputtering direction. The laminated wiring board 3 and semiconductor chip 4 must be tilted until the position is reached.

そこで、本実施形態の接着層５は、図７に示すように、配線板３の上方に面して傾斜させた所定の側面５ａを有している。また、この側面５ａは、下層の半導体チップ（例えば第１の半導体チップ４１）４の上面４ａからその上層の半導体チップ（例えば第２の半導体チップ４２）４の上面４ａの端部までの間、および配線板３の上面３ａから第１の半導体チップ４１の上面４１ａの端部まで間に形成されている。そのため、配線板３の上面３ａおよび半導体チップ４の上面４ａに薄膜配線６を形成する際、積層された配線板３および半導体チップ４を傾けなくても接着層５の側面５ａに薄膜配線６を同時に形成することができる。   Therefore, as shown in FIG. 7, the adhesive layer 5 of the present embodiment has a predetermined side surface 5 a that is inclined to face upward of the wiring board 3. The side surface 5a extends from the upper surface 4a of the lower semiconductor chip (for example, the first semiconductor chip 41) 4 to the end portion of the upper surface 4a of the upper semiconductor chip (for example, the second semiconductor chip 42) 4. And formed between the upper surface 3 a of the wiring board 3 and the end of the upper surface 41 a of the first semiconductor chip 41. Therefore, when the thin film wiring 6 is formed on the upper surface 3 a of the wiring board 3 and the upper surface 4 a of the semiconductor chip 4, the thin film wiring 6 is formed on the side surface 5 a of the adhesive layer 5 without tilting the laminated wiring board 3 and semiconductor chip 4. They can be formed simultaneously.

本実施形態の半導体装置１の製造方法においては、前述した薄膜配線６の形成手法だけでなく、薄膜配線６の形成精度も向上させている。本実施形態の半導体装置１においては、図１に示すように、その高さ方向に３個の半導体チップ４が積層されている。そのため、図８に示すような平板状のマスク１０を使用すると、マスク１０から半導体チップ４、接着層５または配線板３までの距離が局所的に異なってしまう。すると、スパッタ粒子２０は垂直方向だけでなく斜め方向にも進行するため、図８および図１４に示すように、マスク１０に近い部分の薄膜配線６は所定の厚さおよび幅と同等に形成されるのに対し、マスク１０から遠い部分の薄膜配線６が所定の厚さよりも薄く、かつ所定の幅よりも広くなってしまう。そして、半導体チップ４の積層合計枚数Ｎが多くなればなるほど、薄膜配線６の形成精度が劣化しやすくなる。   In the method for manufacturing the semiconductor device 1 according to the present embodiment, not only the method for forming the thin film wiring 6 described above but also the formation accuracy of the thin film wiring 6 is improved. In the semiconductor device 1 of the present embodiment, as shown in FIG. 1, three semiconductor chips 4 are stacked in the height direction. Therefore, when a flat mask 10 as shown in FIG. 8 is used, the distance from the mask 10 to the semiconductor chip 4, the adhesive layer 5, or the wiring board 3 is locally different. Then, since the sputtered particles 20 travel not only in the vertical direction but also in the oblique direction, as shown in FIGS. 8 and 14, the thin film wiring 6 near the mask 10 is formed to have the same thickness and width. In contrast, the portion of the thin film wiring 6 far from the mask 10 is thinner than a predetermined thickness and wider than a predetermined width. As the total number N of stacked semiconductor chips 4 increases, the formation accuracy of the thin film wiring 6 is likely to deteriorate.

そこで、本実施形態のマスク１０においては、図９に示すように、階段状に形成された薄膜配線６の形成領域と同様の形状に形成された階段部１２が形成されており、その階段部１２にスリット１１が形成されている。つまり、配線板３および半導体チップ４の積層形状にあわせてマスク１０の形状を決めることにより、薄膜配線６の形成領域とマスク１０とのギャップを一定にすることができる。そのため、図８に示すような階段部１２のない平板状のマスク１０を用いて薄膜配線６を形成した場合と比較して、形成精度の高い薄膜配線６を形成することができる。   Therefore, in the mask 10 of the present embodiment, as shown in FIG. 9, the staircase portion 12 formed in the same shape as the formation region of the thin film wiring 6 formed in a staircase shape is formed. A slit 11 is formed in 12. That is, by determining the shape of the mask 10 according to the laminated shape of the wiring board 3 and the semiconductor chip 4, the gap between the formation region of the thin film wiring 6 and the mask 10 can be made constant. Therefore, it is possible to form the thin film wiring 6 with higher formation accuracy as compared with the case where the thin film wiring 6 is formed using the flat mask 10 without the stepped portion 12 as shown in FIG.

ただし、小さな半導体チップ４の積層形状にあわせてマスク１０に階段部１２を形成するには加工精度上困難な場合もある。そこで、本実施形態のマスク１０に図９に示すような階段部１２を形成せず、図１０に示すような傾斜部１３を形成しても良い。この傾斜部１３は、半導体チップ４をそれぞれずらして積層させることにより半導体チップ４の全体に生じた傾斜と同程度の傾きをもって形成されている。そのため、薄膜配線６の形成領域とマスク１０とのギャップは一定にはならないが、薄膜配線６の形成精度を高く維持することができる程度にまで薄膜配線６の形成領域とマスク１０とのギャップを狭くすることができる。そのため、図８に示すような傾斜部１３のない平板状のマスク１０を用いて薄膜配線６を形成した場合と比較して、形成精度の高い薄膜配線６を形成することができる。   However, it may be difficult to form the stepped portion 12 on the mask 10 in accordance with the stacked shape of the small semiconductor chips 4 in terms of processing accuracy. Therefore, the inclined portion 13 as shown in FIG. 10 may be formed in the mask 10 of this embodiment without forming the stepped portion 12 as shown in FIG. The inclined portion 13 is formed with an inclination similar to the inclination generated in the entire semiconductor chip 4 by stacking the semiconductor chips 4 while being shifted from each other. For this reason, the gap between the formation region of the thin film wiring 6 and the mask 10 is not constant, but the gap between the formation region of the thin film wiring 6 and the mask 10 is such that the formation accuracy of the thin film wiring 6 can be maintained high. Can be narrowed. Therefore, it is possible to form the thin film wiring 6 with higher formation accuracy as compared with the case where the thin film wiring 6 is formed using the flat mask 10 without the inclined portion 13 as shown in FIG.

すなわち、本実施形態の半導体装置１の製造方法および半導体装置１によれば、ワイヤボンディングに必要なスペースを除外した分だけ半導体装置１の実装面積および実装体積を小さくすることができるので、半導体装置１を小型化することができるという作用を生じる。   That is, according to the manufacturing method of the semiconductor device 1 and the semiconductor device 1 of the present embodiment, the mounting area and the mounting volume of the semiconductor device 1 can be reduced by the amount excluding the space necessary for wire bonding. 1 produces the effect | action that can be reduced in size.

なお、本発明は、前述した実施形態などに限定されるものではなく、必要に応じて種々の変更が可能である。   In addition, this invention is not limited to embodiment mentioned above etc., A various change is possible as needed.

本実施形態の半導体装置を示す断面図Sectional drawing which shows the semiconductor device of this embodiment 本実施形態の半導体装置の内部を示す平面図The top view which shows the inside of the semiconductor device of this embodiment 本実施形態の半導体装置における他の積層パターンの一例を示す断面図Sectional drawing which shows an example of the other laminated pattern in the semiconductor device of this embodiment 本実施形態の半導体装置における他の積層パターンの一例を示す平面図The top view which shows an example of the other laminated pattern in the semiconductor device of this embodiment 本実施形態の半導体装置における他の積層パターンの一例を示す断面図Sectional drawing which shows an example of the other laminated pattern in the semiconductor device of this embodiment 本実施形態の半導体装置の製造方法における工程ａを示す断面図Sectional drawing which shows the process a in the manufacturing method of the semiconductor device of this embodiment 本実施形態の半導体装置の製造方法における工程ｂを示す断面図Sectional drawing which shows the process b in the manufacturing method of the semiconductor device of this embodiment 本実施形態の半導体装置の製造方法における工程ｃを示す断面図Sectional drawing which shows process c in the manufacturing method of the semiconductor device of this embodiment 本実施形態の工程ｃに用いるマスクに設けた階段部を示す断面図Sectional drawing which shows the step part provided in the mask used for the process c of this embodiment 本実施形態の工程ｃに用いるマスクに設けた傾斜部を示す断面図Sectional drawing which shows the inclination part provided in the mask used for the process c of this embodiment 本実施形態に用いる接着層の側面を仮に傾斜させないで形成した場合を示す断面図Sectional drawing which shows the case where it forms without inclining the side surface of the contact bonding layer used for this embodiment temporarily 図１１の配線板および半導体チップに配線板および半導体チップの上方からスパッタを行なった状態を示す断面図Sectional drawing which shows the state which sputtered | spattered the wiring board and semiconductor chip of FIG. 11 from the upper direction of a wiring board and a semiconductor chip 図１１の配線板および半導体チップを傾けて配線板および半導体チップの側方からスパッタを行なった状態を示す部分断面図FIG. 11 is a partial cross-sectional view showing a state where the wiring board and the semiconductor chip in FIG. 11 are tilted and sputtering is performed from the side of the wiring board and the semiconductor chip. 図９に示したマスクを用いて配線板および半導体チップにスパッタを行なった状態を示す平面図The top view which shows the state which sputter | spatterd the wiring board and the semiconductor chip using the mask shown in FIG. 従来の半導体装置を示す断面図Sectional view showing a conventional semiconductor device

符号の説明Explanation of symbols

１ 半導体装置
３ 配線板
４、４１、４２、４３ 半導体チップ
４ａ、４１ａ、４２ａ、４３ａ （半導体チップの）上面
４ｂ、４１ｂ、４２ｂ、４３ｂ （半導体チップの上面の）端辺
５ 接着層
５ａ （接着層の）側面
６ 薄膜配線
７ 接続電極
８、８１、８２、８３ 接続端子
１０ マスク
１１ スリット
１２ 階段部
１３ 傾斜部 DESCRIPTION OF SYMBOLS 1 Semiconductor device 3 Wiring board 4, 41, 42, 43 Semiconductor chip 4a, 41a, 42a, 43a (Semiconductor chip) upper surface 4b, 41b, 42b, 43b (Semiconductor chip upper surface) Edge 5 Adhesive layer 5a (Adhesion) Side face of layer 6 Thin film wiring 7 Connection electrode 8, 81, 82, 83 Connection terminal 10 Mask 11 Slit 12 Stepped portion 13 Inclined portion

Claims (7)

上面に接続電極が形成された配線板の前記上面に第１の半導体チップを前記接続電極が露出するように積層する工程ａと、
前記半導体チップを２個以上積層させる場合においては第（ｎ−１）の接続端子が上面に形成された第（ｎ−１）の半導体チップ（ｎ：２から前記半導体チップの積層合計枚数Ｎまでの間の任意の正の整数）の前記上面に第ｎの半導体チップを前記第（ｎ−１）の接続端子が露出するように積層させる１の積層工程をｎが２からＮまで順に行なう工程ｂと、
前記第ｎの半導体チップの上面に形成された第ｎの接続端子を含むすべての前記接続端子および前記接続電極を接続させる薄膜配線と同形状のスリットが形成されたマスクを用いて前記配線板の上方から導電材料をスパッタまたは蒸着することにより前記薄膜配線を形成する工程ｃと
を備えていることを特徴とする半導体装置の製造方法。 A step a of laminating the first semiconductor chip on the upper surface of the wiring board on which the connection electrode is formed so that the connection electrode is exposed;
When two or more semiconductor chips are stacked, from the (n-1) th semiconductor chip (n: 2 to the total number N of stacked semiconductor chips) having the (n-1) th connection terminal formed on the upper surface. Step 1 in which n is stacked in order from 2 to N in order to stack the nth semiconductor chip so that the (n−1) th connection terminal is exposed on the upper surface of any positive integer between b,
Using all the connection terminals including the nth connection terminal formed on the upper surface of the nth semiconductor chip and a mask in which a slit having the same shape as the thin film wiring for connecting the connection electrode is formed, the wiring board is formed. And a step c of forming the thin film wiring by sputtering or vapor-depositing a conductive material from above. 前記配線板および前記半導体チップは、接着層を介して隣位する前記配線板または他の前記半導体チップに接着されており、
前記接着層は、前記第（ｎ−１）の半導体チップもしくは前記配線板の上面から前記第ｎの半導体チップもしくは前記第１の半導体チップの上面の端部までの間において前記配線板の上方に面する方向に傾斜させた側面を有している
ことを特徴とする請求項１に記載の半導体装置の製造方法。 The wiring board and the semiconductor chip are bonded to the adjacent wiring board or other semiconductor chip via an adhesive layer,
The adhesive layer is located above the wiring board between an upper surface of the (n-1) th semiconductor chip or the wiring board and an end portion of the upper surface of the nth semiconductor chip or the first semiconductor chip. The method for manufacturing a semiconductor device according to claim 1, further comprising a side surface inclined in a facing direction. すべての前記半導体チップは、それらをそれぞれ同一方向にずらして直線階段状に積層されており、
前記接続電極およびすべての前記接続端子は、前記半導体チップの積層により生じた直線階段領域において直線上に配置されている
ことを特徴とする請求項２に記載の半導体装置の製造方法。 All the semiconductor chips are stacked in a linear staircase, shifting them in the same direction,
3. The method of manufacturing a semiconductor device according to claim 2, wherein the connection electrodes and all the connection terminals are arranged on a straight line in a linear staircase region generated by stacking the semiconductor chips. 前記マスクは、最下層に積層された前記配線板から最上層に積層された第Ｎの半導体チップまでの間において前記配線板の上面、前記接着層の側面、前記第１の半導体チップの上面、前記接着層の側面、・・・、前記接着層の側面、前記第Ｎの半導体チップの上面の順に階段状に形成される薄膜配線の形成領域と同様の形状に形成された階段部に前記スリットを有している
ことを特徴とする請求項２または請求項３に記載の半導体装置の製造方法。 The mask includes an upper surface of the wiring board, a side surface of the adhesive layer, an upper surface of the first semiconductor chip between the wiring board stacked in the lowermost layer and the Nth semiconductor chip stacked in the uppermost layer. The slit in the step portion formed in the same shape as the formation region of the thin film wiring formed stepwise in the order of the side surface of the adhesive layer, the side surface of the adhesive layer, and the upper surface of the Nth semiconductor chip. The method for manufacturing a semiconductor device according to claim 2, wherein: 前記マスクは、最下層に積層された前記配線板から最上層に積層された第Ｎの半導体チップまでの間においてすべての前記半導体チップをそれぞれずらして積層させることにより前記半導体チップの全体に生じた傾斜と同程度の傾きをもって形成された傾斜部に前記スリットを有している
ことを特徴とする請求項３に記載の半導体装置の製造方法。 The mask is generated in the entire semiconductor chip by shifting and laminating all the semiconductor chips between the wiring board laminated in the lowermost layer and the Nth semiconductor chip laminated in the uppermost layer. The method of manufacturing a semiconductor device according to claim 3, wherein the slit is provided in an inclined portion formed with an inclination similar to the inclination. 接続電極が上面に形成されている配線板と、
前記配線板の上面に前記接続電極が露出するように積層されている第１の半導体チップと、
前記半導体チップを２個以上積層させる場合においては第（ｎ−１）の接続端子が上面に形成された第（ｎ−１）の半導体チップ（ｎ：２から前記半導体チップの積層合計枚数Ｎまでの間の任意の正の整数）の前記上面に前記第（ｎ−１）の接続端子が露出するように積層されている第ｎの半導体チップと、
前記配線板と前記第１の半導体チップとの間および前記第（ｎ−１）の半導体チップと前記第ｎの半導体チップとの間にそれぞれ介在しているとともに、前記第（ｎ−１）の半導体チップもしくは前記配線板の上面から前記第ｎの半導体チップもしくは前記第１の半導体チップの上面の端部までの間において前記配線板の上方に面する方向に傾斜させた側面を有している接着層と、
導電材料をスパッタまたは蒸着することにより前記配線板の上面、前記接着層の側面、前記第１の半導体チップの上面、前記接着層の側面、・・・、前記接着層の側面、前記第Ｎの半導体チップの上面の順に連続して形成されており、前記第ｎの半導体チップの上面に形成された第ｎの接続端子を含むすべての前記接続端子および前記接続電極に接続している薄膜配線と
を備えていることを特徴とする半導体装置。 A wiring board having connection electrodes formed on the upper surface;
A first semiconductor chip laminated on the upper surface of the wiring board so that the connection electrodes are exposed;
When two or more semiconductor chips are stacked, from the (n-1) th semiconductor chip (n: 2 to the total number N of stacked semiconductor chips) having the (n-1) th connection terminal formed on the upper surface. An n-th semiconductor chip laminated so that the (n-1) -th connection terminal is exposed on the upper surface of any positive integer between
Between the wiring board and the first semiconductor chip and between the (n-1) th semiconductor chip and the nth semiconductor chip, the (n-1) th semiconductor chip is interposed. A side surface that is inclined in a direction facing upward of the wiring board from the upper surface of the semiconductor chip or the wiring board to an end portion of the upper surface of the nth semiconductor chip or the first semiconductor chip. An adhesive layer;
By sputtering or vapor-depositing a conductive material, the upper surface of the wiring board, the side surface of the adhesive layer, the upper surface of the first semiconductor chip, the side surface of the adhesive layer,..., The side surface of the adhesive layer, the Nth All the connection terminals including the nth connection terminal formed on the upper surface of the nth semiconductor chip and the thin film wiring connected to the connection electrode, which are continuously formed in the order of the upper surface of the semiconductor chip; A semiconductor device comprising: すべての前記半導体チップは、それらをそれぞれ同一方向にずらして直線階段状に積層されており、
前記接続電極およびすべての前記接続端子は、前記半導体チップの積層により生じた直線階段領域において直線上に配置されている
ことを特徴とする請求項６に記載の半導体装置。 All the semiconductor chips are stacked in a linear staircase, shifting them in the same direction,
The semiconductor device according to claim 6, wherein the connection electrode and all the connection terminals are arranged on a straight line in a linear staircase region generated by stacking the semiconductor chips.
JP2007190570A 2007-07-23 2007-07-23 Manufacturing method of semiconductor device, and semiconductor device Withdrawn JP2009027067A (en)

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JP2009054835A (en) * 2007-08-28 2009-03-12 Toshiba Corp Semiconductor device and its manufacturing method
KR101096042B1 (en) 2010-03-18 2011-12-19 주식회사 하이닉스반도체 Semiconductor package and method for manufacturing thereof
CN103081103A (en) * 2010-09-01 2013-05-01 甲骨文国际公司 Manufacturing fixture for a ramp-stack chip package
TWI426593B (en) * 2010-11-18 2014-02-11 矽品精密工業股份有限公司 Chip for use with multi-chip stack package and its stack package structure
KR20140144486A (en) * 2013-06-11 2014-12-19 에스케이하이닉스 주식회사 Stack package and manufacturing method for the same
JP2016533640A (en) * 2013-10-21 2016-10-27 オラクル・インターナショナル・コーポレイション Techniques for controlling the position of stacked dies

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009054835A (en) * 2007-08-28 2009-03-12 Toshiba Corp Semiconductor device and its manufacturing method
KR101096042B1 (en) 2010-03-18 2011-12-19 주식회사 하이닉스반도체 Semiconductor package and method for manufacturing thereof
US8319327B2 (en) 2010-03-18 2012-11-27 SK Hynix Inc. Semiconductor package with stacked chips and method for manufacturing the same
CN103081103A (en) * 2010-09-01 2013-05-01 甲骨文国际公司 Manufacturing fixture for a ramp-stack chip package
TWI426593B (en) * 2010-11-18 2014-02-11 矽品精密工業股份有限公司 Chip for use with multi-chip stack package and its stack package structure
KR20140144486A (en) * 2013-06-11 2014-12-19 에스케이하이닉스 주식회사 Stack package and manufacturing method for the same
KR102001880B1 (en) 2013-06-11 2019-07-19 에스케이하이닉스 주식회사 Stack package and manufacturing method for the same
JP2016533640A (en) * 2013-10-21 2016-10-27 オラクル・インターナショナル・コーポレイション Techniques for controlling the position of stacked dies

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