TWI421948B - 具改良性能之功率半導體裝置及其方法 - Google Patents

具改良性能之功率半導體裝置及其方法 Download PDF

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TWI421948B
TWI421948B TW095111827A TW95111827A TWI421948B TW I421948 B TWI421948 B TW I421948B TW 095111827 A TW095111827 A TW 095111827A TW 95111827 A TW95111827 A TW 95111827A TW I421948 B TWI421948 B TW I421948B
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doped region
semiconductor device
region
layer
substrate
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TW200723409A (en
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Gary H Loechelt
Peter J Zdebel
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Semiconductor Components Ind
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Description

具改良性能之功率半導體裝置及其方法
本發明大抵關於半導體裝置，且更明確為關於包括高速裝置例如RF放大器在內之功率切換裝置，及其製造方法。
金屬氧化物半導體場效電晶體(MOSFETs)係一普遍之功率切換裝置類型。一MOSFET裝置包括一源極區、一汲極區、一延伸於源極與汲極區之間之通道區、及一鄰接於通道區之閘極結構。閘極結構包括一傳導性閘極，其係由一薄介電層鄰接於且分隔於通道區。
當一MOSFET裝置在on狀態時，一電壓施加於閘極結構，以利於源極與汲極區之間形成一傳導通道區，供電流流過該裝置。在off狀態時，施加於閘極結構之任意電壓相當低，因此一傳導通道並未形成，即不發生電流流動。在off狀態期間，該裝置需支援源極與汲極區之間之一高電壓。
在將MOSFET裝置之性能最佳化時，設計者常面對裝置參數性能之取捨。更明確地說，目前可用之裝置結構或製程選擇可以改良一項裝置參數，但是此項選擇同時會減弱一或多項其他裝置參數。例如，足以改良輸出或驅動電流(ID S )能力及一MOSFET裝置之on電阻的目前可用結構或製程亦降低其崩潰電壓(BVD S S )能力及增加閘極－汲極電容。
據此，改良之半導體裝置結構及其製造方法係解決上述議題及其他事項所必需者。
為了方便瞭解，圖中之元件並未依比例繪製，且相同之元件編號係適度使用在諸圖中。儘管文後之探討揭述一n通道裝置，本發明亦關於p通道裝置，其可以藉由將該等層及區域之傳導性型式相反而形成。
此外，本發明之裝置可以具體實施於一細胞式設計(其中該等主體區為複數個細胞區)或一單一主體設計(其中該主體區係由形成於一長形圖案中之單一區域構成，典型上為一彎曲形圖案)。惟，本發明之裝置將在本文內以一細胞式設計揭述之，以便於瞭解。應該瞭解的是本發明應涵蓋一細胞式設計及一單一基底設計二者。
圖1揭示根據本發明之一實施例之一絕緣閘極場效電晶體(IGFET)、MOSFET、功率電晶體、或切換裝置或單元10之局部放大截面圖。舉例而言，在許多該等裝置之中，裝置10係與邏輯器及/或其他組件整合至一半導體晶片內，而成為一功率積體電路之一部分。另者，在許多該等裝置之中，裝置10被整合以形成一不連續之電晶體裝置。
裝置10包括一半導體材料區11，其例如包含一具有大約0.001至0.005歐姆－厘米範圍電阻係數之n型矽基板12，且可以摻雜砷。在所示之實施例中，基板12提供一汲極接點或一第一電流攜載接點。一半導體層或延伸之汲極區14形成於基板12內或其上。在一實施例中，半導體層14係使用習知磊晶生長技術形成。另者，半導體層14係使用習知摻雜與擴散技術形成。在一適用於一50伏特裝置之實施例中，半導體層14係n型且有一大約1.0×1015 原子/立方厘米之摻雜物濃度，及其具有一大約3至5微米厚度。半導體層14之厚度及摻雜物濃度係依據裝置10之所需BVDSS 比率而增減。可以瞭解的是其他材料也可用於半導體材料11之主體或其部分，包括矽鍺、矽鍺碳、摻碳之矽、碳化矽、或類此者。此外，在可替代實施例中，基板12之傳導性型式被換成相反於半導體層14之傳導性型式，以形成一絕緣閘極雙極電晶體10。
裝置10亦包括一n型區或氈層17，其形成於半導體材料區11之上或主表面18內或其鄰側。n型區17提供一用於裝置10之低電阻電流路徑。在一示範性實施例中，n型區17具有一大約6.0×1016 原子/立方厘米之最大濃度，及一大約0.4微米深度。
一主體、基底、或主體區31形成於半導體層14內且延伸自主表面18。舉例而言，主體區31包含p型傳導性，且其具有一適於形成一逆向層之摻雜物濃度，該逆向層操作如同裝置10之傳導通道45。主體區31係從主表面18延伸一例如大約0.5至3.0微米深度。一n型源極區、電流傳導、或電流攜載區33形成於主體區31內，且從主表面18延伸一例如大約0.1至0.5微米之深度。一p型主體接點或接觸區36亦形成於主體區31內，且其提供一較低接觸電阻於主表面18處之主體區31。此外，接觸區36降低源極區33下方之主體區31之片電阻係數，抑制寄生雙極效應。
一第一介電層41形成於主表面18之上方或鄰接於其一部分。例如，介電層41包含一具有大約0.05至0.2微米厚度之熱氧化物層。一第二介電層42形成於介電層41上方。在一實施例中，第二介電層42包含氮化矽，且具有大約0.05至0.1微米厚度。
閘極介電層43形成於與主體區31相鄰之主表面18上方或鄰接於該主表面18之其它部分。閘極介電層43例如包含氧化矽，且具有大約0.01至0.1微米厚度。在可替代實施例中，閘極介電層43包含氮化矽、過氧化鉭、二氧化鈦、鈦酸鍶鋇或其組合，包括其與氧化矽之組合，或類此者。
傳導性填隙物閘極區、垂直填隙物閘極區、或填隙物界定之閘極區或傳導性電極57形成於閘極介電層43上方，且其利用介電質填隙物59而隔離於傳導層46。傳導性填隙物閘極區57連同閘極介電層43一起形成一控制電極或閘極結構58。傳導性填隙物閘極區57例如包含n型多晶矽或聚矽，且其厚度大約0.2至0.8微米。在一示範性實施例中，介電質填隙物59包含氮化矽，且其厚度大約0.1微米。填隙物閘極區57耦合於傳導層53，以提供一傳導性閘極結構，其控制通道45之形成及裝置10內之電流傳導。在所示之實施例中，一傳導性連接部分77將填隙物閘極區57耦合於傳導層53。傳導性連接部分77例如包含n型聚矽。一填隙物界定之閘極區係關於一控制電極，其在一表面上沉積閘極材料，以利控制一形成於另一垂直表面上之通道。在裝置10之例子中，通道45形成於主表面18處，該處可視為一水平表面。用於形成填隙物閘極區57之控制電極膜係沿著與表面18垂直之垂直表面68而沉積。
相較於習知裝置，傳導性填隙物閘極區57提供最小之閘極-汲極重疊，藉此大幅減少閘極電荷。此外，在裝置10中，用於閘極之電氣性路線係由傳導層53提供，其位於主表面18上方，藉此進一步減少閘極電荷。再者，在其他元件中，傳導層46(如下述)之功能有如介置於閘極與汲極之間之一接地平面或遮蔽層，以利於進一步減小閘極至汲極之電容。這些特性提供增強之切換速度及減低之輸入電荷要求。
根據本發明，傳導層或摻雜之多晶性半導體層46形成於介電層41、42上方，且其耦合至一形成於半導體材料11之主體內的摻雜區或反摻雜汲極區23。在一示範性實施例中，傳導層46包含一大約0.1微米厚度之聚矽層，且具有一用於一n通道裝置之p型傳導性。當熱處理時，來自傳導層46之p型摻雜物擴散入半導體材料11之主體，以形成摻雜區23。在一可替代實施例中，摻雜區23係使用離子植入技術形成。在一可替代實施例中，傳導層46包含非晶矽、一金屬、一矽化物、或其組合，包括其與聚矽之組合。若一金屬被用於傳導層46，p型摻雜物即先植入或沉積於半導體材料11之主體內，以形成摻雜區23，傳導層46仍呈浮動或耦合於一固定電壓，例如VS 或接地。
根據本發明，摻雜區23係相隔一距離26，且相同於主體區31至汲極接面深度27之距離。在一實施例中，摻雜區23係與主體區31相隔一大約0.5至3.0微米之距離26。在一實施例中，摻雜區23係設在一未曝露於高電流量之半導體層 14部分內，以避免衝擊到汲極電流特徵。在又一實施例中，該等摻雜區23係與一位於摻雜區23中點處之中心線123相隔一距離28。舉例而言，距離28是在一大約0.25至0.8微米範圍內。
一第五介電層61形成於裝置10之一部分上方，且其例如包含具有大約0.05微米厚度之氮化矽。一層間介電質(ILD)層62形成於裝置10之一部分上方，且其例如包含一具有大約0.8微米厚度之沉積氧化矽。一開孔形成於該等介電層內，以提供裝置10一用於源極接觸層63之接點。如圖所示，主表面18之一部分被蝕刻以利源極接觸層63接觸於源極區33及主體區31。在一實施例中，源極接觸層63包含一鋁矽合金或類此者。一汲極接觸層或傳導電極66形成於半導體材料區11之一相對立表面上，且其例如包含一可熔接之金屬結構，例如鈦鎳銀、鉻鎳金、或類此者。
裝置10之操作過程如下。假設源極或輸入端63係以一0伏特電位VS 操作，則填隙物閘極區57接收到一控制電壓VG =2.5伏特，其較大於裝置10之傳導臨界值，汲極或輸出端66則以汲極電位VD =5.0伏特操作。VG 及VS 等值使主體區31在填隙物閘極區57下方轉變而形成通道45，其將源極區33電氣性連接於層17。一裝置電流IDS 從源極端63流出，且選路通過源極區33、通道45、層17、及半導體層14到達汲極端66。在一實施例中，IDS =1.0安培。欲將裝置10切換至off狀態時，一小於該裝置傳導臨界值之控制電壓VG 施加於填隙物閘極57(例如，VG <2.5伏特)。此將通道45去除，且ID S 不再流過裝置10。
根據本發明，摻雜區23之功能在改良汲極區或半導體層14內所形成之電場之平面性，及進一步減少在主體區31內由一高汲極電壓所感應生成之耗盡區電荷。此昇高了裝置10之崩潰電壓。
圖2係一圖表，揭示在一5.0伏特之偏壓VG S 下且傳導層46接至VS ，裝置10之汲極電流ID S a t 性能成為崩潰電壓(BVD S S )之函數。圖2進一步說明ID S a t 成為摻雜區23之多數個距離28(如圖1所示)之函數，如下：資料點1A對應於無摻雜區23，資料點2A對應於0.5微米之距離28，資料點3A對應於0.6微米之距離28，資料點4A對應於0.7微米之距離28，資料點5A對應於0.8微米之距離28。如圖2所示，摻雜區23改良崩潰電壓性能，且未嚴重衝擊到ID S a t 性能。
圖3係一圖表，揭示在一5.0伏特之偏壓VG S 下且傳導層46接至VS ，on狀態中之汲極電阻(Rdson)成為崩潰電壓(BVD S S )之函數。圖3進一步說明Rdson性能成為摻雜區23之距離28之函數。資料點1B－5B對應於圖2所示之點1A－5A。如圖3所示，摻雜區23改良裝置10之崩潰電壓，且未嚴重衝擊到on狀態中之汲極電阻。
圖4係一圖表，揭示在一30.0伏特之偏壓VD S 、一2.0伏特之VG S 下且傳導層46接至VS ，個體電流增益之頻率(fTau)成為崩潰電壓(BVD S S )之函數。圖4進一步說明fTau性能成為摻雜區23之寬度28之函數。資料點1C－5C對應於圖2所示相同距離28之點1A－5A。如圖4所示，摻雜區23改良裝置10之崩潰電壓，且未嚴重衝擊到個體電流增益之頻率。
請即參閱圖5－9，一種用於形成本發明之裝置10之方法將說明於後。圖5揭示裝置10在一初期製造階段時之局部放大截面圖。第一介電層41形成於主表面18上方，且其例如包含一大約0.05至0.2微米厚之氧化矽。一在大約攝氏900度時生長之熱氧化物亦適合。其次，第二介電層42形成於介電層41上方，且其例如包含大約0.05至0.1微米之氮化矽。開孔44隨後形成於介電層41、42之一部分內，以曝露主表面18之一部分。開孔44係使用習知微影蝕刻技術形成。
傳導層46接著形成於第二介電層42上方及開孔44內，使傳導層46之一部分係鄰接於主表面18。當裝置10包含一n通道裝置時，傳導層46包含大約0.1微米之p型聚矽，且可沉積摻雜或不摻雜。若傳導層46初期為沉積不摻雜，傳導層46隨後即使用例如離子植入技術而摻雜。在一實施例中，傳導層46係以一硼離子植入摻雜。一大約5.0×101 5 至1.0×101 6 原子/平方厘米之劑量且一大約30 KeV植入能量即足以將傳導層46摻雜。在一實施例中，傳導層46內之硼摻雜物將從傳導層46擴散入半導體材料11之主體，以形成摻雜區23。在一可替代實施例中，p型摻雜物係在傳導層46沉積前先被離子植入或沉積於開孔44內。
其次，第三介電層48形成於傳導層46上方，且第四介電層51形成於第三介電層48上方。第三介電層48例如包含氮化矽(例如大約0.05微米厚度)，且介電層51包含一沉積之氧化物(例如大約0.7微米厚度)。傳導層53接著形成於第四介電層51上方，且其例如包含n型聚矽(例如大約0.3微米厚度)。一保護層54形成於傳導層53上方，且其例如包含大約0.15微米氮化矽。
一微影蝕刻步驟被執行以蝕刻通過諸層54、53、51、48、46及42，而提供一開孔70。此亦形成基座式堆疊結構56，其係由諸層42、46、48、51、53及54之其餘部分組成。在一實施例中，開孔70具有一大約5.0至8.0微米寬度73。
圖6揭示裝置10在形成介電質填隙物59之其他加工步驟後之局部放大截面圖。在一實施例中，一氮化矽膜沉積於基座式堆疊結構56與第一介電層41上方。舉例而言，一大約0.1微米厚之氮化矽膜使用化學氣相沉積技術沉積。其次，一習知非等向性回蝕步驟被用於將基座式堆疊結構56與第一介電層41上方之氮化矽層去除，同時將該氮化矽層之一部分留在側壁或垂直表面68上，以形成介電質填隙物59。
在另一步驟中，一氧化矽濕化學蝕刻接著被用於將開孔70內之介電層41部分去除。舉例而言，一稀釋之氫氟酸(例如50：1)被用於蝕刻介電層41。在一示範性實施例中，蝕刻時間加長(例如8至15分鐘)，以利於從介電質填隙物59下方將介電層41下切或去除材料，以形成凹部74。依此方式凹陷之介電層41可確保主體區31內所形成之通道45(如圖1所示)延伸入半導體層14，以供通道電流較有效率地流動。在一示範性實施例中，凹部74係在介電質填隙物59下方凹陷一小於約0.1微米之距離。一熱氧化矽接著在開孔70內之主表面18上生長至一大約0.0125微米厚度，以形成閘極介電層43。
圖7揭示裝置10在其他加工後之局部放大截面圖。一順應性半導體材料層571係在裝置10上方沉積至一大約0.1至0.15微米厚度。硼摻雜物隨後被導入通過開孔70及順應性半導體材料層571且進入主表面18，以提供p型摻雜物於主體區31。舉例而言，順應性半導體材料層571包含未摻雜之聚矽，且硼被植入通過未摻雜之聚矽且進入半導體層14。一大約1.0×101 3 原子/平方厘米之劑量及一大約120 KeV植入能量即適用於一50伏特裝置。
圖8揭示裝置10在其他加工後之局部放大截面圖。一第二順應性半導體材料層隨後沉積於順應性半導體材料層571上方，且此二層皆被蝕刻以提供填隙物閘極57。舉例而言，該第二順應性半導體材料層包含大約0.2微米之n型聚矽，其可在沉積期間摻雜或隨後利用離子植入或其他摻雜技術摻雜。填隙物閘極57形成後，另一0.015微米之閘極介電質(例如，氧化矽)添加至填隙物閘極57之表面及閘極氧化物43之曝露部分。
在一實施例中，形成填隙物閘極57之蝕刻步驟亦將保護層54及介電質填隙物59上方部分曝露。保護層54及介電質填隙物59上方部分接著被蝕刻，使保護層54被去除，且介電質填隙物59上方部分被去除於填隙物閘極57與傳導層53之間。
在又一步驟中，傳導性材料例如聚矽被沉積以提供連接傳導性部分77。連接傳導性部分77係填入在保護層54及介電質填隙物59部分之去除期間所形成之該間隙，且將填隙物閘極57耦合於或電氣性連接於傳導層53。一n型摻雜步驟隨後執行以將傳導性連接部分77摻雜，及提供摻雜物於源極區33。在一示範性實施例中，一大約3.0×101 5 原子/平方歷米之砷植入劑量及一大約80 KeV植入能量即用於此摻雜步驟。在一實施例中，一第一退火步驟係在此時使用以激勵及擴散多數個摻雜物，以形成主體區31、摻雜區23及源極區33。舉例而言，裝置10曝露於大約攝氏1030度下約45秒。在一可替代實施例中，摻雜物係在一後續步驟中被激勵及擴散，容後詳述。
圖9揭示裝置10在其他製程步驟後之局部放大截面圖。第五介電層61被沉積，且其例如包含大約0.05微米之氮化矽。ILD層62接著沉積於第五介電層61上方。在一示範性實施例中，ILD層62包含一大約0.8微米厚度之沉積氧化矽。一選項性ILD漸縮形蝕刻被用於使ILD層62之部分62a呈漸縮形，此有助於後續成形層之階梯覆蓋率。
其次，一習知微影蝕刻步驟被用於形成接觸孔81，其曝露出主表面18之一部分。接觸區36隨後使用一p型離子植入步驟而形成通過開孔81。舉例而言，其使用一大約3.0×101 4 原子/平方厘米之硼離子植入劑量及一80 KeV植入能量。一順應性填隙物層接著被沉積及蝕刻，以形成填隙物82。在一示範性實施例中，一0.3微米之氮化矽層被沉積及蝕刻，以形成填隙物82。在一實施例中，一快速退火步驟係在此時使用以激勵及擴散多數個離子植入。例如，裝置10曝露於大約攝氏1030度下約45秒。
一蝕刻步驟隨後被用於去除主表面18之一部分，以形成凹部84。此供源極接觸層63接觸於源極區33與接觸區36，以將該等區域一併縮短。填隙物82接著被移除。在後續之加工中，源極接觸層63被沉積及製圖。基板12接著可選項性薄化，且汲極接觸層66被沉積，以提供如圖1所示之結構。另應瞭解的是其他傳導層例如矽化物層可以在沉積源極接觸層63之前形成。
綜上以觀，本發明顯然已揭露一種新穎裝置及其製造方法。在其他特性之中，其包括一半導體裝置且在裝置之一部分內形成反摻雜之區域。在其他事項之中，該等反摻雜之區域改良了崩潰電壓性能，且不衝擊到輸出電流性能、on狀態電阻、或個體電流增益頻率。
儘管本發明已參考其特定實施例說明及揭示於前，但是本發明不應被拘限於諸揭示實施例。習於此技者可以瞭解到在不脫離本發明範疇下，仍可達成多種修改及變化。因此，本發明應涵蓋文後之請求項範疇內的諸此變化及修改。
10．．．裝置
11．．．半導體材料區
12．．．基板
14．．．半導體層
17．．．n型區
18．．．主表面
23．．．摻雜區
26,28．．．距離
27．．．汲極接面深度
31．．．主體區
33．．．電流攜載區
36．．．接觸區
41．．．第一介電層
42．．．第二介電層
43．．．閘極介電層
44．．．開孔
45．．．傳導通道
46,53．．．傳導層
48．．．第三介電層
51．．．第四介電層
54．．．保護層
56．．．堆疊結構
57．．．填隙物閘極區
58．．．閘極結構
59．．．介電質填隙物
61．．．第五介電層
62．．．層間介電質(ILD)層
62a．．．ILD層之部分
63．．．源極接觸層
66．．．汲極端
68．．．側壁
73．．．寬度
74,84．．．凹部
77．．．傳導性連接部分
81．．．接觸孔
82．．．填隙物
123．．．中心線
571．．．半導體材料層
圖1揭示根據本發明之一實施例之一半導體結構之局部放大截面圖；電流(ID S a t )成為崩潰電壓(BVD S S )之函數；圖3係一圖表，揭示本發明之多數個實施例之on電阻(RD S O N )及BVD S S 性能；圖4係一圖表，揭示BVD S S 及個體電流增益之頻率(fTau)之間之相互關係；圖5揭示本發明之一實施例在一初期製造階段時之局部放大截面圖；圖6揭示本發明之一實施例在一稍後製造階段時之局部放大截面圖；圖7揭示本發明之一實施例在一更稍後製造階段時之局部放大截面圖；圖8揭示本發明之一實施例在另一製造階段時之局部放大截面圖；及圖9揭示本發明之一實施例在又一製造階段時之局部放大截面圖。
10．．．裝置
11．．．半導體材料區
12．．．基板
14．．．半導體層
17．．．n型區
18．．．主表面
23．．．摻雜區
26,28．．．距離
27．．．汲極接面深度
31．．．主體區
33．．．電流攜載區
36．．．接觸區
41．．．第一介電層
42．．．第二介電層
43．．．閘極介電層
45．．．傳導通道
46,53．．．傳導層
48．．．第三介電層
51．．．第四介電層
57．．．填隙物閘極區
58．．．閘極結構
59．．．介電質填隙物
61．．．第五介電層
62．．．層間介電質(ILD)層
63．．．源極接觸層
66．．．汲極端
68．．．側壁
77．．．傳導性連接部分
123．．．中心線

Claims (20)

  1. 一種半導體裝置，包含：一基板，其具有一主表面，其中該基板包含一第一傳導性型式；一基座結構，其疊覆於該主表面之一部分；一傳導性材料，其沿著該基座結構之一側表面設置，以形成該半導體裝置之一第一傳導電極；一第二傳導性型式之一第一摻雜區，其形成於該基板內且鄰接該主表面及該第一傳導電極，其中當該半導體裝置操作時，該第一摻雜區之一部分形成一通道區；該第一傳導性型式之一電流攜載區，其形成於該第一摻雜區內；該第二傳導性型式之一第二摻雜區，其形成於該基板內且鄰近於該通道區之一汲極緣部，其中當在操作時該第二摻雜區經組態以增強該半導體裝置之崩潰電壓，且其中該第二摻雜區係與該第一摻雜區間隔分開，使得該基板之一部分係在該主表面附近的該第一摻雜區與該第二摻雜區之間；及一第一傳導層，其與該第二摻雜區接觸。
  2. 如請求項1之半導體裝置，其中該基板包括該第一傳導性型式之一半導體層，其形成於該基板上方，其中該半導體層具有一較低於該基板者之摻雜濃度。
  3. 如請求項2之半導體裝置，尚包含該第一傳導性型式之一第三摻雜區，其形成鄰接於該等第一及第二摻雜區之 間之該主表面，其中該第三摻雜區具有一較大於該半導體層者之摻雜濃度。
  4. 如請求項1之半導體裝置，其中該基板之一第二表面形成一第二傳導電極。
  5. 如請求項1之半導體裝置，其中該第二摻雜區耦合於該電流攜載區。
  6. 如請求項1之半導體裝置，其中該第一傳導層包含多晶矽。
  7. 如請求項1之半導體裝置，其中該第二摻雜區係與該第一摻雜區相隔一在大約0.5微米至大約3.0微米範圍內之距離。
  8. 如請求項1之半導體裝置，其中該基座結構包括：一第一介電層，其形成於該基板之該主表面上方；一第二介電層，其形成於該第一介電層上方；及一第二傳導層，其形成於該第二介電層上方，其中該第二傳導層耦合於該第一傳導電極。
  9. 如請求項8之半導體裝置，其中該第二傳導層包括多晶矽。
  10. 一種半導體裝置，包含：一半導體基板；一第一傳導性型式之一半導體層，其形成於該半導體基板上方且具有一主表面；一第二傳導性型式之一主體區，其設置於該半導體層內，用於形成該半導體裝置之一通道； 該第一傳導性型式之一電流傳導區，其形成於該主體區內；一閘極結構，其形成於該主表面上方且鄰接於該通道；該第二傳導性型式之一第一摻雜區，其形成於該半導體層內且鄰近於該主表面，而間隔於該主體區；一第一傳導層，其耦合於該第一摻雜區，用於當該半導體裝置操作時可控制該半導體裝置之崩潰電壓。
  11. 如請求項10之半導體裝置，尚包含該第一傳導性型式之一第二摻雜區，其形成於該主體區與該第一摻雜區之間，其中該第二摻雜區具有一較高於該半導體層者之摻雜物濃度。
  12. 如請求項10之半導體裝置，尚包含一基座結構，其形成於該主表面上方，及其中該閘極結構包括一控制電極，其沿著該基座結構之一側表面而形成。
  13. 如請求項12之半導體裝置，其中該控制電極係延伸過該基座結構，以接收一外部信號(VG )。
  14. 如請求項10之半導體裝置，其中該半導體基板包含該第二傳導性型式。
  15. 如請求項10之半導體裝置，其中當該半導體裝置操作時，該第一摻雜區與該電流傳導區係以相同電位(VS )偏壓。
  16. 一種用於形成一半導體裝置之方法，包含以下步驟：提供一基板，其具有一主表面，其中該基板包含一第 一傳導性型式；將一基座結構形成於該主表面之一部分上；沿著該基座結構之一側表面形成一傳導性材料，其經組態作為該半導體裝置之一第一傳導電極；形成一第二傳導性型式之一第一摻雜區於該基板內且鄰接該主表面及該第一傳導電極，其中當該半導體裝置操作時，該第一摻雜區之一部分形成一通道區；形成該第一傳導性型式之一電流攜載區於該第一摻雜區內；形成該第二傳導性型式之一第二摻雜區於該基板內且鄰近於該通道區之一汲極緣部，其中當在操作時該第二摻雜區經組態以增強該半導體裝置之崩潰電壓，且其中該第二摻雜區係與該第一摻雜區間隔分開，使得該基板之一部分係在該主表面附近的該第一摻雜區與該第二摻雜區之間；及形成一第一傳導層，其與該第二摻雜區接觸。
  17. 如請求項16之方法，其中該提供基板之步驟包括提供一具有該第一傳導性型式半導體層之基板，該半導體層形成於該基板上方，其中該半導體層具有一較低於該基板者之摻雜濃度。
  18. 如請求項17之方法，其中該提供基板之步驟包括提供一含有該第一傳導性型式之一第三摻雜區的基板，該第三摻雜區形成鄰接於該等第一及第二摻雜區之間之該主表面，其中該第三摻雜區具有一較大於該半導體層者之摻 雜濃度。
  19. 如請求項16之方法，尚包含將該第二摻雜區電耦合至該電流攜載區之步驟。
  20. 如請求項16之方法，其中該形成第一傳導層之步驟包含形成一多晶矽層。
TW095111827A 2005-04-25 2006-04-03 具改良性能之功率半導體裝置及其方法 TWI421948B (zh)

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