TWI414024B - 使用原位磊晶生長形成的源極／汲極壓力層 - Google Patents
使用原位磊晶生長形成的源極／汲極壓力層 Download PDFInfo
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Description
本發明大致上係關於半導體裝置，及更具體言之，本發明係關於使用原位磊晶生長形成的源極/汲極壓力層。
此申請案已於2007年7月23日在美國以專利申請案第11/781,610號提出申請。
為自源極/汲極壓力層獲取高通道應變，源極/汲極壓力層應被合併為儘可能地接近於通道。當源極/汲極壓力層在閘相鄰之凹槽內磊晶生長時，在源極/汲極壓力層生長之前凹槽需要進行氫氟酸清洗(HF清洗)。但是，用於HF清洗之材料可侵蝕閘氧化物。為防止HF清洗在閘氧化物上的負面效應，源極/汲極壓力層必須在離通道有一些距離之處形成。源極/汲極區域與通道區域之間的間隔建立了高的串聯電阻。
習用地，源極/汲極區域中的高串聯電阻已藉由在源極/汲極區域中植入摻雜物及對該區域退火來減少。摻雜物植入於源極/汲極區域中可引起其他問題。舉例而言，摻雜物的植入可引起壓力層層體鬆弛。鬆弛之壓力層層體在通道區域中建立較低之應變且因此並非如此有效。另外，植入及退火二者均可導致自通道區域至源極/汲極區域之摻雜輪廓的較小突變。
因此，需要有加應力於通道區域以及使用原位摻雜磊晶生長形成的源極/汲極區域。
本發明提供了半導體裝置，包括其製造方法。例示性半導體裝置包括一具有一高k(高電介質常數)零間隔層的結構，該間隔層與一完全原位摻雜源極/汲極延伸壓力層對準。用以形成凹槽的蝕刻步驟係將高k間隔層用作一遮罩而定義，其中原位摻雜磊晶區域形成於該等凹槽之中。
一方面，本發明提供了一種用於形成一半導體裝置的方法。該方法包括形成一半導體層及在該半導體層上形成一閘結構。該方法進一步包括形成一高k側壁間隔層相鄰於該閘結構。該方法進一步包括在該半導體層中形成一凹槽，該凹槽對準於該高k側壁間隔層。該方法進一步包括在該凹槽中形成一原位摻雜磊晶材料，該磊晶材料具有一與半導體層之晶格常數不同的自然晶格常數，以在半導體裝置之通道區域中建立應力。
另一方面，本發明提供了一種用於形成一半導體裝置的方法。該方法包括形成一半導體層，形成一閘電介質層，以及在該閘電介質層上方形成一閘結構。該方法進一步包括形成一高k側壁間隔層相鄰於該閘結構，該高k側壁間隔層具有一比氮氧化矽之電介質常數更大的電介質常數。該方法進一步包括在該半導體層中形成一凹槽，該凹槽對準於該高k側壁間隔層。該方法進一步包括在該凹槽中形成一原位摻雜磊晶材料，該磊晶材料具有一與半導體層之晶格常數不同的自然晶格常數，以在半導體裝置之通道區域中建立應力。該方法進一步包括形成一間隔層相鄰於該高
k側壁間隔層。該方法進一步包括矽化原位摻雜磊晶材料及閘結構的一部分，其中回應於被施加至閘結構的一偏電壓，一虛源極/汲極延伸區域藉由該高k側壁間隔層而形成。
又一方面，本發明提供了一種半導體裝置，該半導體裝置包括一半導體層及在該半導體層上方形成的一閘電介質。該半導體裝置進一步包括一相鄰於閘結構的高k側壁間隔層，該高k側壁間隔層具有一比氮氧化矽之電介質常數更大的電介質常數。該半導體裝置進一步包括在半導體層中形成的一凹槽，該凹槽對準於該高k側壁間隔層。該半導體裝置進一步包括在該凹槽中的一原位摻雜磊晶材料，該磊晶材料具有一與半導體層之晶格常數不同的自然晶格常數，以在半導體裝置之通道區域中建立應力。
圖1顯示了一半導體裝置10在一處理步驟期間的一視圖。半導體裝置10可包含使用半導體材料於一基板12上方之一埋入氧化層(BOX)14之上所形成的一裝置。此處所述之半導體材料可為任何半導體材料或材料之組合，諸如砷化鎵、矽鍺、矽，類似物及以上之組合。半導體裝置10此外可包含一半導體層16。半導體層16可被摻雜以形成一p型層或形成一n型層。半導體層可使用一隔離區域18自其他半導體層隔離。作為第一步，一閘電介質層20可被形成於半導體層16之上方。閘電介質層20可使用化學氣相沈積或物理氣相沈積方法而被沈積。閘電介質層20可為使用
鉿、鋁、鉬、鈦、鉭、鋯、矽或任何其他適合元素之氧化物所形成的一高k電介質層。閘電介質層20亦可為一熱生長或一沈積氧化矽層。閘電介質層20亦可含有氮。閘電介質層20亦可為一沈積氧化矽層及一沈積高k電介質層的組合。閘電介質層20可具有範圍在1至5奈米的一厚度。閘結構22可被形成於閘電介質層20上方。閘結構22可為僅具有一單一多晶矽層的一多晶矽閘結構。閘結構22亦可為一單一金屬層。或者，閘結構22可為包括多晶矽及/或金屬層的一多層結構。
接著，如圖2所示，一側壁間隔層24可相鄰於閘結構22而形成。側壁間隔層24可使用一高k電介質材料形成。如此處使用的，術語"高k電介質"包括電介質常數大於氮化矽之電介質常數的材料、電介質常數大於7(較佳地，7.5)的材料，或者電介質常數大於氮氧化物之電介質常數的材料。在另一實施例中，高k電介質材料可具有大於10的一電介質常數。在一實施例中，側壁間隔層24必須具有比氮化矽之電介質常數更大的一電介質常數。側壁間隔層24可自一種材料形成，該材料包含由鉭、鋯、鉿、鑭、釔及鍶所組成之群中的一個或多個。側壁間隔層24可由鉭、鋯或鉿之氧化物或矽酸鹽之材料形成。側壁間隔層24可由鑭、釔或鍶之氧化物的材料形成。側壁間隔層24可具有範圍在4至6奈米的一厚度。或者，側壁間隔層24可具有範圍在2至10奈米的一厚度。側壁間隔層24在其之下建立一較低電阻區，其可被視為建立一虛源極/汲極延伸區域。換而言
之，與一實際源極/汲極延伸相同之效應係使用該虛源極/汲極延伸來達成，該虛源極/汲極延伸係在一偏電壓被施加至閘結構22時被建立。
接著，如圖3所示，一凹槽26及一凹槽28可被形成於半導體材料層16中。凹槽26可被形成於源極側上且形成為對準側壁間隔層24。凹槽28可被形成於汲極側上且形成為對準側壁間隔層24。可將側壁間隔層24及閘結構22作為一遮罩使用以及蝕刻半導體材料16來形成凹槽26及凹槽28。
接著，如圖4所示，原位摻雜磊晶區域30及32可分別被形成於凹槽26及凹槽28中。在半導體裝置10係一P通道裝置的一實施例中，原位摻雜磊晶區域30及32可包括原位摻雜有由硼、BF2及銦所組成之群中之一個的矽鍺。在半導體裝置10係一N通道裝置的另一實施例中，原位摻雜磊晶區域30及32可包括原位摻雜有由磷、砷及銻所組成之群中之一個的矽碳。
接著，如圖5所示，側壁間隔層34可相鄰於側壁間隔層24而形成。側壁間隔層34較佳地為氮化物，但亦可為另一材料或材料之組合。側壁間隔層34較佳地比側壁間隔層24更厚。舉例而言，側壁間隔層34可具有一在最厚點為大約40奈米之橫向厚度。
接著，如圖6所示，矽化物區域36、38及40可被形成。雖然未顯示，但可執行進一步的半導體處理步驟，包括電介質間層、接觸件、深源極/汲極區域的形成。
圖7顯示了一半導體裝置50在一處理步驟期間的一視
圖。舉例而言，繼圖4所示之處理步驟之後，半導體裝置10可經受圖7所示之步驟。特定言之，半導體裝置50可藉由蝕刻側壁間隔層24而形成，得到漸縮式側壁間隔層52，顯示於圖7中。任何蝕刻方法諸如濕或乾蝕刻可被使用。側壁間隔層24的蝕刻將減少間隔層相關聯之寄生電容。
接著，如圖8所示，側壁間隔層54可相鄰於側壁間隔層52而形成。側壁間隔層54較佳地為氮化物，但亦可為另一材料或材料之組合。
接著，如圖9所示，矽化物區域56、58及60可被形成。雖然未顯示，但可執行進一步的半導體處理步驟，包括電介質間層、接觸件、深源極/汲極區域的形成。
雖然本發明已就特定導電性類型或電位之極性進行描述，但熟練技術者應了解導電性類型或電位之極性可被反轉。
雖然此處本發明係參考特定實施例來描述，但在不脫離如下文申請專利範圍中所闡述之本發明的範疇下，可做出多種修飾及變化。舉例而言，雖然對於形成半導體裝置10及50之處理步驟係描述為以一特定之順序執行，但其等不必按所描述之順序執行。因此，說明書及圖式應視為說明性而非限制性意義，且希望所有此種修飾被包括在本發明之範疇內。此處關於特定實施例所描述之問題的任何優點、優勢或解決辦法不應被視為任何或所有請求項的關鍵、必要或基本特徵或要素。
此外，如此處所使用的，術語"一"或"一個"被定義為一
個或多個。又，請求項中諸如"至少一個"及"一個或多個"之引導性片語的使用，不應被視為暗示藉由不定冠詞"一"或"一個"之另一請求項元件的引導將含有此種已引導請求項元件的任何特定請求項限制於僅含有此種元件之發明，即使當相同請求項包括引導性片語"一個或多個"及"至少一個"以及不定冠詞諸如"一"或"一個"。對於定冠詞的使用也是如此。
除非另外有說明，術語諸如"第一"及"第二"被用於在此等術語描述之元件之間做出任意辨別。因此，此等術語不必意為指示此等元件的時序或其他優先性。
10‧‧‧半導體裝置
12‧‧‧基板
14‧‧‧埋入氧化層(BOX)
16‧‧‧半導體材料層
18‧‧‧隔離區域
20‧‧‧閘電介質層
22‧‧‧閘結構
24‧‧‧側壁間隔層
26‧‧‧凹槽
28‧‧‧凹槽
30‧‧‧原位摻雜磊晶區域
32‧‧‧原位摻雜磊晶區域
34‧‧‧側壁間隔層
36‧‧‧矽化物區域
38‧‧‧矽化物區域
40‧‧‧矽化物區域
50‧‧‧半導體裝置
52‧‧‧側壁間隔層
54‧‧‧側壁間隔層
56‧‧‧矽化物區域
58‧‧‧矽化物區域
60‧‧‧矽化物區域
本發明經由實例來說明，且不受附圖限制，附圖中相同參考數字指示相似元件。圖中元件僅為簡潔及明確起見而繪示及不必按比例繪製。
圖1係一半導體裝置在一處理步驟期間的一視圖；圖2係一半導體裝置在一處理步驟期間的一視圖；圖3係一半導體裝置在一處理步驟期間的一視圖；圖4係一半導體裝置在一處理步驟期間的一視圖；圖5係一半導體裝置在一處理步驟期間的一視圖；圖6係一半導體裝置在一處理步驟期間的一視圖；圖7係一半導體裝置在一處理步驟期間的一視圖；圖8係一半導體裝置在一處理步驟期間的一視圖；及圖9係一半導體裝置在一處理步驟期間的一視圖。
10‧‧‧半導體裝置
12‧‧‧基板
14‧‧‧埋入氧化層(BOX)
16‧‧‧半導體材料層
18‧‧‧隔離區域
20‧‧‧閘電介質層
22‧‧‧閘結構
24‧‧‧側壁間隔層
30‧‧‧原位摻雜磊晶區域
32‧‧‧原位摻雜磊晶區域
34‧‧‧側壁間隔層
36‧‧‧矽化物區域
38‧‧‧矽化物區域
40‧‧‧矽化物區域
Claims (5)
- 一種用於形成一半導體裝置的方法，其包含：形成一半導體層；在該半導體層上形成一閘電介質層；在該閘電介質層上形成一閘結構；形成一高k側壁間隔層相鄰於該閘結構，該高k側壁間隔層具有一比氮氧化矽之一電介質常數更大之電介質常數；使用該高k側壁間隔層以在該半導體層中形成一凹槽，其中，該凹槽對準於該高k側壁間隔層且未底切該高k側壁間隔層；及在該凹槽中形成一原位摻雜磊晶材料，該磊晶材料具有與該半導體層之一晶格常數不同的一自然晶格常數，以在半導體裝置之一通道區域中建立應力；在該凹槽中形成該原位摻雜磊晶材料之後，蝕刻該高k側壁間隔層以形成一錐形高k側壁間隔層；形成一間隔層相鄰於該錐形高k側壁間隔層；且矽化該原位摻雜磊晶材料的一部分及該閘結構。
- 一種用於形成一半導體裝置的方法，其包含：形成一半導體層；在該半導體層上方形成一閘電介質層；在該閘電介質層上方形成一閘結構；形成一高k側壁間隔層相鄰於該閘結構，該高k側壁間隔層具有一比氮氧化矽之一電介質常數更大的電介質常數； 使用該高k側壁間隔層以在該半導體層中形成一凹槽，其中該凹槽對準於該高k側壁間隔層且未底切該高k側壁間隔層；在該凹槽中形成一原位摻雜磊晶材料，該磊晶材料具有與該半導體層之一晶格常數不同的一自然晶格常數，以在半導體裝置之一通道區域中建立應力；在該凹槽中形成該原位摻雜磊晶材料之後，蝕刻該高k側壁間隔層以形成一錐形高k側壁間隔層；形成一間隔層相鄰於該錐形高k側壁間隔層；及矽化該原位摻雜磊晶材料的一部分及該閘結構；其中該半導體裝置係為一P型通道裝置，且其中該原位摻雜磊晶材料包含原位摻雜有由硼、BF2及銦所組成之群中之一個的矽鍺。
- 一種用於形成一半導體裝置的方法，其包含：形成一半導體層；在該半導體層上方形成一閘電介質層；在該閘電介質層上方形成一閘結構；形成一高k側壁間隔層相鄰於該閘結構，該高k側壁間隔層具有一比氮氧化矽之一電介質常數更大的電介質常數；使用該高k側壁間隔層以在該半導體層中形成一凹槽，其中該凹槽對準於該高k側壁間隔層且未底切該高k側壁間隔層；在該凹槽中形成一原位摻雜磊晶材料，該磊晶材料具 有與該半導體層之一晶格常數不同的一自然晶格常數，以在半導體裝置之一通道區域中建立應力；在該凹槽中形成該原位摻雜磊晶材料之後，蝕刻該高k側壁間隔層以形成一錐形高k側壁間隔層；形成一間隔層相鄰於該錐形高k側壁間隔層；及矽化該原位摻雜磊晶材料的一部分及該閘結構；其中該半導體裝置係為一N型通道裝置，且其中該原位摻雜磊晶材料包含原位摻雜有由磷、砷及銻所組成之群中之一個的矽碳。
- 一種用於形成一半導體裝置的方法，其包含：形成一半導體層；在該半導體層上方形成一閘電介質層；在該閘電介質層上方形成一閘結構；形成一高k側壁間隔層相鄰於該閘結構，該高k側壁間隔層具有一比氮氧化矽之一電介質常數更大的電介質常數；使用該高k側壁間隔層以在該半導體層中形成一凹槽，其中該凹槽對準於該高k側壁間隔層且未底切該高k側壁間隔層；在該凹槽中形成一原位摻雜磊晶材料，該磊晶材料具有與該半導體層之一晶格常數不同的一自然晶格常數，以在半導體裝置之一通道區域中建立應力；在該凹槽中形成該原位摻雜磊晶材料之後，蝕刻該高k側壁間隔層以形成一錐形高k側壁間隔層； 形成一間隔層相鄰於該錐形高k側壁間隔層；及矽化該原位摻雜磊晶材料的一部分及該閘結構；其中當一偏電壓被施加至該閘結構時，該高k側壁間隔層在其之下形成一虛源極/汲極延伸區域。
- 一種用於形成一半導體裝置的方法，其包含：形成一半導體層；在該半導體層上方形成一閘電介質層；在該閘電介質層上方形成一閘結構；形成一高k側壁間隔層相鄰於該閘結構，該高k側壁間隔層具有一比氮氧化矽之一電介質常數更大的電介質常數；使用該高k側壁間隔層以在該半導體層中形成一凹槽，其中該凹槽對準於該高k側壁間隔層且未底切該高k側壁間隔層；在該凹槽中形成一原位摻雜磊晶材料，該磊晶材料具有與該半導體層之一晶格常數不同的一自然晶格常數，以在半導體裝置之一通道區域中建立應力；在該凹槽中形成該原位摻雜磊晶材料之後，蝕刻該高k側壁間隔層以形成一錐形高k側壁間隔層；形成一間隔層相鄰於該錐形高k側壁間隔層；矽化該原位摻雜磊晶材料的一部分及該閘結構；及蝕刻該高k側壁間隔層以形成一錐形側壁間隔層。
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| US6949482B2 (en) * | 2003-12-08 | 2005-09-27 | Intel Corporation | Method for improving transistor performance through reducing the salicide interface resistance |
| US7365378B2 (en) * | 2005-03-31 | 2008-04-29 | International Business Machines Corporation | MOSFET structure with ultra-low K spacer |
| CN1941296A (zh) * | 2005-09-28 | 2007-04-04 | 中芯国际集成电路制造(上海)有限公司 | 应变硅cmos晶体管的原位掺杂硅锗与碳化硅源漏极区 |
| US7384835B2 (en) * | 2006-05-25 | 2008-06-10 | International Business Machines Corporation | Metal oxide field effect transistor with a sharp halo and a method of forming the transistor |
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2007
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2008
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| TW200307331A (en) * | 2002-05-22 | 2003-12-01 | Hitachi Ltd | Metal insulator semiconductor type semiconductor device and its manufacturing method |
| US20050130432A1 (en) * | 2003-12-11 | 2005-06-16 | Machala Charles F.Iii | Method for improving transistor leakage current uniformity |
Also Published As
| Publication number | Publication date |
|---|---|
| US20090026554A1 (en) | 2009-01-29 |
| US7833852B2 (en) | 2010-11-16 |
| TW200917376A (en) | 2009-04-16 |
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