TWI408767B - A substrate processing apparatus, and a substrate processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance working ratio in each processing chamber and thereby enhance throughput of an entire processing apparatus by matching the timing of transferring wafers from cassette containers with the processing time at each processing chamber. <P>SOLUTION: The substrate processing apparatus 100 comprises a processing unit 110 having a plurality of processing chambers 140A, 140B (P1, P2) for applying given processing to wafers, a transfer unit 120 connected to the processing unit 110, a transfer unit side transfer mechanism 170 for transferring the wafers contained in cassette containers 134A, 134B to the processing unit, and a processing unit side transfer mechanism 180 for transferring the wafers transferred from the transfer unit to the processing chambers. A control unit 190 is provided that obtains wafer transferring timing for each processing chamber for transferring the wafers from the cassette containers to each processing chamber, based on processing times T<SB>P1</SB>, T<SB>P2</SB>of the wafers W<SB>P1</SB>, W<SB>P2</SB>in each processing chamber P1, P2, and transfers the wafers from the cassette containers according to the transfer timing. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

Substrate processing device and substrate processing method

The present invention relates to a substrate processing apparatus and a substrate transfer method of a substrate processing apparatus that perform a specific process on a substrate to be processed such as a semiconductor wafer or a glass substrate (for example, a liquid crystal substrate).

Such a substrate processing apparatus usually includes a processing unit having a plurality of processing chambers for performing specific processing on a substrate to be processed, for example, a semiconductor wafer (hereinafter simply referred to as "wafer"), and a transfer unit for loading The lock chamber is connected to the processing unit (for example, Patent Document 1).

For example, a cluster tool type substrate processing apparatus, which is, for example, as shown in FIG. 6 of Patent Document 1, airtightly seals a plurality of processing chambers and a load lock chamber around a common transfer chamber formed in a polygonal shape. Connected to form. A processing unit side conveying mechanism including a transfer arm or the like is provided in the common transfer chamber, and the processing unit side transfer mechanism carries out the wafer transfer between the plurality of processing chambers and the load lock chamber. The transport unit is also provided with a processing unit side transport mechanism including a transfer arm, and the wafer is transported between the cassette container (substrate storage container) containing the wafer and the load lock chamber by the processing unit side transport mechanism. Move in and out.

When the substrate processing apparatus applies a specific process to the wafer stored in the cassette container, first, the unloading wafer is carried out by the processing unit side transfer mechanism from the cassette container by the processing unit side transport mechanism. The unprocessed wafer that has been carried out from the cassette container is loaded into a positioning device (for example, an orienter or a pre-alignment stage) provided in the transport unit before being loaded into the lock chamber. The unprocessed wafer after positioning is carried out by the positioning device and carried into the load lock chamber.

The unprocessed wafer loaded into the lock lock chamber is carried out by the processing unit side transport mechanism from the load lock chamber, and is carried into the processing chamber to perform a specific process. After the processing in the processing chamber is completed, the processing completion wafer is carried out by the processing unit side transfer mechanism from the processing chamber, and is returned to the load lock chamber. The process wafer returned to the load lock chamber is returned to the cassette container by the processing unit side transfer mechanism.

In order to improve the processing efficiency in each processing chamber in the substrate processing apparatus, it is preferable to leave the unprocessed wafer as close as possible to the processing chamber, and therefore, the unprocessed wafer is also handled by the cassette container during processing in the processing chamber. The substrates are sequentially carried out so that their wafers stand by in the common transfer chamber, the load lock chamber, and the positioning device. After one wafer processing in the processing chamber is completed, the processed wafer is immediately stored in the cassette container, and the unprocessed wafers in each standby are sequentially transferred to immediately transfer the next unprocessed wafer into the processing chamber.

Further, when wafer processing is performed in parallel in each processing chamber, it is important to determine which transfer timing to carry the wafers processed in each processing chamber from the cassette container when it is desired to increase the efficiency of the processing in each processing chamber. In this regard, when the next unprocessed wafer is carried out from the cassette container, the remaining time of the processing in each processing chamber is compared, and the unprocessed wafer processed in the processing chamber having the shortest remaining time is detected and carried out by the cassette container. . In this case, for example, the processing chamber having the shorter remaining time of the processing can be processed as the next wafer. Therefore, the wafers can be carried out from the cassette container in the order of the remaining time, thereby improving the processing chambers. Product efficiency.

Patent Document 1: JP-A-2002-237507

However, in many cases, different types of processing are performed in each processing chamber, for example, an etching process or a film forming process, and even if the processing conditions are different in the same processing, the wafer processing time of each processing chamber (for example, crystal) The time when the circle is carried into the wafer and the processing is completed and the next wafer can be carried in is often different.

However, in the above-mentioned prior art, when the next unprocessed wafer is carried out from the cassette container, only the remaining time of the processing in each processing chamber is focused, and it is carried out by the cassette container in the order of the remaining time. The processing timing of an unprocessed wafer does not take into account the difference in processing time of each of the processing chambers described above.

Therefore, when the residual time of the wafer processing in the processing chamber having a shorter processing time is shorter than the processing time in which the processing time is shorter, the wafer of the processing chamber having a longer processing time is first carried out by the cassette container. The wafer will stand by for a long time in the common transfer chamber, the load lock chamber, the positioning device, etc., and the wafer in the processing chamber with a short processing time cannot be carried out by the cassette container, that is, the processing efficiency of the processing chamber is lowered. The problem of reduced work efficiency of the entire substrate processing apparatus.

More specifically, for example, when the processing of the processing chamber P1 having a long processing time and the processing of the processing chamber P2 having a short processing time are performed in parallel, if the remaining time of the processing of the processing chamber P1 having a long processing time is short The wafer W _{P 1} processed in the processing chamber P1 becomes the next object to be taken out by the cassette container.

In this case when, for example, the common transfer chamber prior to processing another wafer views of a processing chamber of P1 in the standby state, therefore, even if the end of the processing chamber P1 of the wafer W _{P 1} is unloaded from the cassette container, the Wafer W _{P 1} cannot be processed immediately. This is because even if the wafers that have been in the common transfer chamber, the load lock chamber, and the positioning device are sequentially transported, they are carried out by the cassette container before the processing of the other wafer that has been carried into the processing chamber P1 is completed. The wafer W _{1 is in} a state of being in standby in the common transfer chamber, the load lock chamber, the positioning device, and the like.

Even if the processing of the processing chamber P2 having a short processing time is immediately completed and the processing is not performed, the wafer W _{P 2} processed in the processing chamber P2 having a short processing time cannot be carried out by the cassette container. Therefore, an unnecessary waiting time is generated in the processing chamber P2 having a short processing time, the efficiency of the processing chamber P2 is lowered, and the work efficiency of the entire substrate processing apparatus is lowered.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a substrate processing method for a substrate processing apparatus and a substrate processing apparatus, wherein when the processing substrate is processed in parallel in each processing chamber, the processing timing of the substrate to be processed from the substrate storage container can be matched with each processing. The processing time of the chamber can improve the efficiency of each processing chamber and improve the working efficiency of the entire substrate processing apparatus.

In order to solve the above problems, a substrate processing apparatus according to one aspect of the present invention includes: a processing unit having a plurality of processing chambers for performing specific processing on a substrate to be processed; a transport unit connected to the processing unit; and a transport unit The side transport mechanism is provided in the transport unit, and the processing substrate for accommodating the substrate storage container is transported to the processing unit; and the processing unit side transport mechanism is provided in the processing unit for transporting the transport unit The substrate to be processed is transferred to the processing chamber, and includes control means for calculating, based on a processing time of the substrate to be processed in each of the processing chambers, the processing of each of the processing chambers by the substrate storage container. The transfer timing of the substrate is processed, and the substrate to be processed is carried out from the substrate storage container in accordance with the transfer timing.

In order to solve the above problems, a substrate transfer method of a substrate processing apparatus according to another aspect of the present invention includes a processing unit having a plurality of processing chambers for performing specific processing on a substrate to be processed, and a transport unit connected to the processing The transport unit side transport mechanism is provided in the transport unit, and the processing substrate for accommodating the substrate storage container is transported to the processing unit, and the processing unit side transport mechanism is provided in the processing unit for transporting the transport unit a substrate transfer method of the substrate processing apparatus in which the substrate to be processed is transported to the processing chamber; and the processing of each of the processing chambers by the substrate storage container is calculated for each processing chamber based on the processing time of the processed substrate in each processing chamber When the substrate to be processed is processed by the chamber, the substrate to be processed is transported from the substrate storage container in accordance with the transfer timing.

According to the above-described apparatus or method, according to the processing time of the substrate to be processed in each processing chamber, the substrate to be processed is carried out from the substrate storage container in accordance with the transfer timing calculated in advance in each of the processing chambers. Therefore, when the processed substrate is processed in parallel in each processing chamber, The processing timing of the substrate to be processed from the substrate storage container can be matched with the processing time of each processing chamber, whereby the processing efficiency of each processing chamber can be improved, and the work efficiency of the entire substrate processing apparatus can be improved. For example, the substrate to be processed which is processed in a processing chamber having a long processing time can be carried out from the substrate storage container at a long interval, and the substrate to be processed which is processed in a processing chamber having a short processing time can be carried out from the substrate storage container at a short interval. In this case, the substrate to be processed in the processing chamber having a long processing time has a long waiting time in the common transfer chamber, the load lock chamber, the positioning device, and the like, and the substrate to be processed in the processing chamber having a short processing time cannot be stored in the substrate. The removal of the container can be eliminated, the efficiency of each processing chamber can be improved, and the working efficiency of the entire substrate processing apparatus can be improved.

Further, in the above-described apparatus or method, the transport timing of the substrate to be processed is, for example, the number of carry-out ratios of the substrate to be processed and the carry-out interval in each of the processing chambers when the substrate storage container is carried out. The ratio of the number of substrates to be processed to be processed refers to the ratio of the number of substrates to be processed in each of the processing chambers carried out by the substrate storage container, and the interval at which the substrate to be processed is removed is the processing chamber that is carried out by the substrate storage container. Handle the substrate removal interval.

In this case, it is preferable that the number of times of carrying out the substrate to be processed is determined in each of the processing chambers in each of the sections of the reference carrying-out interval determined by the processing time of the substrate to be processed in each of the processing chambers. The number of sheets to be processed is calculated by the maximum number of substrates to be processed, and the number of sheets to be processed in the respective processing chambers is set to be equal to the number of sheets to be processed in the processing chambers. The processing time of each of the substrates to be processed is shifted by one piece per sheet.

In this method, by calculating the transport timing of the substrate to be processed from the substrate storage container, for example, the processing time of the substrate to be processed in one processing chamber, and the maximum number of processed substrates that can be processed in other processing chambers The treatment can reduce the processing waiting time of each processing chamber, and can improve the efficiency of each processing room. In addition, each of the processing chambers carries out one or a plurality of processed substrates from the substrate storage container at each of the processing chambers. Thus, the transfer timing of the substrates to be processed from the substrate storage container is used for each processing chamber. In the processing of the substrate, for example, the substrate to be processed for each processing chamber is often offset by the offset time of the initial timing generated when the first sheet is transferred. Therefore, the timing at which the substrate to be processed is carried out is not simultaneous. Accordingly, the waiting time caused by the wafer unloading wait does not occur in each processing chamber.

Further, in the above apparatus or method, the ratio of the number of carried out substrates to be processed is determined, for example, based on the processing time of the substrate to be processed in each of the processing chambers, and the processing time of the processing chamber having the longest processing time among the processing chambers is assumed In the case of the above-described reference carry-out interval, the maximum number of substrates to be processed that can be processed in other processing chambers in the interval of the reference carry-out interval is calculated. As described above, the ratio of the number of substrates to be processed is determined based on the reference carry-out interval set by the processing time of the processing chamber which is the longest processing time, and the method for determining the reference carrying interval is easy. Therefore, the number of substrates to be processed is smaller than that. The calculation becomes easy.

Further, in the above apparatus or method, it is preferable that the reference carry-out interval is determined by shortening the waiting time in accordance with the waiting time in each section of the reference carry-out interval of each of the processing chambers. Therefore, the waiting time of each processing chamber can be optimized, and the work efficiency of the entire substrate processing apparatus can be improved.

In order to solve the above problems, a substrate transfer method of a substrate processing apparatus according to another aspect of the present invention is characterized in that a plurality of the substrates to be processed which are accommodated in the substrate storage container are sequentially processed in accordance with a predetermined transfer timing. a substrate transfer method of a substrate processing apparatus that performs processing on the substrate to be processed in parallel in a plurality of processing chambers; the transfer timing has a step of calculating a processing time of the substrate to be processed in each of the processing chambers And a step of calculating the ratio of the number of substrates to be processed in each of the processing chambers in the interval of the determined reference carrying interval; and calculating the carrying out of the processed substrate in each of the processing chambers based on the ratio of the number of substrates to be processed The steps of the interval.

Further, in the above method, the step of calculating the number of times of carrying out the substrate to be processed may include the step of: processing the processing time of processing one sheet of the substrate to be processed in the processing chamber having the longest processing time in each of the processing chambers At the time of the reference carry-out interval, a step of calculating the maximum number n of substrates to be processed that can be processed in another processing chamber in the interval of the reference carry-out interval; and processing of processing one substrate to be processed in the processing chamber having the longest processing time When the time is the reference carry-out interval, the step of calculating the waiting time of the other processing chamber in the section of the reference carrying-out interval is calculated, and when the processing time of the n+1 pieces of the processed substrate is processed as the reference carrying-out interval in the other processing chamber, the calculation is performed. a step of waiting for the processing chamber having the longest processing time in the interval of the reference carry-out interval; and comparing the waiting times of the processing chambers, when the waiting time of the processing chamber having the longest processing time is equal to or less than the waiting time of the other processing chambers, The above-mentioned reference carry-out interval is determined as the processing room having the longest processing time When the processing time of one substrate to be processed is controlled, the ratio of the number of carried out substrates to be processed is set to 1:n, and when the waiting time of the processing chamber having the longest processing time is longer than the waiting time of the other processing chambers, The reference carry-out interval is determined by the processing time of the other processing chambers for processing the n+1 pieces of the substrate to be processed, and the number of times of transporting the substrate to be processed is 1:n+1.

In this case, the step of calculating the carry-out interval of the substrate to be processed may include the step of moving the number of substrates to be processed in the processing chamber having the longest processing time when the number of substrates to be processed is 1:n The interval is the interval at which the reference carry-out interval is carried out one by one, and the number of times of transporting the substrate to be processed in the other processing chamber is set to be n pieces at the reference carry-out interval. When the number of times of transporting the substrate to be processed is 1:n+1, the interval between the number of substrates to be processed in the processing chamber having the longest processing time is set at the reference carry-out interval. The interval at which the one substrate is carried out one by one, and the number of times of transporting the substrate to be processed in the other processing chambers is an interval at which the n+1 sheets are carried out one sheet at a time in each of the processing times at the reference carry-out interval. step.

As described above, the ratio of the number of substrates to be processed is determined based on the reference carry-out interval set by the processing time of the processing chamber which is the longest processing time, and the method for determining the reference carrying interval is easy. Therefore, the number of substrates to be processed is smaller than that. The calculation becomes easy. In addition, the reference carry-out interval is determined, and the waiting time of any one of the processing chamber having the longest processing time and the other processing chamber is minimized, and the transport timing of the substrate to be processed from the substrate storage container is calculated based on the reference carry-out interval (for example, the substrate to be processed) Since the number of unloading ratios and the time between the substrates to be processed are shifted out, the waiting time of each processing chamber can be optimized, and the work efficiency of the entire substrate processing apparatus can be improved.

Further, in the above method, the step of calculating the number of times of carrying out the substrate to be processed may be performed by assuming that the processing time for processing the m-th substrate to be processed in the processing chamber having the longest processing time among the processing chambers is At the time of the reference carry-out interval, a step of calculating the maximum number n of substrates to be processed that can be processed in another processing chamber in the interval of the reference carry-out interval; and processing the m-processed substrates in the processing chamber having the longest processing time When the time is the reference carry-out interval, the step of calculating the waiting time of the other processing chamber in the interval of the reference carrying interval is calculated, and when the processing time of the n+1 pieces of the processed substrate in the other processing chamber is the reference carrying-out interval, Calculating a waiting time of the processing chamber having the longest processing time in the interval of the reference carrying-out interval; and changing the m to calculate the maximum number of substrates n to be processed, the waiting time of the other processing chamber, and the processing time of the processing time being the longest Waiting time of the room, determining the waiting time of the other processing rooms and the above processing time The processing time of the longest processing chamber becomes the minimum m, n steps: and the waiting time of the other processing chambers when the m and n are determined are compared with the waiting time of the processing chamber having the longest processing time, when the processing time is the longest When the waiting time of the processing chamber is equal to or less than the waiting time of the other processing chambers, the reference carrying-out interval is determined as the processing time in which the processing chamber having the longest processing time processes the m-substrate to be processed, and the substrate to be processed is carried out. The ratio is set to m:n. When the waiting time of the processing chamber having the longest processing time is greater than the waiting time of the other processing chambers, the reference carrying out interval is determined as the processing time of the other processing chambers to process n+1 pieces of the processed substrate. At the same time, the ratio of the number of carried out substrates to be processed is m:n+1.

In this case, the step of calculating the carrying-out interval of the substrate to be processed may include the step of moving the number of substrates to be processed in the processing chamber having the longest processing time when the number of substrates to be processed is m:n The interval is such that the m pieces are ejected one by one in each of the processing times at the reference carry-out interval, and the number of times of transporting the substrate to be processed in the other processing chamber is set to be carried out at the reference The interval at which the n pieces are carried out one by one in each of the processing times, and when the number of the substrates to be processed is m:n+1, the number of the substrates to be processed in the processing chamber having the longest processing time is The interval is such that the m pieces are ejected one by one in each of the processing times at the reference carry-out interval, and the number of times of transporting the substrate to be processed in the other processing chamber is set to be carried out at the reference The step of separating the n+1 pieces at intervals of one piece per piece of processing time.

In this case, the number of times of carrying out the substrate to be processed is determined based on the reference carry-out interval set by m times the processing time of the processing chamber having the longest processing time, and the method of determining the reference carry-out interval becomes easy, and therefore, it is processed. It is easy to calculate the number of substrates to be carried out. In addition, the reference carry-out interval is determined, and the waiting time of any one of the processing chamber having the longest processing time and the other processing chamber is minimized, and the transport timing of the substrate to be processed from the substrate storage container is calculated based on the reference carry-out interval (for example, the substrate to be processed) Since the number of unloading ratios and the time between the substrates to be processed are shifted out, the waiting time of each processing chamber can be optimized, and the work efficiency of the entire substrate processing apparatus can be improved.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail. In the present specification and the drawings, constituent elements that have substantially the same functions are denoted by the same reference numerals, and the description thereof will not be repeated.

(Configuration Example of Substrate Processing Apparatus)

First, a substrate processing apparatus according to an embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a schematic configuration diagram of a substrate processing apparatus according to an embodiment of the present invention. The substrate processing apparatus 100 includes a plurality of processing units 110 for performing various processes such as a film formation process and an etching process on a substrate to be processed, for example, a semiconductor wafer (hereinafter simply referred to as "wafer") W, and a transfer unit 120. It is used to carry in and out of the wafer W to the processing unit 110. The transport unit 120 has a transfer chamber 130 that is shared when the wafer W is transported.

The transfer chamber 130 of the transfer unit 120 is composed of, for example, an inert gas such as N ₂ gas or a case in which the clean air is circulated with a substantially polygonal polygonal cross section. A plurality of cassettes 132 (here, 132A and 132B) are provided on one side surface of the long side of the polygonal shape of the cross section of the transfer chamber 130. Each of the cassettes 132A and 132B can carry the cassette containers 134A and 134B as an example of the substrate storage container.

Each of the cassette containers 134A and 134B can be placed in a plurality of stages at equal intervals, and accommodates, for example, a maximum of 25 wafers W, and the inside thereof has a hermetic structure such as a full N ₂ gas atmosphere. The transfer chamber 130 allows the inside of the wafer W to be carried in and out via the gate valves 136A and 136B.

The wafers processed by the processing chambers 140A and 140B to be described later are accommodated in the cassette containers 134A and 134B, respectively. However, if it is known which wafer is processed in which processing chamber, it is not necessary to separately store the wafers processed by the processing chambers 140A and 140B in the individual cassette containers 134A and 134B. For example, one or both of the cassette containers 134A or 134B may be mixed in the wafers processed by the respective processing chambers 140A, 140B. In addition, in the example of FIG. 1, for example, each of the two cassettes 134A and 134B may be placed on each of the cassettes 132A and 132B, but the number of the cassettes and the cassettes is not limited thereto. For example, 3 or more.

At the end of the transfer chamber 130, that is, on one side of the short side forming a substantially polygonal shape of the cross section, an orienter (pre-alignment stage) 137 as a positioning device is provided, and the director 137 is provided with an optical sensor 139 inside. The peripheral portions of the rotating stage 138 and the wafer W can be optically detected. The director 137 is used to detect the orientation plane or the groove of the wafer W and the like.

The processing unit 110 has a processing chamber 140 (140A, 140B) that applies a specific process such as a film forming process (for example, a plasma CVD process) or an etching process (for example, a plasma etching process) to the wafer. The processing performed by each of the 140 transport columns A and B may be the same processing or different processing. Each wafer is subjected to a specific process in each of the processing chambers 140A and 140B in accordance with the display information (process parameters) of the processing of the etching process previously stored in the memory of the control unit. Regarding which processing chamber the wafers are processed, for example, the above process can be used. Parameter judgment. The processing unit 110 includes a common transfer chamber 150 that carries in and out of the wafer W to the processing chambers 140A and 140B. The common transfer chamber 150 is formed in a polygonal shape, for example, a hexagonal shape, and the respective processing chambers 140A and 140B are disposed around the gate valves 144A and 144B.

Each of the processing chambers 140A and 140B applies the same type or different kinds of processing to the wafer W. Mounting stages 142A and 142B on which the wafer W is placed are provided in the respective processing chambers 140A and 140B. Further, the number of the processing chambers 140 is not limited to two, and may be additionally added.

The first and second load lock chambers 160 M and 160 N which are one example of the vacuum preparation chamber connected to the transport unit 120 are disposed around the common transfer chamber 150. Specifically, the first and second load lock chambers 160 M and 160 N are connected to each other via the gate valves (vacuum side gate valves) 154 M and 154 N around the common transfer chamber 150, respectively. The bottom end of the second load lock chambers 160 M and 160 N is connected to the other side of the long side of the substantially polygonal shape of the cross section of the transfer chamber 130 via a gate valve (atmospheric side gate valve) 162 M, 162 N Connected.

The first and second load lock chambers 160 M and 160 N are vacuum-suckable, and have a function of temporarily maintaining the wafer W under pressure adjustment and then transferring it to the second stage. Further, the load lock chambers 160 M, 160 N may have a cooling mechanism or a heating mechanism.

As described above, the common transfer chamber 150 and the respective processing chambers 140A and 140B and the common transfer chamber 150 and the respective load lock chambers 160 M and 160 N are configured to be airtightly opened/closed, and are group-processed. It can be configured to communicate with the common transfer chamber 150 if necessary. Further, the first and second load lock chambers 160 M and 160 N and the transfer chamber 130 are also configured to be airtightly opened/closed.

In the common transfer chamber 150, for example, the processing unit side transfer mechanism 180 composed of a multi-joint arm portion, such as stretching, lifting, and turning, is provided. The processing unit side transport mechanism 180 can access each of the load lock chambers 160 M, 160 N and the respective process chambers 140A, 140B. For example, when the wafer is loaded into each of the load lock chambers 160 M and 160 N, the wafer is carried into the processing chamber 140A or 140B for processing the wafer by the processing unit side transfer mechanism 180.

The processing unit side conveying mechanism 180 is constituted by a two-arm mechanism having two grips, and two wafers can be used at a time. Accordingly, for example, when the wafers are moved in and out of the processing chambers 140A and 140B, the completed wafer and the unprocessed wafer can be exchanged. Further, the grip on the processing unit side conveying mechanism 180 side is not limited to the above, and may be a single arm mechanism having only one grip.

The transport unit side transport mechanism 170 that transports the wafer W in the longitudinal direction (the direction of the arrow in FIG. 1) is provided in the transfer chamber 130. The base 172 to which the transport unit side transport mechanism 170 is fixed is slidably attached to the guide rail 174 which is provided along the longitudinal direction in the center portion of the transport chamber 130. A movable member and a stator of the linear motor are respectively disposed on the base 172 and the guide rail 174. A linear motor drive mechanism 176 for driving the linear motor is provided at an end of the guide rail 174. The control unit 190 is connected to the linear motor drive mechanism 176. Accordingly, the control unit 190 can be driven 176 according to the control signal of the control unit 190, and the transport unit side transport mechanism 170 and the base 172 can be moved in the direction of the arrow along the guide rail 174.

Similarly to the processing unit side transport mechanism 180, the transport unit side transport mechanism 170 is configured by a two-arm mechanism having two grips, and two wafers can be used at a time. Accordingly, for example, when the wafer is carried in and out of the cassette container 134, the director 137, and the load lock chambers 160 M and 160 N, the wafer can be exchanged for in and out. Further, the grip on the processing unit side conveying mechanism 180 side is not limited to the above, and may be a single arm mechanism having only one grip.

In the substrate processing apparatus 100, in addition to the control of each of the transport mechanisms 170 and 180, the gate valves 136, 144, 154, and 162, and the director 137, the transfer timing of the wafer from the cassette container 134 is described later. The control unit 190 that controls or controls the overall operation of the substrate processing apparatus such as the control of carrying out the wafer by the cassette container 134 in accordance with the transfer timing of the wafer. The control unit 190 includes, for example, a microcomputer that constitutes the main body of the control unit 190, a memory for storing various materials, and the like.

(Operation of substrate processing apparatus)

The operation of the substrate processing apparatus having the above configuration will be described below. The wafer W carried out by the cassette unit 134A or 134B by the transport unit side transport mechanism 170 is transported to the orienter 137 and transferred to the rotary mount 138 of the orienter 137, and is positioned therein. The positioned wafer is carried out by the director 137 and carried into the load lock chambers 160 M and 160 N. At this time, when the processed wafer is present in the load lock chamber 160 M or 160 N, the unprocessed wafer is carried out after the wafer is processed and completed.

The wafer loaded into the lock chamber 160 M or 160 N is carried out by the processing unit side transport mechanism 180 from the load lock chamber 160 M or 160 N, and is carried into the processing chamber 140A or 140B for wafer processing. A specific treatment is administered. After the processing of the processing chamber 140A or 140B is completed, the wafer is processed, and the processing unit side transfer mechanism 180 is carried out from the processing chamber 140A or 140B to return to the load lock chamber 160 M or 160 N. The processed wafer returned to the load lock chamber 160 M or 160 N is returned to the cassette container 134A or 134B by the transport unit side transport mechanism 170.

In order to improve the processing efficiency of the processing chamber 140A or 140B, it is preferable to make the unprocessed wafer as close as possible to the processing chamber in the standby position, and therefore, the processing is performed by the cassette container 134A or 134B during the processing of the processing chamber 140A or 140B. The wafers are not processed, and their wafers are placed in the common transfer chamber 150, the load lock chamber 160 M or 160 N, the director 137, and the like. After the processing of one wafer of the processing chamber 140A or 140B is completed, the processed wafer is immediately returned to the cassette container 134A or 134B, and the unprocessed wafers in the standbys are sequentially transferred to wait for the common transfer chamber 150. An unprocessed wafer is immediately moved into the processing chamber 140A or 140B.

In the substrate processing apparatus 100, when wafer processing is performed in parallel in each of the processing chambers 140A and 140B, when the processing efficiency of each of the processing chambers 140A and 140B is to be improved, the transfer timing of the wafers processed by the processing chambers 140A and 140B is determined. It is important that the processing chamber 140A or 140B is carried out. The substrate transfer method of this embodiment including the process of calculating the transfer timing will be described below.

(Substrate transfer method of substrate processing apparatus)

In the substrate transfer method of the present embodiment, the wafer transfer timing calculated in advance by the processing time of each processing chamber is carried out by the transfer unit side transfer mechanism 170 by the respective cassette containers 134. Since the wafers are carried out by the respective cassette containers 134 in accordance with the wafer transfer timing corresponding to the processing time of each processing chamber, even if a plurality of processing chambers having different processing times are continuously processed in parallel, the processing is not performed. The processing time of the chamber is different and an unnecessary waiting time is generated, which improves the working efficiency of the entire substrate processing apparatus. Here, the processing time of each processing chamber refers to a time required for one wafer processing (for example, including a processing time), and for example, the processing is carried out from one wafer to the wafer in each processing chamber. The time when the next wafer can be moved in.

The wafer transfer timing is determined, for example, by the wafer carry-out ratio and the wafer carry-out interval. Here, the wafer carry-out ratio refers to the ratio of the number of wafers carried out by each of the processing chambers carried out by the cassette container 134, and the wafer unloading interval refers to the wafer unloading interval of each processing chamber carried out by the cassette container 134. For example, suppose that the processing chamber that has the longest processing time equivalent to one wafer is P1, the other processing chambers are Pk (k=2, 3, . . . ), and the processing chamber P1 corresponds to the processing time of one wafer. When Tp1 is set, the processing time corresponding to one wafer of the other processing chambers Pk is Tpk, the wafer processed by the processing chamber P1 is Wp1, and the wafer processed by the other processing chamber Pk is Wpk, and the number of wafers is removed. The ratio of the number of unloaded wafers Wp1 and wafer Wpk carried out by the cassette container 134 for each processing time Tp1, Tpk corresponding to each of the processing chambers P1, Pk. Further, the wafer carry-out interval is a transfer interval between the wafer Wp1 and the wafer Wpk which are carried out by the cassette container 134 at the wafer carry-out ratio.

When the number of processing chambers included in the substrate processing apparatus is three or more, the wafer transfer timing is calculated for each of the other processing chambers Pk in relation to the processing chamber P1 having the longest wafer processing time. DETAILED words, for example, includes three processing chambers P1, P2, P3 of the substrate processing apparatus, by calculating the relationship between the processing chamber P1 and P2 of the wafer processing chambers and wafer W ₁ Wp2 of conveyance timing. Moreover, the transfer timing of the wafer Wp3 is calculated based on the relationship between the processing chamber P1 and the processing chamber P3. As described above, the wafer transfer timing is calculated based on the relationship between the processing chamber P1 having the longest wafer processing time and the other processing chambers Pk, because the optimum processing of the wafers processed by the respective processing chambers can be easily calculated based on the longest processing time Tp1. The transfer timing.

The method of calculating the wafer transfer timing described above will be described below. The wafer transfer timing can be calculated as follows for each processing time Tp1, Tpk of each of the processing chambers P1, Pk. Here, for example, a substrate processing apparatus 100 including two processing chambers as shown in FIG. 1 will be described as an example. Among the processing chambers 140A and 140B of the substrate processing apparatus 100, the processing chamber having the longest processing time is P1, and the other processing chambers are P2.

For example, the ratio of the processing times Tp1 and Tp2 of the processing chambers P1 and P2 (Tp1: Tp2) is 2:1, and the processing chamber P2 can process 2 crystals in the processing time Tp1 of the wafer Wp1 of the processing chamber P1. Round Wp2. Therefore, the wafer carry-out ratio is set to 1:2. In this case, since the processing of the next wafer after the processing of each of the processing chamber P1 and the processing chamber P2 is completed, the wafer unloading intervals of the wafers Wp1 and Wp2 are set to the respective processing times Tp1 and Tp2.

In response to this, the wafers Wp1 and Wp2 processed in the respective processing chambers P1 and P2 are carried out by one sheet at intervals of the respective processing times Tp1 and Tp2. At this time, the processing time Tp1 is twice the processing time Tp2. Therefore, while the wafer Wp1 processed in the processing chamber P1 is carried out one sheet, the wafer Wp2 processed in the processing chamber P2 is carried out by two sheets.

As described above, in the present embodiment, the wafer transfer timing from the cassette container 134 is calculated based on the processing times Tp1 and Tpk of the respective processing chambers P1 and Pk. Therefore, the processing time is longer than the processing chamber P1 according to the transfer timing. The wafer Wp1 may be carried out by the cassette container 134 at a longer interval corresponding to the processing time Tp1, and the wafer Wpk processed by the processing chamber Pk may be processed by the cassette container 134 at a shorter interval corresponding to the processing time Tpk. Was moved out. According to this, it is conventional that the wafer Wp1 of the processing chamber P1 has a long processing time and waits for a long time in the common transfer chamber 150, the load lock chambers 160M, 160N, and the director 137, and the wafer Wpk of the processing chamber Pk cannot be processed for a short time. The case where the cassette container 134 is carried out can be eliminated, the efficiency of the processing chambers P1 and Pk can be improved, and the work efficiency of the entire substrate processing apparatus can be improved.

However, there is only one transport unit side transport mechanism 170. For example, the substrate processing apparatus 100 including two processing chambers as shown in FIG. 1, for example, the start timing of the wafer Wp1 being processed from the processing chamber P1 as shown in FIG. From t11, the offset time Ts2 of the operation cycle portion of the transport unit side transport mechanism 170 occurs between the start timing t12 at which the first wafer Wp2 processed by the other processing chamber P2 is carried out. The operation cycle of the transport unit side transport mechanism 170 is, for example, one of the following series of operations. First, the wafer is carried out from the cassette container 134 by the transport unit side transport mechanism 170 and transported to the director 137. Thereafter, the wafer is accessed by the director 137 to exchange the wafer with the positioning completion. Thereafter, the positioning completed wafer is transferred to the load lock chamber 160 M or 160 N, and the positioning completion wafer and the process completed wafer exchange are performed in the load lock chamber 160 M or 160 N. Finally, the process completed wafer is returned to the cassette container 134. In the specific example of FIG. 5, the time taken for the series of operations, that is, the offset time Ts2 of the start timing is set to, for example, 20 seconds.

Further, the transfer interval in which the wafer Wp1 processed by the processing chamber P1 is carried out by one sheet is equal to the unloading interval in which the two wafers Wp2 processed by the processing chamber P2 are carried out, and therefore, the intervals in which the transfer intervals are often generated are The offset time Tsk of the start timing described above is such that the wafer Wp1 is carried out by the cassette container 134, and the timing at which the wafer Wp2 is carried out by the cassette container 134 is not simultaneously. Therefore, when such a wafer transfer timing is carried out by the cassette container 134 from the wafers Wp1 and Wpk, the waiting time due to the wafer carry-out wait is not generated in each of the processing chambers P1 and P2.

As described above, when the processing time Tp1 of the processing chamber P1 is exactly an integral multiple (for example, n times) of the processing time Tk of the processing chamber Pk, the processing interval of each wafer Wp1 processed by the processing chamber P1 is carried out, and the processing chamber Since the number of sheets of the integral multiple of the Pk-processed wafer Wpk (for example, n pieces) is equal to the unloading interval, the carry-out interval is a part of the offset time Tsk which is often shifted from the start timing. Therefore, each of the processing chambers P1, Pk does not cause a waiting time caused by wafer carry-out waiting. Further, in the wafer transfer timing in this case, it is only necessary to use the processing times Tp1 and Tpk of the processing chambers P1 and Pk for the wafer carry-out intervals of the wafers Wp1 and Wpk processed in the respective processing chambers P1 and Pk. Accordingly, the number of wafer carry-outs for the wafers Wp1 and Wpk can be determined.

However, in actual processing of the wafer, in many cases, the processing time Tp1 of the processing chamber P1 is not exactly an integral multiple of the processing time Tpk of the processing chamber Pk. In this case, even if the wafers Wp1 and Wpk are carried out to generate the offset timing of the above-described startup timing, the timing at which the wafer Wp1 is carried out by the cassette container 134 occurs because the respective wafers Wp1 and Wpk have different ejection intervals. The timing at which the wafer Wpk is carried out by the cassette container 134 is simultaneous. In this case, wafer unloading waits for any of the wafers Wp1 and Wp2, and as a result, a waiting time is generated in any of the processing chambers P1 and P2, which reduces the work efficiency of the entire substrate processing apparatus.

Therefore, in the present invention, the transport timing is calculated such that one or each of the wafers Wp1 and Wpk is carried out by the cassette container 134 at the same reference carry-out interval Tx, whereby the wafers Wp1 and Wp2 are jammed containers. 134 does not generate wafer carry-out waiting when moving out.

Specifically, first, the reference carry-out interval Tx of the reference when the wafers Wp1 and Wpk are carried out by the cassette container 134 is determined in accordance with the processing times Tp1 and Tpk of the processing chambers P1 and Pk. Thereafter, the maximum number m and n of wafers Wp1 and Wpk that can be processed in the interval of the reference carry-out interval Tx are calculated.

In this case, for example, as the wafer transfer timing, the wafer carry-out ratio of the wafers Wp1 and Wpk is m:n, and the wafer carry-out interval is set to each processing time Tp1, Tpk. According to this, for the wafer Wp1 processed by the processing chamber P1, each of the m pieces is carried out by the cassette container 134 at each processing time Tp1 in the reference carry-out interval Tx, and the wafer processed for the processing chamber Pk Wpk, in the same reference carry-out interval Tx as described above, causes each of the n pieces to be carried out by the cassette container 134 for each processing time Tpk. In this case, the wafers Wp1 and Wpk may be continuously carried out as long as the m-sheet and n-sheet carry-out timings in the respective sections of the reference carry-out interval Tx are each of the processing times Tp1 and Tpk, or may be discontinuously carried out.

As described above, when the wafers Wp1 and Wpk are processed in parallel in the respective processing chambers P1 and Pk, the wafer transfer timing of the cassette container 134 can be matched with the processing times Tp1 and Tpk of the processing chambers P1 and Pk. Further, according to the wafer transfer timing, for example, during the processing time of the wafer Wp1 in the processing chamber P1, the processing of the wafer Wpk which is the largest possible number of processing in the other processing chambers Pk can be performed, and the processing chambers P1 can be reduced. The processing waiting time of Pk can improve the efficiency of the processing in each processing chamber, and accordingly, the working efficiency of the entire substrate processing apparatus can be improved.

Further, each of the one or each of the plurality of wafers Wp1 and Wpk is carried out at the timing (period) of the same reference carry-out interval Tx by the cassette container 134. Thus, the wafers Wp1 and Wpk are carried out by the cassette container 134. The timing is often shifted from the offset time Tsk of the above-described start timing, and therefore, the timings at which the wafers Wp1 and Wpk are carried out by the cassette container 134 are not simultaneously. Accordingly, the processing chambers P1 and P2 do not have a waiting time due to wafer carry-out waiting.

In this case, the remaining time obtained by subtracting the processing times of the number of wafers Wp1 and Wpk m and n from the reference carry-out interval Tx is the waiting time of each of the processing chambers Pk and P1 of each of the reference carry-out intervals Tx. Therefore, it is preferable to determine the reference carry-out interval Tx so that the waiting time is as small as possible. For example, Tp1 which is m times the processing time Tp1 of the processing chamber P1. When m is used as the reference carry-out interval Tx, the waiting time of the processing chamber P1 can be eliminated, and the processing time Tpk×n or the (p+1) times of the processing time Tpk can be eliminated. (n+1) As the reference carry-out interval Tx, the waiting time of the processing chamber Pk can be eliminated.

As described above, the reference carry-out interval Tx is determined in accordance with the combination of the processing times Tp1 and Tp2 of the processing chambers P1 and P2 so that the waiting time of any one of the processing chambers P1 and P2 is the shortest, and the card loading container is calculated based on the reference carrying interval Tx. 134 wafer transfer timing (for example, wafer carry-out ratio and wafer carry-out interval). According to this, the waiting time of each of the processing chambers P1 and P2 can be optimized, and the work efficiency of the entire substrate processing apparatus can be improved. Moreover, the method of calculating such a wafer transfer timing can be applied regardless of whether or not the processing time Tp1 of the processing chamber P1 is exactly an integral multiple of the processing time Tpk of the processing chamber Pk.

Further, when there are three or more processing chambers in the substrate processing apparatus, the wafer transfer timing is calculated for each of the other processing chambers Pk in accordance with the relationship between the processing chambers P1 having the longest wafer processing time. However, in this case, in order to determine the unification of the reference carry-out interval Tx, for example, when the wafer transfer timing of the other processing chamber P2 is first calculated, the reference carry-out interval Tx is determined, and the other processing chambers P3, P4, and . . . Pkend uses the above-mentioned reference carry-out interval Tx that has been determined when calculating the wafer transfer timing. Further, the waiting time is calculated for each of the other processing chambers Pk in accordance with the relationship with the processing chamber P1, and the waiting time may be minimized to calculate the reference carrying interval Tx.

(Specific example of processing the wafer transfer timing)

A specific example of calculation of the wafer transfer timing by the wafer transfer timing calculation method will be described below with reference to the drawings. Fig. 2 is a flow chart showing the processing of calculating the wafer transfer timing in the embodiment. Further, the processing for calculating the wafer transfer timing is constituted by, for example, a specific program, and is executed by the control unit 190 in accordance with the program. For example, the program is stored in advance in a memory medium such as a memory of the control unit 190 or a hard disk device of an externally connected main computer device, and the control unit 190 reads and executes the programs from the recording medium.

As shown in FIG. 2, the wafer transfer timing is calculated. First, the wafer processing time of each processing chamber is compared in step S110. The processing chamber corresponding to the longest processing time of one wafer is set to P1, and the other processing chambers are set to Pk (k = 2, 3, ..., kend). The kend is the number of processing chambers provided in the substrate processing apparatus 100. For example, the substrate processing apparatus 100 of FIG. 1 has two processing chambers 140A and 140B, and the processing chamber corresponding to the longest processing time of one wafer is the processing chamber 140A, and the processing chamber 140A is the processing chamber P1, and the processing chamber 140B is set. Processing chamber P2.

Thereafter, in step S120, the processing time corresponding to one wafer of the processing chamber P1 is set to Tp1, and the processing time corresponding to one wafer of the other processing chamber Pk is set to Tpk. Further, the number of the processing chamber P1 and the other processing chambers Pk (k = 2, 3, ..., kend) is preferably in the order of the processing chamber having a longer processing time. For example, the substrate processing apparatus having three processing chambers is set as the processing chamber P1, the processing chamber P2, and the processing chamber P3 in the order of the processing time corresponding to one wafer.

Thereafter, the processing of calculating the wafer transfer timing is performed in steps S130 and S140. That is, the process of calculating the wafer carry-out ratio is performed in step S130, and the process of calculating the wafer carry-out interval is performed in step S140. A specific example of the process of calculating the wafer carry-out ratio in step S130 is shown in FIG. 3, and a specific example of the process of calculating the wafer carry-out interval in step S140 is shown in FIG. 3 and 4, the maximum number m of wafers Wp1 that can be processed at the reference carry-out interval Tx is set to 1, that is, the processing time Tp1 of the processing chamber P1 having the longest processing time corresponding to one wafer. The process at the time of the reference carry-out interval Tx is determined for the reference. FIG. 5 is a view showing the processing time of the wafers Wp1 and Wp2 processed by the processing chambers P1 and P2 when the wafer transfer timing calculated by FIG. 2-4 is carried out by the cassette container 134. In FIG. 5, the horizontal axis represents time, and the processing time periods of the wafers Wp1 and Wp2 processed by the two processing chambers P1 and P2 are respectively shown in a bar graph.

(Specific example of processing the ratio of wafer carry-out ratio)

First, a specific example of the process of calculating the wafer carry-out ratio will be described with reference to FIG. As shown in FIG. 3, in step S210, when the processing time Tp1 of the processing chamber P1 having the longest processing time corresponding to one wafer is used as the reference carrying interval Tx, it is within the interval of the reference carrying interval Tx (herein In the processing time Tp1, the maximum number n of wafers Wpk that can be processed by the other processing chamber Pk is calculated. In the longest processing time Tp1, the number of wafers Wpk that can be processed by the other processing chamber Pk is carried out by the cassette container 134, and accordingly, the waiting time of the processing chamber Pk can be minimized.

Specifically, for example, the following formulas (1-1) and (1-2) are simultaneously established to calculate the number n of wafers Wpk. Further, in the following formulae (1-1) and (1-2), Tp1 is the processing time corresponding to one wafer Wp1 of the processing chamber P1, and Tpk is equivalent to one wafer Wpk of the other processing chamber Pk. For the processing time, n is an integer satisfying n≧1, k is an integer satisfying k≧2, and "." in the following formulas (1-1) and (1-2) indicates a sign of multiplication (the same applies hereinafter) ).

Tp1≧Tpk. n (1-1) Tp1<Tpk. (n+1) (1-2)

In the following steps S220-S280, the processing time Tp1 of the processing chamber P1 and the processing time Tpk of the processing chamber Pk are determined. The shorter waiting time among (n+1) is used as the reference carry-out interval Tx, and the wafer carry-out ratio of the wafers Wp1 and Wpk processed in each of the processing chambers P1 and Pk is calculated. As described above, by using the shorter waiting time of the processing chambers P1 and Pk as the reference carry-out interval Tx, the processing waiting time can be shortened for all of the processing chambers P1 and Pk. According to this, it is possible to optimize the waiting time of the entire substrate processing apparatus.

Specifically, in step S220, the processing time Tp1 of the processing chamber P1 is set as the reference carrying interval Tx, and the waiting time Twk of the other processing chamber Pk is calculated according to the following formula (1-3). In step S230, the processing chamber is used. Pk processing time Tpk. (n+1) is the reference carry-out interval Tx, and the waiting time Tw1 of the processing chamber P1 is calculated based on the following formula (1-4).

Twk=Tp1-Tpk. n (1-3) Tw1=Tpk. (n+1)-Tp1 (1-4)

In step S240, the waiting times Tw1 and Twk are compared, and which waiting time is short. Specifically, for example, it is determined whether or not the waiting time Twk is equal to or shorter than the waiting time Tw1 (Twk ≦ Tw1). When it is determined in step S240 that Twk ≦ Tw1, that is, when the waiting time Twk is short (or the waiting times Tw1 and Twk are equal), the reference of each of the wafers Wp1 and Wpk is performed in step S250 as shown in the following formula (1-5). The carry-out interval Tx is determined as the processing time Tp1 of the processing chamber P1, and in step S260, the wafer carry-out ratio (Wp1: Wpk) of each of the wafers Wp1 and Wpk is set to 1:n.

Tx=Tp1=Tpk. n+Twk (1-5)

The reference carry-out interval Tx (=Tp1=Tpk.n+Twk) obtained in this way, in each of the sections, the wafer Wp1 processed by the processing chamber P1 is carried out one piece, and the waiting time of the processing chamber P1 is 0, and the processing chamber Pk The processed wafer Wpk is carried out by n pieces, and the waiting time of the processing chamber Pk is Twk.

On the other hand, when the non-Twk ≦ Tw1 is determined in S240, that is, when the waiting time Tw1 is short, the reference carry-out interval Tx of each of the wafers Wp1 and Wpk is determined as the following equation (1-6) in step S270. Processing room Pk Tpk. (n+1), in step S280, the wafer carry-out ratio (Wp1: Wpk) of each of the wafers Wp1 and Wpk is set to 1:n+1.

Tx=Tp1+Tw1=Tpk. (n+1) (1-6)

The reference carry-out interval Tx (=Tp1+Tw1=Tpk.(n+1)) obtained in this way, in each of the sections, the wafer Wp1 processed by the processing chamber P1 is carried out one piece, and the waiting time of the processing chamber P1 is Tw1, and processing is performed. The wafer Wk processed by the chamber Pk is carried out out of n+1 sheets, and the waiting time of the processing chamber Pk is zero. Moreover, the reference carry-out interval Tx and the number of wafer carry-outs obtained by the process of FIG. 3 are stored in the memory of the control unit 190, and the like.

(Specific example of processing the wafer carry-out interval)

Hereinafter, a specific example of the process of calculating the wafer carry-out interval will be described with reference to FIG. 4, and the ratio of the number of wafer carry-outs generated by the reference carry-out interval Tx determined by the process of calculating the wafer carry-out ratio is calculated as shown in FIG. The wafer carry-out interval of each of the wafers Wp1 and Wpk when the wafer is carried out by the cassette container 134.

Specifically, as shown in FIG. 4, in step S310, the wafer carry-out ratio (Wp1: Wpk) calculated by the process of FIG. 3 is taken out from the memory of the control unit 190, and the number of wafer carry-out ratios is determined ( Wp1:Wpk) is 1:n or 1:n+1.

When it is determined in step S310 that the wafer carry-out ratio (Wp1:Wpk) is 1:n, the wafer carry-out interval of the wafer Wp1 processed in the processing chamber P1 in step S320 is assumed to be carried out at the reference carry-out interval Tx. interval. In response to this, the wafer Wp1 is carried out by one sheet at the reference carry-out interval Tx, that is, by one of the cassette containers 134 at each processing time Tp1. In this case, since the reference carry-out interval Tx is the processing time Tp1 of the processing chamber P1, for example, as shown in the processing time of the upper side of FIG. 5(a), the waiting time of the processing chamber P1 is 0, and the wafer Wp1 is continuously processed.

Thereafter, in step S330, the wafer unloading interval of the wafer Wpk processed in the processing chamber Pk is set to an interval at which each n pieces of the reference carry-out interval Tx are carried out for each processing time Tpk. In this case, for example, the wafer Wpk is continuously carried out by the cassette container 134 in each of the sections of the reference carry-out interval Tx, and only the waiting time Twk is carried out. That is, after the n pieces are continuously carried out by the cassette container 134, only one waiting time Twk is waited for, and the next n pieces are continuously carried out again by the cassette container 134. In this case, the reference carry-out interval Tx becomes the processing time Tpk of the processing chamber Pk. n+Twk, for example, as shown in the processing time of the lower side of FIG. 5(a), the processing chamber Pk performs continuous processing for each n wafer Wpk in a state where the waiting time Twk exists in each section of the reference carrying interval Tx. Further, Fig. 5(a) shows a specific example of k = 2 and n = 3.

On the other hand, when it is determined in step S310 that the wafer carry-out ratio (Wp1:Wpk) is 1:n+1, the wafer carry-out interval of the wafer Wp1 processed in the processing chamber P1 in step S340 is carried out at the reference carry-out interval Tx. 1 piece interval. In this case, for example, each of the wafers Wp1 is carried out by the cassette container 134 in each of the intervals of the reference carry-out interval Tx, and the waiting time Tw1 is waited for. That is, after one sheet is taken out from the cassette container 134, the waiting time Tw1 is waited for, and the next sheet is again carried out by the cassette container 134. In this case, since the reference carry-out interval Tx is the processing time Tp1+Ww1 of the processing chamber P1, for example, as shown in the processing time of the upper side of FIG. 5(b), there is a waiting time Tw1 in each section of the processing chamber P1 in the reference carrying-out interval Tx. Each wafer Wp1 is processed in the state.

Thereafter, in step S350, the wafer unloading interval of the wafer Wpk processed in the processing chamber Pk is set to be an interval at which n+1 sheets are moved one by one for each processing time Tpk at the reference carry-out interval Tx. In this case, the wafer Wpk is continuously carried out by the cassette container 134 in each of the intervals of the reference carry-out interval Tx. For example, the reference carry-out interval Tx becomes the processing time Tpk of the processing chamber Pk. (n+1), for example, as shown in the processing time of the lower side of FIG. 5(b), the processing chamber Pk continuously processes each n+1 wafer Wpk in the state of the waiting time 0 in each section of the reference carry-out interval Tx. Further, Fig. 5(b) shows a specific example of k = 2 and n = 2.

The wafer carry-out ratio calculated by the processing shown in FIGS. 3 and 4 and the wafer carry-out interval are stored in the memory of the control unit 190. Actually close. When the wafer processing is actually performed, the control unit 190 obtains the wafer carry-out ratio and the wafer carry-out interval obtained from the memory in FIGS. 3 and 4, and controls the transport unit side transfer according to the wafer carry-out ratio and the wafer carry-out interval. The mechanism 170 causes the wafers Wp1 and Wpk to be carried out by the cassette container 134, respectively.

According to this, for example, the wafer Wp1 processed by the processing chamber P1 is processed by the cassette container 134 at a longer interval according to the processing time Tp1, and the wafer Wpk processed by the processing chamber Pk is processed accordingly. The time Tpk is carried out by the cassette container 134 at a short interval. In this case, the wafer Wp1 processed by the processing chamber P1 for a long time is reserved for the long time in the common transfer chamber 150, the load lock chambers 160 M, 160 N, the director 137, etc., and the processing time is shorter. The case where the wafer Wpk cannot be carried out by the cassette container 134 can be eliminated. Therefore, the efficiency of the processing of each of the processing chambers P1 and Pk can be improved, and the work efficiency of the entire substrate processing apparatus can be improved.

Further, since the wafers Wp1 and Wpk are carried out by the cassette 134 at the timing (period) of the same reference carry-out interval Tx, the respective intervals of the reference carry-out interval Tx of the wafers Wp1 and Wpk are shifted only from the wafer to be processed first. The offset time Tsk of the start timing generated when Wp1 and Wpk are carried out. Therefore, the timings at which the wafers Wp1 and Wpk are carried out are not simultaneous, and the processing of FIGS. 3 and 4 is not only applicable to the case where the processing time Tp1 of the processing chamber P1 is not an integral multiple of the processing time Tpk of the processing chamber Pk, as shown in FIG. 5. The processing time of (c) is also applied to the case where the processing time Tp1 of the processing chamber P1 is exactly an integral multiple of the processing time Tpk of the processing chamber Pk.

(Application of a substrate processing apparatus having two processing chambers)

Hereinafter, the processing for calculating the wafer transfer timing shown in FIGS. 2-4 will be described with respect to the substrate processing apparatus having two processing chambers as shown in FIG. 1, and will be described with reference to FIG. Fig. 5(a) shows a case where the processing time corresponding to one wafer of each of the processing chambers 140A and 140B is 200 seconds and 60 seconds, and Fig. 5(b) shows the case of 200 seconds and 70 seconds, and Fig. 5(c) ) indicates 200 seconds, 50 seconds. In any case, the processing chamber having the longest processing time is the processing chamber 140A. Therefore, according to steps S110 and S120 of FIG. 2, the processing chamber 140A is the processing chamber P1, the processing time is Tp1, and the other processing chambers 140B are the processing chamber P2. Its processing time is Tp2.

When the transfer timing is calculated in accordance with step S130 (for example, the processing shown in FIG. 3) and step S140 (for example, the processing shown in FIG. 4) of FIG. 2, the processing time is determined by each processing chamber, and therefore, FIG. 5(a) and FIG. ), (c) Description.

First, a specific example of Fig. 5(a) will be described. In this specific example, the processing room waiting time is shortened by setting the reference carry-out interval Tx to the processing time Tp1. 5(a), the processing time Tp1 of the processing chamber P1 is 200 seconds, and the processing time Tp2 of the processing chamber P2 is 60 seconds. Therefore, according to step S210 of FIG. 3, k=2 is substituted into the equation (1-1) and (1-2), satisfying those of the formula is n=3.

Then, according to steps S220 and S230, k=2 is substituted into the equations (1-3) and (1-4), respectively, and the waiting time Tw2 of the processing chamber P2 is 200-60×3=20 seconds. The waiting time of the chamber P1 is Tw1 = 60 × 4 - 200 = 40 seconds. The waiting time Tw2 (=20 seconds) of the processing chamber P2 is smaller than the waiting time Tw1 (=40 seconds) of the processing chamber P1. Therefore, in step S240, step S240, step S260, the reference carrying interval Tx of the wafers Wp1 and Wp2 becomes the processing chamber. The processing time Tp1 (=200 seconds) of P1, the wafer Wp1 processed by the processing chamber P1, and the wafer carry-out ratio (Wp1:Wp2) of the wafer Wp2 processed by the processing chamber P2 are 1:3.

Thereafter, in accordance with steps S310, S320, and S330, the wafer carry-out interval of the wafer Wp1 processed by the processing chamber P1 is set to be an interval at which one sheet is carried out in the reference carry-out interval Tx (=200 seconds). The wafer carry-out interval of the wafer Wp2 processed in the processing chamber P2 is set to be three sheets at the reference carry-out interval Tx (=200 seconds) and one sheet for each processing time Tp2 to be carried out.

When the respective wafers Wp1 and Wp2 are carried out from the cassette container 134 by the above-described wafer transfer timing, the processing time of each of the processing chambers P1 and P2 is as shown in FIG. 5(a). In this case, the waiting time in the processing chamber P1 is 0, the wafer Wp1 is continuously processed, and in the processing chamber P2, there is a waiting time Tw2 (= 20 seconds) for each reference carrying interval Tx (= 200 seconds). Three wafers of wafer Wp2 are processed continuously.

Next, a specific example of FIG. 5(b) will be described. In this specific example, the reference carry-out interval Tx is set as the processing time Tp2 of the processing chamber P2. (n+1) The processing room waiting time is shortened. In FIG. 5(b), the processing time Tp1 of the processing chamber P1 is 200 seconds, and the processing time Tp2 of the processing chamber P2 is 70 seconds. Therefore, according to step S210 of FIG. 3, k=2 is substituted into the equation (1-1). And (1-2), satisfying those of the formula is n=2.

Then, according to step S220 and step S230, it is assumed that k=2 is substituted into equations (1-3) and (1-4), respectively, and the waiting time Tw2 of the processing chamber P2 is 200-70×2=60 seconds, and the processing is performed. The waiting time of the chamber P1 is Tw1 = 70 × 3 - 200 = 10 seconds. The waiting time Tw1 (=10 seconds) of the processing chamber P1 is smaller than the waiting time Tw2 (=60 seconds) of the processing chamber P2. Therefore, in step S240, step S270, and step S280, the reference carrying interval Tx of the wafers Wp1 and Wp2 becomes the processing chamber. The processing time of P2 is 70 seconds × 3 (= 210 seconds), and the wafer carry-out ratio (Wp1: Wp2) of wafer Wp1 and wafer Wp2 is 1:3.

Thereafter, in accordance with steps S310, S340, and S350 of FIG. 4, the wafer carry-out interval of the wafer Wp1 processed by the processing chamber P1 is set to be an interval at which each sheet is carried out in the reference carry-out interval Tx (=200 seconds). The wafer carry-out interval of the wafer Wp2 processed in the processing chamber P2 is an interval at which each of the three sheets is carried out in the standard carry-out interval Tx (=200 seconds) at each processing time Tp2 (=70 seconds).

When the respective wafers Wp1 and Wp2 are carried out from the cassette container 134 by the wafer transfer timing described above, the processing time of each of the processing chambers P1 and P2 is as shown in FIG. 5(b). In this case, the wafer Wp1 is continuously processed in the processing chamber P1 by the waiting time Tw1 in each of the reference carry-out intervals Tx. Further, in the processing chamber P2, the three wafers Wp2 are continuously processed by the waiting time 0 in each of the reference carry-out intervals Tx (= 200 seconds).

Next, a specific example of FIG. 5(c) will be described. In this specific example, the processing time Tp1 of the processing chamber P1 is equal to the processing time Tp2 of the processing chamber P2. n. In this case, the processing time of the processing chamber P2 is Tp2. N (or the processing time Tp1 of the processing chamber P1) is set as the reference carry-out interval Tx, and accordingly, the waiting time of each processing chamber becomes zero. In FIG. 5(c), the processing time Tp1 of the processing chamber P1 is 200 seconds, and the processing time Tp2 of the processing chamber P2 is 0 seconds. According to the step S210 of FIG. 3, it is assumed that k=2 is substituted into the equation (1-1) and 1-2), satisfying those of the formula is n=4.

Then, according to step S220 and step S230, it is assumed that k=2 is substituted into equations (1-3) and (1-4), respectively, and the waiting time Tw2 of the processing chamber P2 is 200-50×4=0 seconds. The waiting time of the chamber P1 is Tw1 = 50 × 5 - 200 = 50 seconds. The waiting time Tw1 (=0 seconds) of the processing chamber P1 is smaller than the waiting time Tw2 (= 50 seconds) of the processing chamber P2. Therefore, in step S240, step S270, step S280, the reference carrying interval Tx of the wafers Wp1 and Wp2 becomes the processing chamber. P2 processing time Tp2. n (=200 seconds), the wafer carry-out ratio (Wp1: Wp2) of the wafer Wp1 and the wafer Wp2 is 1:4.

Thereafter, in accordance with steps S310, S340, and S350 of FIG. 4, the wafer carry-out interval of the wafer Wp1 processed by the processing chamber P1 is set to be an interval at which one sheet is carried out in the reference carry-out interval Tx (=200 seconds). The wafer carry-out interval of the wafer Wp2 processed in the processing chamber P2 is an interval in which one sheet is carried out in the reference carry-out interval Tx (=200 seconds) and one sheet is carried out in each processing time Tp2 (=50 seconds).

When the respective wafers Wp1 and Wp2 are carried out from the cassette container 134 by the above-described wafer transfer timing, the processing time of each of the processing chambers P1 and P2 is as shown in FIG. 5(c). In this case, the wafer Wp1 is continuously processed in the processing chamber P1 by the waiting time 0 in each of the reference carry-out intervals Tx. Further, in the processing chamber P2, four wafers Wp2 are continuously processed by the waiting time 0 in each of the reference carry-out intervals Tx (= 200 seconds).

(Application of a substrate processing apparatus having three or more processing chambers)

Hereinafter, the processing for calculating the wafer transfer timing shown in FIGS. 2-4 will be described with respect to the substrate processing apparatus including three or more processing chambers. Fig. 6 is a schematic configuration of a substrate processing apparatus having three or four processing chambers. The substrate processing apparatus 200 of FIG. 6 has a configuration substantially the same as that of the substrate processing apparatus 100 of FIG. 1, and the chambers 140C and 140D are connected to both sides of the common transfer chamber 150 via the gate valves 144C and 144D. Here, for example, the chamber 140C is configured as a processing chamber for performing wafer processing, and the chamber 140D is configured as a detection chamber for performing various types of detection such as measurement of the processing result of the processed wafer, and is provided with three processing chambers. In the substrate processing apparatus 200, when the chambers 140C and 140D are simultaneously used as processing chambers for wafer processing, the substrate processing apparatus 200 is provided with four processing chambers. Further, in the substrate processing apparatus 200 of Fig. 6, a cassette table 132C is provided on one side surface of the long side of the polygonal shape of the cross section of the transfer chamber 130, and another cassette container 134C can be placed. For example, the wafer processed by the chamber 140C or 140D which is a processing chamber may be accommodated in the cassette container 134C.

First, the substrate processing apparatus 200 shown in FIG. 6 has a configuration of a substrate processing apparatus having three processing chambers, and the processing for calculating the wafer transfer timing shown in FIGS. 2-4 is performed, and a specific numerical value will be described with reference to FIG. Fig. 7 shows the wafer processing time courses of the respective processing chambers in which the transfer timing calculated in accordance with Fig. 2-4 is processed. The horizontal axis of Fig. 7 is time, and the processing time periods of the wafers processed by the three processing chambers P1, P2, and P3 are respectively represented by bar graphs. 7 shows that the processing time of each of the processing chambers 140A, 140B, and 140C corresponding to one wafer is 200 seconds, 70 seconds, and 50 seconds. In this case, the processing chamber having the longest processing time is the processing chamber 140A. In steps S110 and S120 of FIG. 2, the processing chamber 140A is the processing chamber P1, the processing time is Tp1, the processing chamber 140B is the processing chamber P2, the processing time is Tp2, and the processing chamber 140C is the processing chamber P3, and the processing time is Tp3. Therefore, in this case, the transfer timing of the wafer Wp1 and the wafer Wp2 is calculated based on the relationship between the processing chamber P1 and the processing chamber P2, and the transfer timing of the wafer Wp3 is calculated based on the relationship between the processing chamber P1 and the processing chamber P3. When the transfer timing of the wafer Wp3 is calculated, the reference carry-out interval Tx determined when the transfer timing of the wafer Wp1 and the wafer Wp2 is calculated is used to unify the reference carry-out interval Tx. A method of calculating such a wafer transfer timing will be described below.

First, the transfer timing of the wafer Wp1 and the wafer Wp2 is calculated based on the relationship between the processing chamber P1 and the processing chamber P2. In this case, similarly to the specific example of FIG. 5(b), the reference transport intervals of the wafers Wp1 and Wp2 are performed. Tx is the processing time of the processing chamber P2 of 70 seconds × 3 (= 210 seconds), and the wafer carry-out ratio (Wp1: Wp2) of the wafers Wp1 and Wp2 is 1:3. The wafer carry-out interval of the wafer Wp1 is shifted by one at the reference carry-out interval Tx (=210 seconds), and the wafer carry-out interval of the wafer Wp2 is three sheets at the reference carry-out interval Tx (=210 seconds). A processing time Tp2 (=0 seconds) is carried out at intervals of one piece.

Next, the transfer timing of the wafer Wp3 processed in the processing chamber P3 is calculated based on the relationship between the processing chamber P1 and the processing chamber P3. In this case, since the reference carry-out interval Tx has been determined to be 210 seconds, the transfer timing of the wafer Wp3 is calculated using this. Specifically, for example, the reference carry-out interval Tx is fixed to 210 seconds, and the processes of steps S210, S220, and S260 of FIG. 3 are performed, and the processes of steps S310 and S330 of FIG. 4 are performed.

That is, in step S210, k=3 is substituted into equations (1-1) and (1-2), and those satisfying the formula are n=4. Then, according to step S220, it is assumed that k=3 respectively substitutes the numerical value into the formula (1-3), and the waiting time Tw3 of the processing chamber P3 is 210-50×4=10 seconds, and the processing chamber P1 processes the crystal according to step S260. The wafer Wp3 processed by the circle Wp1 and the processing chamber P3 has a wafer carry-out ratio (Wp1 = Wp3) of 1:4. Thereafter, in accordance with steps S310 and S330 of FIG. 4, the wafer carry-out interval of the wafer Wp3 processed by the processing chamber P3 is set to 4 pieces in the reference carry-out interval Tx (=210 seconds) at each processing time Tp3 (= 50 seconds) The interval at which each piece is moved out.

When the respective wafers Wp1, Wp2, and Wp3 are carried out from the cassette container 134 by the above-described wafer transfer timing, the processing time of each of the processing chambers P1, P2, and P3 is as shown in FIG. In this case, in each of the reference carry-out intervals Tx (=210 seconds), the waiting time Tw1 in the processing chamber P1 is 10 seconds, the wafer Wp1 is continuously processed, and the waiting time in the processing chamber P2 is 0, and each of the three wafers Wp2 The processing is continued, and the waiting time Tw3 in the processing chamber P3 is 10 seconds, and each of the four wafers Wp3 is continuously processed.

Next, the substrate processing apparatus 200 shown in Fig. 6 is provided with a configuration of a substrate processing apparatus having four processing chambers, and the processing for calculating the wafer transfer timing shown in Figs. 2-4 is performed, and a specific numerical value will be described with reference to Fig. 8 . Fig. 8 shows the wafer processing time courses of the respective processing chambers in which the transfer timing calculated in accordance with Fig. 2-4 is processed. The horizontal axis of Fig. 8 is time, and the processing time courses of the wafers processed by the four processing chambers P1, P2, P3, and P4 are respectively represented by bar graphs. 8 shows the processing time of each of the processing chambers 140A, 140B, 140C, and 140D corresponding to one wafer, which is 200 seconds, 70 seconds, 60 seconds, and 50 seconds. In this case, the processing chamber having the longest processing time is processed. The chamber 140A, therefore, according to steps S110 and S120 of FIG. 2, the processing chamber 140A is the processing chamber P1, the processing time is Tp1, the processing chamber 140B is the processing chamber P2, the processing time is Tp2, and the processing chamber 140C is the processing chamber P3. The processing time is Tp3, and the processing chamber 140D is the processing chamber P4, and the processing time is Tp4. Therefore, in this case, the transfer timing of the wafer Wp1 and the wafer Wp2 is calculated based on the relationship between the processing chamber P1 and the processing chamber P2, and the transfer timing of the wafer Wp3 is calculated based on the relationship between the processing chamber P1 and the processing chamber P3, and the wafer Wp4 The transfer timing is calculated based on the relationship between the processing chamber P1 and the processing chamber P4. When the transfer timing of the wafers Wp3 and Wp4 is calculated, the reference carry-out interval Tx determined when the transfer timing of the wafer Wp1 and the wafer Wp2 is calculated is used to unify the reference carry-out interval Tx. A method of calculating such a wafer transfer timing will be described below.

First, the transfer timing of the wafer Wp1 and the wafer Wp2 is calculated based on the relationship between the processing chamber P1 and the processing chamber P2. In this case, similarly to the specific example of FIG. 5(b), the reference transport intervals of the wafers Wp1 and Wp2 are performed. Tx is the processing time of the processing chamber P2 of 70 seconds × 3 (= 210 seconds), and the wafer carry-out ratio (Wp1: Wp2) of the wafers Wp1 and Wp2 is 1:3. The wafer carry-out interval of the wafer Wp1 is shifted by one at the reference carry-out interval Tx (=210 seconds), and the wafer carry-out interval of the wafer Wp2 is three sheets at the reference carry-out interval Tx (=210 seconds). A processing time Tp2 (=0 seconds) is carried out at intervals of one piece.

Next, the transfer timing of the wafer Wp3 processed in the processing chamber P3 is calculated based on the relationship between the processing chamber P1 and the processing chamber P3. In this case, since the reference carry-out interval Tx has been determined to be 210 seconds, the transfer timing of the wafer Wp3 is calculated using this. Specifically, for example, the reference carry-out interval Tx is fixed to 210 seconds, and the processes of steps S210, S220, and S260 of FIG. 3 are performed, and the processes of steps S310 and S330 of FIG. 4 are performed.

That is, in step S210, k=3 is substituted into equations (1-1) and (1-2), and those satisfying the formula are n=3. Then, in step S220, it is assumed that k=3 respectively substitutes the numerical value into the formula (1-3), and the waiting time Tw3 of the processing chamber P3 is 210-60×3=30 seconds, and the processing chamber P1 processes the crystal according to step S260. The wafer carry-out ratio (Wp1: Wp3) of the wafer Wp3 processed by the circle Wp1 and the processing chamber P3 is 1:3. Thereafter, in accordance with steps S310 and S330 of FIG. 4, the wafer carry-out interval of the wafer Wp3 processed by the processing chamber P3 is set to 3 pieces in the reference carry-out interval Tx (=210 seconds) at each processing time Tp3 (= 50 seconds) The interval at which each piece is moved out.

Next, the transfer timing of the wafer Wp4 processed in the processing chamber P4 is calculated based on the relationship between the processing chamber P1 and the processing chamber P4. In this case, since the reference unloading interval Tx is determined to be 210 seconds, the transfer timing of the wafer Wp4 is calculated using this. Specifically, for example, the reference carry-out interval Tx is fixed to 210 seconds, and the processes of steps S210, S220, and S260 of FIG. 3 are performed, and the processes of steps S310 and S330 of FIG. 4 are performed.

That is, in step S210, k=4 is substituted into equations (1-1) and (1-2), and those satisfying the formula are n=4. Then, in step S220, if k=4 is substituted into the formula (1-3), the waiting time of the processing chamber P4 is Tw4=210-50×4=10 seconds, and the processing chamber P1 processes the crystal according to step S260. The wafer carry-out ratio (Wp1: Wp4) of the wafer Wp4 processed by the circle Wp1 and the processing chamber P3 is 1:4. Thereafter, in accordance with steps S310 and S330 of FIG. 4, the wafer carry-out interval of the wafer Wp4 processed in the processing chamber P4 is set to 4 pieces in the reference carry-out interval Tx (=210 seconds) at each processing time Tp3 (= 50 seconds) The interval at which each piece is moved out.

When the respective wafers Wp1, Wp2, Wp3, and Wp4 are carried out by the cassette container 134 by the above-described wafer transfer timing, the processing time of each of the processing chambers P1, P2, P3, and P4 is as shown in FIG. In this case, in each of the reference carry-out intervals Tx (=210 seconds), the waiting time Tw1 in the processing chamber P1 is 10 seconds, the wafer Wp1 is continuously processed, and the waiting time in the processing chamber P2 is 0, and each of the three wafers Wp2 is continuously processed, and the processing chamber P3 waits for a time Tw3 of 30 seconds, and each of the three wafers Wp3 is continuously processed. The processing chamber P4 waits for a time Tw4 of 10 seconds, and each of the four wafers Wp4 is continuously processed.

(Other specific examples of the processing of calculating the wafer transfer timing)

Other specific examples of the process of calculating the wafer transfer timing by the principle of the present invention will be described below. The main flow of the other specific examples is the same as that shown in FIG. 2, and detailed description thereof will be omitted. FIG. 9 is another specific example of the calculation process of the wafer carry-out ratio in step S130 of FIG. 2. FIG. 10 is another specific example of the process of calculating the wafer carry-out interval in step S140 of FIG. The processing of Figures 9 and 10 is the processing time Tp1 of the processing chamber P1 which has the longest processing time corresponding to one wafer. On the basis of m, the wafer carry-out ratio and the wafer carry-out interval are calculated, that is, the number of wafers Wp1 that can be processed at the reference carry-out interval Tx is m. Also, m can be 1. The wafer transfer timing at the time of m=1 is the same as the result calculated by the processing of Figs. 3 and 4.

(Other specific examples of processing for calculating the number of wafer carry-outs)

First, another specific example of the process of calculating the above-described wafer carry-out ratio will be described with reference to FIG. 9. As shown in FIG. 9, in step S410, it is assumed that the processing time Tp1 of the processing chamber P1 which is the longest processing time corresponding to one wafer is assumed. m is the reference carry-out interval Tx, and the maximum number n of wafers Wpk that can be processed by the other processing chambers Pk in the section of the reference carry-out interval Tx (here, the processing time Tp1.M) is calculated. Processing time Tp1 in the processing chamber P1. In m, the number of wafers Wpk in which the other processing chambers Pk can be processed is carried out from the cassette container, whereby the waiting time of the processing chamber Pk can be minimized.

Specifically, for example, the following equations (2-1) and (2-2) are simultaneously established to calculate the number n of wafers Wpk. Further, in the following formulas (2-1) and (2-2), Tp1 is a processing time corresponding to one wafer Wp1 in the processing chamber P1, and Tpk is processing corresponding to one wafer Wpk in the other processing chamber Pk. Time, n is an integer satisfying n≧1, m is an integer satisfying m≧1, and k is an integer satisfying k≧2 as described above.

Tp1. m≧Tpk. n (2-1) Tp1. M<Tpk. (n+1) (2-2)

In the following steps S420 to S490, it is determined that m and n make the waiting time of each processing chamber the shortest, and the processing time Tp1 of the processing chamber P1 and the processing time Tpk of the processing chamber Pk are determined. The shorter waiting time among (n+1) (the shorter the reference carry-out interval Tx) is used as the reference carry-out interval Tx, and the wafer carry-out ratio of the wafers Wp1 and Wpk processed in each of the processing chambers P1 and Pk is calculated. According to this, all the processing chambers P1 and Pk can shorten the waiting time of processing. Therefore, the optimization of the waiting time of the entire substrate processing apparatus can be achieved.

Specifically, it is assumed in step S420 that the processing time Tp1 of the processing chamber P1. m is set as the reference carry-out interval Tx, and the waiting time Twk of the other processing chamber Pk is calculated by the following formula (2-3). The processing time Tpk of the processing chamber Pk is assumed in step S430. (n+1) is the reference carry-out interval Tx, and the waiting time Tw1 of the processing chamber P1 is calculated by the following formula (2-4).

Twk=Tp1. m-Tpk. n (2-3) Tw1=Tpk. (n+1)-Tp1. m (2-4)

Thereafter, the value of m is changed in step S440 (for example, the value of m is sequentially increased by 1), and the maximum number of slices n and the waiting times Tw1 and Twk are calculated for each m in steps S410, S420, and S430, and m and n are determined to make the waiting time. Either Tw1 or Twk is the smallest.

Thereafter, in step S450, the waiting times Tw1 and Twk at the time m and n determined in the above-described step S440 are compared, and it is determined which of the waiting times is shorter. When it is determined in step S450 that Twk ≦ Tw1, that is, when the waiting time Twk is short (or the waiting times Tw1 and Twk are equal), the reference wafers Wp1 and Wpk are moved out at intervals in step S460 according to the following formula (2-5). Tx is determined as the processing time Tp1 of the processing chamber P1. m, in step S470, the wafer carry-out ratio (Wp1: Wpk) of each of the wafers Wp1, Wpk is m: n.

Tx=Tp1. M=Tpk. n+Twk (2-5)

According to the above-mentioned reference carry-out interval Tx (=Tp1.M=Tpk.n+Twk), in this section, the wafer Wp1 processed by the processing chamber P1 is carried out by m pieces, and the waiting time of the processing chamber P1 is 0, and processing is performed. The wafer Wk processed by the chamber Pk is carried out by n pieces, and the waiting time of the processing chamber Pk is Twk.

On the other hand, when it is determined in step S450 that the non-Twk ≦ Tw1, that is, the waiting time Tw1 is short, the reference carry-out interval Tx of each of the wafers Wp1 and Wpk is determined as the processing in the following step (2-6) in the step S480. Room Pk processing time Tpk. (n+1), in step S490, the wafer carry-out ratio (Wp1 = Wpk) of each of the wafers Wp1, Wpk is m = n + 1.

Tx=Tp1. m+Tw1=Tpk. (n+1) (2-6)

According to the above-mentioned reference carry-out interval Tx (=Tp1.m+Tw1=Tpk.(n+1)), in the interval, the wafer Wp1 processed by the processing chamber P1 is carried out by m pieces, and the waiting time of the processing chamber P1 is Tw1. The wafer Wpk processed in the processing chamber Pk is carried out by n+1 sheets, and the waiting time of the processing chamber Pk is zero. Further, the reference carry-out interval Tx and the wafer carry-out ratio obtained in the process of FIG. 3 are stored in the memory of the control unit 190 or the like.

(Other specific examples of the processing of calculating the wafer carry-out interval)

Next, another specific example of the process of calculating the wafer carry-out interval will be described with reference to FIG. 10, and the number of wafer carry-out ratios generated by the reference carry-out interval Tx determined by the process of calculating the wafer carry-out ratio is calculated as shown in FIG. The wafer unloading interval of each of the wafers Wp1 and Wpk when the wafer is actually carried out by the cassette container 134 is calculated.

Specifically, as shown in FIG. 10, in step S510, the wafer carry-out ratio (Wp1: Wpk) calculated by the process of FIG. 9 is taken out from the memory of the control unit 190, and the number of wafer carry-out ratios is determined ( Wp1: Wpk) is m: n or m: n+1.

When it is determined in step S510 that the wafer carry-out ratio (Wp1:Wpk) is m:n, the wafer carry-out interval of the wafer Wp1 processed in the processing chamber P1 in step S520 is assumed to be carried out at the reference carry-out interval Tx. The interval between each piece is carried out at each processing time Tp1. In this case, the wafer Wp1 is continuously carried out by the cassette container 134 in each of the m pieces of the reference carry-out interval Tx. In this case, the reference carry-out interval Tx becomes the processing time Tp1 of the processing chamber P1. Therefore, the waiting time of the processing chamber P1 at each of the reference carry-out intervals Tx is 0, and each of the m wafers Wp1 is continuously processed.

Thereafter, in step S530, the wafer unloading interval of the wafer Wk processed in the processing chamber Pk is set to be one interval at a time for each of the reference carry-out intervals Tx and one for each processing time Tpk. In this case, for example, the wafer Wpk is continuously carried out by the cassette container 134 in each of the sections of the reference carry-out interval Tx, and only the waiting time Twk is carried out. That is, after the n pieces are continuously carried out by the cassette container 134, only one waiting time Twk is waited for, and the next n pieces are continuously carried out again by the cassette container 134. In this case, the reference carry-out interval Tx becomes the processing time Tpk of the processing chamber Pk. Since n + Twk, the processing chamber Pk performs continuous processing for each n wafer Wpk in a state where the waiting time Twk exists in each section of the reference carry-out interval Tx.

On the other hand, when it is determined in step S510 that the wafer carry-out ratio (Wp1:Wpk) is m:n+1, the wafer carry-out interval of the wafer Wp1 processed in the processing chamber P1 in step S540 is set to be m at the reference carry-out interval Tx. The interval at which each sheet is carried out at each processing time Tp1. In this case, for example, the wafer Wp1 is carried out by the cassette container 134 in each of the intervals of the reference carry-out interval Tx, and only the waiting time Tw1 is carried out. That is, the m pieces are successively carried out by the cassette container 134 after each processing time Tp1, and wait for the waiting time Tw1, and then the next m pieces are continuously carried out by the cassette container 134 for each processing time Tp1. In this case, the reference carry-out interval Tx becomes the processing time Tp1 of the processing chamber P1. Since m + Ww1, each m wafer Wp1 is processed in the state where the processing chamber P1 has the waiting time Tw1 in each section of the reference carry-out interval Tx.

Thereafter, in step S550, the wafer unloading interval for the wafer Wk processed in the processing chamber Pk is set to be an interval at which n+1 sheets are moved one by one for each processing time Tpk at the reference carry-out interval Tx. In this case, the wafer Wpk is continuously carried out by the cassette container 134 in each of the intervals of the reference carry-out interval Tx. For example, the reference carry-out interval Tx becomes the processing time Tpk of the processing chamber Pk. (n+1), therefore, the processing chamber Pk continuously processes each n+1 wafer Wpk in the state of the waiting time 0 in each of the reference carry-out intervals Tx.

The wafer carry-out ratio calculated by the processing shown in FIGS. 9 and 10 and the wafer carry-out interval are stored in the memory of the control unit 190. When the wafer processing is actually performed, the control unit 190 obtains the wafer carry-out ratio and the wafer carry-out interval obtained from the memory in FIGS. 9 and 10, and controls the transport unit side based on the wafer carry-out ratio and the wafer carry-out interval. The transport mechanism 170 causes the wafers Wp1 and Wpk to be carried out by the cassette container 134, respectively.

According to this, for example, the wafer Wp1 processed by the processing chamber P1 is processed by the cassette container 134 at a longer interval according to the processing time Tp1, and the wafer Wpk processed by the processing chamber Pk is processed accordingly. The time Tpk is carried out by the cassette container 134 at a short interval. In this case, the wafer Wp1 processed by the processing chamber P1 for a long time is reserved for the long time in the common transfer chamber 150, the load lock chambers 160 M, 160 N, the director 137, etc., and the processing time is shorter. The case where the wafer Wpk cannot be carried out by the cassette container 134 can be eliminated. Therefore, the efficiency of the processing of each of the processing chambers P1 and Pk can be improved, and the work efficiency of the entire substrate processing apparatus can be improved.

Further, since the wafers Wp1 and Wpk are carried out by the cassette container 134 at the timing (cycle) of the same reference carry-out interval Tx, the respective intervals of the reference carry-out interval Tx of the wafers Wp1 and Wpk are shifted only from the initial processing. The offset time Tsk of the start timing generated when the wafers Wp1 and Wpk are carried out. Therefore, the timings at which the wafers Wp1 and Wpk are carried out are not simultaneous, and the processing of FIGS. 9 and 10 is applicable not only to the case where the processing time Tp1 of the processing chamber P1 is not an integral multiple of the processing time Tpk of the processing chamber Pk, but also for the processing. The processing time Tp1 of the chamber P1 is exactly the case of an integral multiple of the processing time Tpk of the processing chamber Pk.

Next, the substrate processing apparatus 200 shown in FIG. 6 has a configuration of a substrate processing apparatus having four processing chambers, and the processing for calculating the wafer transfer timing shown in FIGS. 2, 9, and 10 is described with more specific numerical values. Fig. 11 shows the wafer processing time courses of the respective processing chambers processed in accordance with the transfer timings calculated in accordance with Figs. 2, 9, and 10. The horizontal axis of Fig. 11 is time, and the processing time periods of the wafers processed by the four processing chambers P1, P2, P3, and P4 are respectively represented by bar graphs. 11 shows the processing time of each of the processing chambers 140A, 140B, 140C, and 140D corresponding to one wafer, which is 100 seconds, 70 seconds, 60 seconds, and 50 seconds. In this case, the processing chamber having the longest processing time is processed. The chamber 140A, therefore, according to steps S110 and S120 of FIG. 2, the processing chamber 140A is the processing chamber P1, the processing time is Tp1, the processing chamber 140B is the processing chamber P2, the processing time is Tp2, and the processing chamber 140C is the processing chamber P3. The processing time is Tp3, and the processing chamber 140D is the processing chamber P4, and the processing time is Tp4. Therefore, in this case, the transfer timing of the wafer Wp1 and the wafer Wp2 is calculated based on the relationship between the processing chamber P1 and the processing chamber P2, and the transfer timing of the wafer Wp3 is calculated based on the relationship between the processing chamber P1 and the processing chamber P3, and the wafer Wp4 The transfer timing is calculated based on the relationship between the processing chamber P1 and the processing chamber P4. When the transfer timing of the wafers Wp3 and Wp4 is calculated, the reference carry-out interval Tx determined when the transfer timing of the wafer Wp1 and the wafer Wp2 is calculated is used to unify the reference carry-out interval Tx. A method of calculating such a wafer transfer timing will be described below.

First, the transfer timing of the wafer Wp1 and the wafer Wp2 is calculated based on the relationship between the processing chamber P1 and the processing chamber P2, that is, when the waiting times Twk and Tw1 are minimized by m and n in steps S410 to S440 of FIG. m=2, n=3. Next, in steps S450 to S470, the reference carry-out interval Tx of the wafers Wp1 and Wp2 becomes the processing time of the processing chamber P2 of 70 seconds × 3 (= 210 seconds), and the wafer carry-out ratio of the wafers Wp1 and Wp2 (Wp1: Wp2) ) becomes 2:3. The wafer unloading interval of the wafer Wp1 is two intervals at the reference carry-out interval Tx (=210 seconds), and one wafer is ejected at each processing time Tp1 (=100), and the wafer carry-out interval of the wafer Wp2 The interval between each of the three pieces at the reference carry-out interval Tx (=200 seconds) and one piece at each processing time Tp2 (=70 seconds).

Next, the transfer timing of the wafer Wp3 processed in the processing chamber P3 is calculated based on the relationship between the processing chamber P1 and the processing chamber P3. In this case, since the reference carry-out interval Tx has been determined to be 210 seconds, the transfer timing of the wafer Wp3 is calculated using this. Specifically, it is the same as the case of FIG. Therefore, the wafer carry-out ratio (Wp1: Wp3) of the wafer Wp1 processed by the processing chamber P1 and the wafer Wp processed by the processing chamber P3 is 1:3. The wafer carry-out interval of the wafer Wp3 is set to be one of three sheets at a standard carry-out interval Tx (=210 seconds) and one sheet for each processing time Tp3 (=30 seconds).

Next, the transfer timing of the wafer Wp4 processed in the processing chamber P4 is calculated based on the relationship between the processing chamber P1 and the processing chamber P4. In this case, since the reference unloading interval Tx is determined to be 210 seconds, the transfer timing of the wafer Wp4 is calculated using this. Specifically, it is the same as the case of FIG. Therefore, the wafer carry-out ratio Wp1 of the processing chamber P1 and the wafer Wp4 processed by the processing chamber P4 have a wafer transfer ratio (Wp1: Wp4) of 1:4. The wafer carry-out interval of the wafer Wp4 is an interval at which each of the four sheets is carried out at each of the processing time Tp3 (= 50 seconds) in the reference carry-out interval Tx (= 210 seconds).

When the respective wafers Wp1, Wp2, Wp3, and Wp4 are carried out from the cassette container 134 by the above-described wafer transfer timing, the processing time of each of the processing chambers P1, P2, P3, and P4 is as shown in FIG. In this case, in each of the reference carry-out intervals Tx (=210 seconds), the waiting time Tw1 in the processing chamber P1 is 10 seconds, and two wafers Wp1 are continuously processed, and the waiting time in the processing chamber P2 is 0, each 3 The wafer Wp2 was continuously processed, and the waiting time Tw3 was 30 seconds in the processing chamber P3, and the three wafers Wp3 were continuously processed. The waiting time Tw4 in the processing chamber P4 was 10 seconds, and the four wafers Wp4 were continuously processed.

As described above, according to the present embodiment, the wafer transfer timing calculated in advance for each of the processing chambers P1 and Pk is carried out by the cassette container 134 in accordance with the processing times Tp1 and Tpk of the wafers Wp1 and Wpk of the processing chambers P1 and Pk. When the wafers Wp1 and Wpk are processed in the respective processing chambers P1 and Pk, the wafer transfer timing of the cassette container 134 can be optimized in accordance with the processing times Tp1 and Tpk of the processing chambers P1 and Pk. For example, the wafer Wp1 processed by the processing chamber P1 is processed by the cassette container 134 at a longer interval according to the processing time Tp1, and the processing time is shorter than the processing time Tpk of the wafer Wk processed by the processing chamber Pk. The short interval is carried out by the cassette container 134.

Therefore, it is known that the wafer Wp1 processed by the processing chamber P1 is used for a long time to stand in the common transfer chamber 150, the load lock chambers 160 M, 160 N, the director 137, etc., and the processing time is shorter than that of the processing chamber Pk. The case where the round Wpk cannot be carried out by the cassette container 134 can be eliminated. Therefore, the efficiency of the processing of each of the processing chambers P1 and Pk can be improved, and the work efficiency of the entire substrate processing apparatus can be improved.

Further, in the above-described embodiment, the processing for calculating the wafer transfer timing is performed before the actual wafer processing. For example, the heat treatment of the substrate processing apparatus when the power is turned on is performed. Further, it may be performed after component exchange or clean room maintenance for the substrate processing apparatus, or after maintenance.

Further, in the present embodiment, when the wafer transfer timing is calculated based on the processing time of each processing chamber, the wafer transfer timing is calculated before the actual wafer processing, and is calculated based on the predicted value of the processing time of each processing chamber. However, due to the processing environment such as particles attached to the chamber, the actual wafer processing time may deviate from the above predicted value. In addition, in the case where a part of the basic processing conditions (for example, the pressure in the processing chamber, the temperature, the flow ratio of the processing gas, the applied voltage of the counter electrode, etc.) is changed or a new processing condition is added, the processing time may deviate from the above. Predictive value.

As described above, when the processing time of each processing chamber deviates from the predicted value, the wafer transfer timing needs to be recalculated again. According to this, the wafer transfer timing can be calculated according to the actual processing time of each processing chamber, and the unpredictable waiting time caused by the deviation between the processing chambers and the actual processing time can be prevented.

The preferred embodiments of the present invention are described above with reference to the drawings. However, the present invention is not limited to the embodiments, and various modifications and changes can be made without departing from the scope of the invention. Within the scope.

For example, in the above-described embodiment, a so-called group processing type substrate processing apparatus in which a processing unit is connected to a plurality of processing chambers around a common transfer chamber is taken as an example. The present invention is also applicable to, for example, a processing unit connecting a load lock chamber to a processing chamber, and a transport unit. Other types of substrate processing apparatuses including a so-called tandem type substrate processing apparatus in which a plurality of processing units are connected in parallel, and which have a plurality of processing chambers for parallel processing.

(industrial availability)

In the present invention, a substrate processing apparatus that performs a specific treatment on a substrate to be processed and a substrate transfer method of the substrate processing apparatus can be applied.

(effect of the invention)

According to the present invention as described above, it is possible to provide a substrate processing method for a substrate processing apparatus and a substrate processing apparatus. When the processing substrates are processed in parallel in each processing chamber, the processing timing of the substrates to be processed from the substrate storage container can be matched with the processing chambers. According to this, the processing efficiency of each processing chamber can be improved, and the working efficiency of the entire substrate processing apparatus can be improved.

100, 200. . . Substrate processing device

110. . . Processing unit

120. . . Transport unit

130. . . Transfer room

132 (132A~132C). . . Card

134 (134A~134C). . . Card container

136 (136A~136C). . . Gate valve

137. . . Orienter

138. . . Rotating table

139. . . Optical sensor

140 (140A~140C). . . Processing room

140D. . . Processing room or testing room

142 (142A~142D). . . Mounting table

144 (144A~144D). . . Gate valve

150. . . Common transfer room

160 (160 M: 160 N). . . Loading lock room

170. . . Transport unit side transport mechanism

172. . . Abutment

174. . . guide

176. . . Linear motor drive mechanism

180. . . Processing unit side conveying mechanism

190. . . Control department

Fig. 1 is a view showing an example of the configuration of a substrate processing apparatus according to an embodiment of the present invention.

Fig. 2 is a flow chart showing the process of calculating the wafer transfer timing in the embodiment.

FIG. 3 is a flow chart showing a specific example of the calculation process of the wafer carry-out ratio of FIG. 2.

Fig. 4 is a flow chart showing a specific example of the process of calculating the wafer carry-out interval of Fig. 2;

Figure 5 is a diagram showing the processing time of wafers in two processing chambers.

Fig. 6 is a view showing another configuration example of the substrate processing apparatus according to the embodiment of the present invention.

Figure 7 is a diagram showing the processing time of wafers in three processing chambers.

Figure 8 is a diagram showing the processing time of wafers in four processing chambers.

Fig. 9 is a flow chart showing another specific example of the calculation processing of the wafer carry-out ratio of Fig. 2;

Fig. 10 is a flow chart showing another specific example of the process of calculating the wafer carry-out interval of Fig. 2;

Figure 11 is a diagram showing the processing time of wafers in four processing chambers.

100. . . Substrate processing device

110. . . Processing unit

120. . . Transport unit

130. . . Transfer room

132A~132B. . . Card

134A~134B. . . Card container

136A~136B. . . Gate valve

137. . . Orienter

138. . . Rotating table

139. . . Optical sensor

140A~140B. . . Processing room

142A~142B. . . Mounting table

144A~144B. . . Gate valve

150. . . Common transfer room

154M, 154N. . . Gate valve

160M, 160N. . . Loading lock room

162M, 162N. . . Gate valve

170. . . Transport unit side transport mechanism

172. . . Abutment

174. . . guide

176. . . Linear motor drive mechanism

180. . . Processing unit side conveying mechanism

190. . . Control department

Claims (9)

A substrate processing apparatus comprising: a processing unit having a plurality of processing chambers for performing specific processing on a substrate to be processed; a transport unit connected to the processing unit; and a transport unit side transporting mechanism provided in the transport unit for The processing substrate to be processed in the substrate storage container is transported to the processing unit; and the processing unit side transporting mechanism is provided in the processing unit for transporting the processed substrate transported by the transport unit to the processing chamber; The control means for calculating the number of the substrates to be transported by the substrate storage container in accordance with the number of the substrates to be processed and the carry-out interval when the substrate to be processed is carried out by the substrate storage container Processing the substrate transfer timing, and the substrate to be processed is carried out from the substrate storage container according to the transfer timing; and the control means determines the reference carry-out interval based on the processing time of the processed substrate in each of the processing chambers. Each of the intervals of the reference carry-out interval is in the above The number of the substrates to be processed that can be processed by the chamber is determined, and the ratio of the number of the substrates to be processed is determined. The interval at which the substrates are processed is set to be in the processing chambers at the reference carrying interval. The number of sheets of the substrate to be processed is the interval at which one sheet is carried out for each processing time of the substrate to be processed in each of the processing chambers. The substrate processing apparatus of claim 1, wherein the ratio of the number of the substrates to be processed is based on the processing chambers In the processing time of the substrate to be processed, it is assumed that the processing time of the processing chamber having the longest processing time among the processing chambers is the reference carrying-out interval, and the processing can be processed in another processing chamber in the interval of the reference carrying-out interval. Calculated by processing the maximum number of substrates. The substrate processing apparatus according to claim 1 or 2, wherein the reference carry-out interval is determined by shortening the waiting time in accordance with a waiting time in each section of the reference carry-out interval of each of the processing chambers. A substrate transfer method of a substrate processing apparatus, comprising: a processing unit having a plurality of processing chambers for performing specific processing on a substrate to be processed; a transport unit connected to the processing unit; and a transport unit side transport mechanism; The transport unit is configured to transport the substrate to be processed in the substrate storage container to the processing unit, and the processing unit side transfer mechanism is provided in the processing unit, and the substrate to be processed is transported by the transport unit And the conveyance to the processing chamber; and the number of the substrates to be processed in the processing chambers when the substrate to be processed is carried out by the substrate storage container, and the carrying-out interval are calculated, and the substrate storage container is transported to the processing chambers. The transport timing of the substrate to be processed; the ratio of the number of transported substrates to be processed is determined according to the processing time of the substrate to be processed in each of the processing chambers, and the basis of the reference carry-out interval is determined according to the interval of the reference carry-out interval The above-mentioned processed substrate that can be processed in each of the above processing chambers The maximum number of pieces to be obtained by; The carrying-out interval of the substrate to be processed is set to be the number of times the number of the substrates to be processed is compared in the respective processing chambers at the reference carrying-out interval, and the processing time of each of the processed substrates in the respective processing chambers The interval at which one sheet is carried out; when the substrate to be processed is processed, the substrate to be processed is carried out from the substrate storage container in accordance with the transfer timing. The substrate transfer method of the substrate processing apparatus according to the fourth aspect of the invention, wherein the number of the substrates to be processed is assumed to be the processing time in each of the processing chambers based on the processing time of the substrate to be processed in each of the processing chambers. When the processing time of the longest processing chamber is the reference carrying-out interval, the maximum number of the substrates to be processed that can be processed in the other processing chambers in the interval of the reference carrying-out interval is calculated. The substrate transfer method of the substrate processing apparatus according to the fourth or fifth aspect of the invention, wherein the reference carry-out interval is made based on a waiting time in each section of the reference carry-out interval of each of the processing chambers, and the waiting time is shortened. Decide. A substrate transporting method of a substrate processing apparatus, wherein a plurality of the substrates to be processed, which are sequentially stored in a substrate storage container, are sequentially transported to a processing chamber to be processed in accordance with a predetermined transfer timing, and thus are paralleled in a plurality of processing chambers. A substrate transfer method of a substrate processing apparatus that performs the processing on the substrate to be processed; and has the following steps: a step of calculating a ratio of the number of substrates to be processed in each of the processing chambers in a section of the reference carrying interval determined in accordance with a processing time of the substrate to be processed in each of the processing chambers; and a number of carrying out the substrates to be processed The step of calculating the carry-out interval of the substrate to be processed in each of the processing chambers is calculated, and the transfer timing is obtained based on the number of carry-outs of the substrate to be processed and the carry-out interval calculated in the respective steps. The substrate transfer method of the substrate processing apparatus according to the seventh aspect of the invention, wherein the step of calculating the number of times of transporting the substrate to be processed has the following step: assuming that the processing chamber having the longest processing time among the processing chambers is processed 1 When the processing time of the substrate to be processed is the reference carrying-out interval, the step of calculating the maximum number n of substrates to be processed that can be processed in another processing chamber in the interval of the reference carrying interval is assumed; When the processing time of the processing substrate for one processing chamber is the reference carrying-out interval, the step of calculating the waiting time of the other processing chambers in the interval of the reference carrying-out interval is calculated; and it is assumed that n+1 pieces of the above-mentioned objects are processed in the other processing chambers. When the processing time of the processing substrate is the reference carrying-out interval, the step of calculating the waiting time of the processing chamber having the longest processing time in the interval of the reference carrying-out interval is calculated; and the waiting time is compared, and the processing chamber having the longest processing time is When the waiting time is below the waiting time of the other processing chambers mentioned above, the above will be The reference carry-out interval is determined as the processing time for processing the one substrate to be processed in the processing chamber having the longest processing time, and the ratio of the number of carried out substrates to be processed is 1:n, and the waiting time of the processing chamber having the longest processing time When the waiting time is longer than the other processing chambers, the reference carrying-out interval is determined as the processing time for the other processing chambers to process the n+1 pieces of the processed substrate, and the number of the substrates to be processed is set to 1:n. +1; a step of calculating a carry-out interval of the substrate to be processed, wherein the number of carry-outs of the substrate to be processed in the processing chamber having the longest processing time is the same when the number of times of transporting the substrate to be processed is 1:n The interval between the substrates to be carried out at the reference carry-out interval is the interval at which the number of the substrates to be processed in the other processing chambers is n pieces in the reference carry-out interval. When the number of carry-outs of the substrate to be processed is 1:n+1, the processing substrate of the processing chamber having the longest processing time is The number of times of unloading is set to be at intervals in which one of the reference transport intervals is carried out, and the number of times of transporting the substrate to be processed in the other processing chamber is n+1 pieces in the reference carry-out interval. The step of moving out one piece of each processing time. The substrate transfer method of the substrate processing apparatus of the seventh aspect of the invention, wherein the step of calculating the number of carry-out ratios of the substrate to be processed has the following Step: When it is assumed that the processing time for processing the m-th substrate to be processed in the processing chamber having the longest processing time among the processing chambers is the reference carrying-out interval, it is calculated that it can be processed in another processing chamber in the interval of the reference carrying-out interval. a step of maximizing the number n of substrates to be processed; and assuming that the processing time for processing the m substrates to be processed in the processing chamber having the longest processing time is the reference carrying interval, calculating the other processing chambers in the interval of the reference carrying interval a step of waiting for a time; assuming that the processing time of the n+1 pieces of the substrate to be processed is the reference carry-out interval in the other processing chamber, the step of calculating the waiting time of the processing chamber having the longest processing time in the interval of the reference carrying interval Changing m to calculate the maximum number n of substrates to be processed, the waiting time of the other processing chambers, and the waiting time of the processing chamber having the longest processing time, and determine the processing chamber in which the waiting time of the other processing chambers and the processing time are the longest. The steps of waiting time to become the smallest m, n: and comparing the determined m, n The waiting time of the other processing chamber is the waiting time of the processing chamber having the longest processing time, and when the waiting time of the processing chamber having the longest processing time is equal to or less than the waiting time of the other processing chamber, the reference carrying out interval is determined as The processing time of the m-processed substrate is processed by the processing chamber having the longest processing time, and the ratio of the number of the substrates to be processed is set to m:n, and the waiting time of the processing chamber having the longest processing time is larger than that of the other processing chambers. In the waiting time, the reference carrying-out interval is determined as the processing time in which the other processing chamber processes n+1 pieces of the processed substrate, and the substrate to be processed is moved. The ratio of the number of outputs is set to m:n+1; the step of calculating the carry-out interval of the substrate to be processed has the step of: when the number of carry-outs of the substrate to be processed is m:n, the processing chamber having the longest processing time The number of times of carrying out the substrate to be processed is an interval between each of the m pieces in the reference carry-out interval and one piece at a time of each processing time, and the number of times of transporting the substrate to be processed in the other processing chamber is The interval between the n pieces in the reference carry-out interval and the one out of each of the processing times, and the processing time in which the processing time is the longest when the number of the substrates to be processed is m:n+1 The number of times of carrying out the substrate to be processed is an interval between each of the m-th order of the reference carry-out interval and one sheet at a time of each processing time, and the number of times of transporting the substrate to be processed in the other processing chamber is It is a step of setting the interval between n+1 pieces of the reference carry-out interval and one piece of each of the processing times.