JP4610317B2 - Substrate processing apparatus and substrate transfer method for substrate processing apparatus - Google Patents

Description

  The present invention relates to a substrate processing apparatus for performing a predetermined process on a substrate to be processed such as a semiconductor wafer and a glass substrate (for example, a liquid crystal substrate), and a substrate transfer method of the substrate processing apparatus.

  In general, this type of substrate processing apparatus includes a processing unit having a plurality of processing chambers for performing predetermined processing on a substrate to be processed, such as a semiconductor wafer (hereinafter also simply referred to as “wafer”), and a load lock on the processing unit. A transport unit connected through the chamber is provided (see, for example, Patent Document 1).

  For example, in the case of a cluster tool type substrate processing apparatus, the processing unit includes a plurality of processing chambers and a plurality of processing chambers around a common transfer chamber formed in a polygon, as described in FIG. Constructed with airtight connection of load lock chambers. A processing unit-side transfer mechanism including a transfer arm is provided in the common transfer chamber, and wafers are transferred into and out of the plurality of processing chambers and the load lock chamber by the processing unit-side transfer mechanism. The transfer unit is also provided with a transfer unit-side transfer mechanism including a transfer arm and the like. The transfer unit-side transfer mechanism allows a transfer between the cassette container (substrate storage container) in which a wafer is stored and the load lock chamber. A wafer is carried in and out.

  In such a substrate processing apparatus, when a predetermined process is performed on a wafer stored in a cassette container, first, an unprocessed wafer is unloaded from the cassette container by the transfer unit side transfer mechanism in the transfer unit. The unprocessed wafer unloaded from the cassette container is loaded into a positioning device (for example, an orienter or pre-alignment stage) provided in the transfer unit and positioned before being loaded into the load lock chamber. The unprocessed wafer thus positioned is unloaded from the positioning device and loaded into the load lock chamber.

  Unprocessed wafers loaded into the load lock chamber are unloaded from the load lock chamber by the processing unit-side transfer mechanism, loaded into the processing chamber, and subjected to predetermined processing. The processed wafer that has been processed in the processing chamber is unloaded from the processing chamber by the processing unit side transfer mechanism and returned to the load lock chamber. The processed wafer returned to the load lock chamber is returned to the cassette container by the transfer unit side transfer mechanism.

  In order to improve the throughput of processing in each processing chamber in such a substrate processing apparatus, it is desirable to wait for an unprocessed wafer as close to the processing chamber as possible, so that processing is performed in the processing chamber. In the meantime, unprocessed wafers are unloaded from the cassette container one after another, and these wafers are put on standby in a common transfer chamber, a load lock chamber, a positioning device, and the like. When the processing of one wafer is completed in the processing chamber, the processed wafer is immediately accommodated in the cassette container, and the standby unprocessed wafers are sequentially fed so that the next unprocessed wafer is immediately carried into the processing chamber. It is like that.

  In addition, when wafers are processed in parallel in each processing chamber, the wafer processed in each processing chamber is unloaded from the cassette container at any transfer timing in order to improve the operating rate of each processing chamber. It is important to decide what to do. In this regard, conventionally, when the next unprocessed wafer is unloaded from the cassette container, the remaining times of the processes performed in the respective process chambers are compared and processed in the process chamber having the shortest remaining time. Unprocessed wafers were detected from the cassette container and carried out. According to this, for example, a processing chamber with a shorter remaining processing time can process the next wafer earlier. Therefore, by removing the wafers from the cassette container in order of decreasing remaining time, the operating rate of each processing chamber can be increased. Can be improved.

JP 2002-237507 A

  By the way, in each processing chamber, for example, different types of processing such as etching processing and film forming processing are performed, and even in the same type of processing, processing with different processing conditions is often performed. (For example, the time from when a wafer is loaded until the processing of the wafer is completed and unloaded and the next wafer can be loaded) is often different from each other.

  However, in the conventional apparatus as described above, when the next unprocessed wafer is unloaded from the cassette container, attention is paid only to the remaining processing time of each processing chamber, and the next container is transferred from the cassette container in the order of the shortest remaining time. Since the transfer timing is such that unprocessed wafers are unloaded, the difference in processing time between the processing chambers as described above has not been taken into consideration.

  For this reason, for example, if the remaining processing time is shorter in the processing chamber having a longer processing time than in the processing chamber having a shorter processing time, the wafer in the processing chamber having a longer processing time is first unloaded from the cassette container. There is a situation where such wafers wait for a long time in a common transfer chamber, load lock chamber, positioning device, etc., and the wafers in the processing chamber with a short processing time cannot be unloaded from the cassette container. There is a problem that the throughput of the entire substrate processing apparatus is lowered due to the decrease.

More specifically, for example, when the processing in the processing chamber P1 having a long processing time and the processing in the processing chamber P2 having a short processing time are performed in parallel, the processing chamber P1 having a longer processing time performs processing. If the remaining time is short, the wafer WP1 to be processed in the processing chamber _P1 becomes the next target to be taken out from the cassette container.

In this case, for example, another wafer to be processed next in the processing chamber P1 is already waiting in the common transfer chamber, so that the processing in the processing chamber P1 is completed and the wafer _WP1 is unloaded from the cassette container. However, the wafer _WP1 cannot be processed immediately. This is because even if the wafers already waiting in the common transfer chamber, the load lock chamber, the positioning device, etc. are sequentially fed, the processing from the cassette container is continued until the processing of another wafer previously loaded into the processing chamber P1 is completed. This is because the unloaded wafer _WP1 waits in a common transfer chamber, a load lock chamber, a positioning device, and the like.

In this case, even if the processing in the processing chamber P2 with a short processing time ends immediately and is not in operation, the wafer _WP2 processed in the processing chamber P2 with a short processing time cannot be unloaded from the cassette container. . For this reason, since an extra waiting time is generated in the processing chamber P2 having a short processing time, the operation rate of the processing chamber P2 is reduced, and the throughput of the entire substrate processing apparatus is reduced.

  Therefore, the present invention has been made in view of such problems, and the object of the present invention is to process the substrate to be processed from the substrate storage container when processing the substrate to be processed in each processing chamber in parallel. The transfer timing can be adjusted to the processing time of each processing chamber, thereby improving the operating rate in each processing chamber and improving the overall throughput of the substrate processing apparatus and the substrate transfer of the substrate processing apparatus. It is to provide a method.

  In order to solve the above problems, according to an aspect of the present invention, a processing unit having a plurality of processing chambers for performing a predetermined process on a substrate to be processed, a transfer unit connected to the processing unit, A transport unit-side transport mechanism that transports the substrate to be processed, which is provided in the transport unit and is accommodated in the substrate storage container, to the processing unit; and the substrate to be processed that is provided in the processing unit and transported from the transport unit. A substrate processing apparatus comprising a processing unit side transfer mechanism for transferring to the processing chamber, wherein each of the processing chambers is moved from the substrate storage container to the respective processing chambers based on a processing time of the substrate to be processed in each of the processing chambers. The transport timing of the substrate to be processed transported toward the processing chamber is obtained, and the substrate to be processed is unloaded from the substrate storage container according to the transport timing. A substrate processing apparatus, characterized in that it comprises a control means is provided.

  In order to solve the above problems, according to another aspect of the present invention, a processing unit having a plurality of processing chambers for performing predetermined processing on a substrate to be processed, a transfer unit connected to the processing unit, A transport unit side transport mechanism that transports the substrate to be processed, which is provided in the transport unit and accommodated in the substrate storage container, to the processing unit, and the substrate that is disposed in the processing unit and transported from the transport unit. A substrate transport method of a substrate processing apparatus comprising a processing unit side transport mechanism for transporting a substrate to the processing chamber, wherein the substrate is processed for each processing chamber based on a processing time of the substrate to be processed in each processing chamber. When the transport timing of the substrate to be processed transported from the storage container toward the processing chambers is obtained, and when processing the substrate to be processed, Substrate transfer method of a substrate processing apparatus, characterized in that unloading the substrate to be processed from the substrate storage container I is provided.

  According to the above apparatus or method, the substrate to be processed is unloaded from the substrate storage container in accordance with the transfer timing previously determined for each processing chamber based on the processing time of the substrate to be processed in each processing chamber. When processing substrates to be processed in parallel, the transfer timing of the substrate to be processed from the substrate storage container can be adjusted to the processing time of each processing chamber, thereby improving the operation rate in each processing chamber and Throughput of the entire processing apparatus can be improved. For example, a substrate to be processed to be processed in a processing chamber having a long processing time can be unloaded from the substrate storage container at a long interval, and a substrate to be processed to be processed in a processing chamber having a short processing time can be unloaded from the substrate storage container at a short interval. it can. As a result, the substrate to be processed in the processing chamber having a long processing time as in the prior art waits for a long time in the common transfer chamber, the load lock chamber, the positioning device, etc. As a result, it is possible to eliminate the situation in which it is not possible to unload the substrate, so that the operating rate in each processing chamber can be improved and the throughput of the entire substrate processing apparatus can be improved.

  Further, in the above apparatus or method, the transport timing of the substrate to be processed is, for example, the ratio of the number of substrates to be processed and the unloading interval for each processing chamber when the substrate to be processed is unloaded from the substrate storage container. . Here, the ratio of the number of substrates to be processed is the ratio of the number of substrates to be processed for each processing chamber being unloaded from the substrate storage container, and the unloading interval of the substrates to be processed is unloaded from the substrate storage container. This is the unloading interval of the substrate to be processed for each processing chamber.

  In this case, the unloading number ratio of the substrates to be processed is such that the substrates to be processed that can be processed in each processing chamber within each section of the reference unloading interval determined based on the processing time of the substrates to be processed in each processing chamber. The unloading interval of the substrates to be processed is calculated based on the maximum unloading number, and the number of unloading substrate ratios of the substrates to be processed at the reference unloading interval is determined for each processing chamber. It is desirable to set the interval for carrying out one sheet every processing time.

  By determining the transfer timing of the substrate to be processed from the substrate storage container in this way, for example, the maximum number of sheets that can be processed in another processing chamber within the time during which the processing substrate is processed in one processing chamber. Since only the substrate to be processed can be processed, the processing waiting time of each processing chamber can be reduced and the operating rate of each processing chamber can be improved. In addition, the processing substrate is unloaded from the substrate storage container one by one or a plurality of substrates at the same reference unloading interval for each processing chamber, so that the timing of unloading from the substrate storage container is different for each processing substrate in each processing chamber. For example, since the time is always shifted by the time difference of the start timing that occurs when the first substrate is transported for each substrate to be processed in each processing chamber, the timing for unloading the substrate to be processed is not simultaneous. Thereby, it is possible to prevent the waiting time due to the wafer unloading waiting in each processing chamber.

  In the above apparatus or method, the ratio of the number of unprocessed substrates to be processed is, for example, based on the processing time of the substrate to be processed in each of the processing chambers, of the processing chamber having the longest processing time among the processing chambers. When the processing time is the reference carry-out interval, the processing time is obtained based on the maximum number of substrates to be processed that can be processed in another processing chamber within the interval of the reference carry-out interval. Thus, by determining the reference carry-out interval by determining the reference carry-out interval based on the processing time of the processing chamber having the longest processing time, the reference carry-out interval can be easily determined. The number ratio can be easily calculated.

  In the above apparatus or method, it is preferable that the reference carry-out interval is determined based on the wait time in each section of the reference carry-out interval in each processing chamber so that the wait time is shortened. Thereby, since the waiting time of each processing chamber can be optimized, the throughput of the entire substrate transfer apparatus can be further improved.

  In order to solve the above-described problem, according to another aspect of the present invention, a plurality of the substrates to be processed accommodated in a substrate storage container are respectively transported to a processing chamber to be processed and are determined in advance. The substrate transport method of the substrate processing apparatus performs processing on the substrate to be processed in parallel in a plurality of processing chambers by sequentially transporting the substrate in the processing chamber, wherein the transport timing is the processing of the substrate to be processed in each processing chamber. A step of obtaining a ratio of the number of substrates to be processed for each processing chamber within a reference unloading interval determined based on time, and a step of determining the number of substrates to be processed based on the ratio of the number of substrates to be processed There is provided a substrate transfer method for a substrate processing apparatus, comprising a step of determining a carry-out interval of the substrate to be processed.

  Further, in the above method, the step of obtaining the ratio of the number of substrates to be processed includes the processing time for processing one substrate to be processed in the processing chamber having the longest processing time among the processing chambers. When the interval is set, the step of obtaining the maximum number n of the substrates to be processed that can be processed in another processing chamber within the interval of the reference carry-out interval, and one processing target in the processing chamber having the longest processing time A step of obtaining a waiting time of the other processing chamber in the interval of the reference unloading interval when a processing time for processing the substrate is set as a reference unloading interval; and tentatively, n + 1 substrates to be processed in the other processing chamber When the waiting time of the processing chamber with the longest processing time in the interval of the reference unloading interval when the processing time to be processed is set as the reference unloading interval is compared with these waiting times, When the waiting time of the processing chamber having the longest processing time is equal to or shorter than the waiting time of the other processing chamber, the processing time for processing one substrate in the processing chamber having the longest processing time is set as the reference carry-out interval. And when the waiting time of the processing chamber having the longest processing time is larger than the waiting time of the other processing chamber, the reference unloading interval is set to And determining the processing time for processing the n + 1 substrates to be processed in another processing chamber, and setting the ratio of the number of substrates to be processed to 1: n + 1.

  In this case, in the step of obtaining the unloading interval of the substrates to be processed, when the unloading number ratio of the substrates to be processed is 1: n, the unloading interval of the substrates to be processed in the processing chamber having the longest processing time is , An interval for carrying out the substrates one by one at the reference carrying-out interval, and an interval for carrying out the substrates to be processed in the other processing chambers is an interval for carrying out n pieces at the reference carrying-out interval one by one for each processing time. When the ratio of the number of substrates to be processed is 1: n + 1, the interval between the number of substrates to be processed in the processing chamber with the longest processing time is the interval at which the substrates are unloaded one by one at the reference unloading interval. The interval for unloading the substrates to be processed in the other processing chamber may include a step of setting n + 1 sheets at the reference unloading interval to unload one by one for each processing time.

  Thus, by determining the reference carry-out interval by determining the reference carry-out interval based on the processing time of the processing chamber having the longest processing time, the reference carry-out interval can be easily determined. The number ratio can be easily calculated. Further, the reference carry-out interval is determined so that the waiting time of either the treatment chamber with the longest processing time or the other treatment chamber is the shortest, and the substrate to be processed is transferred from the substrate storage container based on the reference carry-out interval. Since the timing (for example, the ratio of the number of substrates to be processed and the interval between the substrates to be processed) is obtained, the waiting time of each processing chamber can be optimized, so that the throughput of the entire substrate transfer apparatus can be further improved. it can.

  Further, in the above method, the step of obtaining the ratio of the number of substrates to be processed includes a processing time for processing the m substrates to be processed in a processing chamber having the longest processing time among the processing chambers as a reference unloading interval. In this case, the step of obtaining the maximum number n of the substrates to be processed that can be processed in another processing chamber within the interval of the reference carry-out interval, and the m substrates to be processed in the processing chamber having the longest processing time. The waiting time of the other processing chamber in the interval of the reference unloading interval when the processing time for processing is set as the reference unloading interval, and temporarily processing the n + 1 substrates to be processed in the other processing chamber Determining the waiting time of the processing chamber with the longest processing time within the interval of the reference unloading interval when the processing time to be used is the reference unloading interval, and changing the m to the maximum of the substrate to be processed N, the waiting time of the other processing chamber, and the waiting time of the processing chamber with the longest processing time are obtained, and the waiting time of the processing chamber with the longest processing time and the waiting time of the other processing chamber is minimized. The process time is the longest by comparing the step of determining m and n with the waiting time of the other processing chamber at the determined m and n and the waiting time of the processing chamber with the longest processing time. When the waiting time of the processing chamber is equal to or shorter than the waiting time of the other processing chamber, the reference carry-out interval is determined as a processing time for processing m substrates to be processed in the processing chamber having the longest processing time. When the ratio of the number of processing substrates to be carried out is m: n and the waiting time of the processing chamber with the longest processing time is longer than the waiting time of the other processing chamber, the reference unloading interval is set to n + 1 in the other processing chamber. Process the substrate to be processed The unloading ratio of the substrate to be processed and determines the processing time m: may include a step of the n + 1.

  In this case, in the step of obtaining the unloading interval of the substrates to be processed, when the unloading number ratio of the substrates to be processed is m: n, the unloading interval of the substrates to be processed in the processing chamber having the longest processing time is The number of the substrates to be processed in the other processing chambers is set to an interval for carrying out the n substrates at the reference carry-out interval. When an unloading ratio of the substrates to be processed is m: n + 1, the interval of unloading the substrates to be processed in the processing chamber with the longest processing time is the reference unloading interval. The interval for carrying out m pieces at intervals is taken as an interval for carrying out one piece at each processing time, and the number of carrying-outs of the substrates to be processed in the other processing chambers is set at n + 1 pieces at the reference carrying-out interval for every processing time. Interval to carry out one by one It may have a step of.

  According to this, by determining the reference carry-out interval on the basis of the carry-out ratio of the substrates to be processed based on the m times of the treatment time of the processing chamber having the longest processing time, it is easy to determine the reference carry-out interval. Therefore, it is possible to easily calculate the ratio of the number of substrates to be processed. Further, the reference carry-out interval is determined so that the waiting time of either the treatment chamber with the longest processing time or the other treatment chamber is minimized, and the substrate to be processed is transferred from the substrate storage container based on the reference carry-out interval. Since the timing (for example, the unloading number ratio of the substrates to be processed and the unloading interval of the substrates to be processed) is obtained, the waiting time of each processing chamber can be optimized, so that the throughput of the entire substrate transfer apparatus can be further improved. it can.

  As described above, according to the present invention, when processing a substrate to be processed in each processing chamber in parallel, the transfer timing of the substrate to be processed from the substrate storage container can be adjusted to the processing time of each processing chamber. Thus, it is possible to provide a substrate processing apparatus and a substrate transfer method for the substrate processing apparatus that can improve the operation rate in each processing chamber and improve the throughput of the entire substrate processing apparatus.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

(Configuration example of substrate processing equipment)
First, a substrate processing apparatus according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a substrate processing apparatus according to an embodiment of the present invention. The substrate processing apparatus 100 includes a plurality of processing units 110 that perform various processes such as a film forming process and an etching process on a substrate to be processed, for example, a semiconductor wafer (hereinafter also simply referred to as “wafer”) W. And a transfer unit 120 that carries the wafer W in and out of the unit 110. The transfer unit 120 has a transfer chamber 130 that is shared when transferring the wafer W.

The transfer chamber 130 of the transfer unit 120 is configured by a box having a substantially polygonal cross section in which an inert gas such as N ₂ gas or clean air is circulated. A plurality of cassette stands 132 (132A and 132B in this case) are arranged side by side on one side of the transfer chamber 130 that forms the long side of the substantially polygonal cross section. Each of the cassette bases 132A and 132B is configured to be able to place cassette containers 134A and 134B as an example of a substrate storage container.

Each cassette container 134A, 134B can accommodate, for example, a maximum of 25 wafers W placed in multiple stages at an equal pitch, and the inside has a sealed structure filled with, for example, an N ₂ gas atmosphere. Yes. The transfer chamber 130 is configured such that the wafer W can be transferred into and out of the transfer chamber 130 via gate valves 136A and 136B.

  Here, wafers to be processed in processing chambers 140A and 140B described later are stored in the cassette containers 134A and 134B, respectively. However, if it is known which wafer is processed in which processing chamber, the wafers to be processed in the respective processing chambers 140A and 140B do not necessarily have to be stored separately in the cassette containers 134A and 134B. For example, wafers to be processed in the processing chambers 140A and 140B may be mixed in one or both of the cassette containers 134A and 134B. Further, FIG. 1 shows an example in which two cassette containers 134A and 134B can be mounted on each cassette table 132A and 132B, respectively, but the number of cassette tables and cassette containers is not limited to this. For example, three or more units may be used.

  A positioning surface having an end portion of the transfer chamber 130, that is, a measurement surface forming a short side having a substantially polygonal cross section, is provided with a rotary mounting table 138 and an optical sensor 139 for optically detecting the peripheral portion of the wafer W. An orienter (pre-alignment stage) 137 as an apparatus is provided. The orienter 137 detects the orientation flat or notch of the wafer W and performs alignment.

  The processing unit 110 has a processing chamber 140 (140A, 140B) for performing predetermined processing such as film formation processing (for example, plasma CVD processing) and etching processing (for example, plasma etching processing) on the wafer. The processing performed in each processing chamber 140A, 140B may be the same type of processing, or may be different processing. Each wafer is subjected to a predetermined process in each of the processing chambers 140A and 140B based on information (process recipe) indicating processing steps such as an etching process stored in advance in a memory or the like of the control unit. The processing chamber in which each wafer is processed may be determined by the above process recipe, for example. The processing unit 110 includes a common transfer chamber 150 for transferring wafers into and out of the processing chambers 140A and 140B. The common transfer chamber 150 is formed in a polygonal shape (for example, a hexagon), and the processing chambers 140A and 140B are disposed around the common transfer chamber 150 via gate valves 144A and 144B, respectively.

  Each of the processing chambers 140A and 140B performs, for example, the same type of processing or different types of processing on the wafer W. In the processing chambers 140A and 140B, mounting tables 142A and 142B for mounting the wafer W are provided, respectively. Note that the number of processing chambers 140 is not limited to two, and may be additionally provided.

  Around the common transfer chamber 150, first and second load lock chambers 160M and 160N as an example of a vacuum preparation chamber connected to the transfer unit 120 are disposed. Specifically, the tips of the first and second load lock chambers 160M and 160N are connected around the common transfer chamber 150 via gate valves (vacuum side gate valves) 154M and 154N, respectively. The base ends of the second load lock chambers 160M and 160N are connected to the other side surfaces of the transfer chamber 130 that form long sides having a substantially polygonal cross section via gate valves (atmosphere side gate valves) 162M and 162N, respectively.

  The first and second load lock chambers 160M and 160N are configured to be evacuated and have a function of temporarily holding the wafer W and adjusting the pressure to pass to the next stage. The load lock chambers 160M and 160N may be configured to further have a cooling mechanism or a heating mechanism.

  As described above, the common transfer chamber 150 and the processing chambers 140A and 140B and the common transfer chamber 150 and the load lock chambers 160M and 160N can be opened and closed in an airtight manner, and are formed into cluster tools. Thus, communication with the inside of the common transfer chamber 150 is possible as required. The first and second load lock chambers 160M and 160N and the transfer chamber 130 are also configured to be openable and closable.

  In the common transfer chamber 150, for example, a processing unit-side transfer mechanism 180 including an articulated arm configured to be able to bend, stretch, move up and down, and turn is provided. The processing unit side transport mechanism 180 can access the load lock chambers 160M and 160N and the processing chambers 140A and 140B. For example, when a wafer is loaded into each of the load lock chambers 160M and 160N, the wafer is loaded into the processing chamber 140A or 140B where the wafer is processed by the processing unit side transfer mechanism 180.

  The processing unit side transfer mechanism 180 is constituted by a double arm mechanism having two picks, and can handle two wafers at a time. Thereby, for example, when a wafer is carried in and out of each processing chamber 140A, 140B, the processed wafer and the unprocessed wafer can be exchanged. Note that the number of picks of the processing unit side transport mechanism 180 is not limited to the above, and for example, a single arm mechanism having only one pick may be used.

  In the transfer chamber 130, a transfer unit side transfer mechanism 170 for transferring the wafer W along the longitudinal direction (the arrow direction shown in FIG. 1) is provided. The base 172 to which the transport unit side transport mechanism 170 is fixed is supported so as to be slidable on a guide rail 174 provided along the length direction in the center of the transport chamber 130. The base 172 and the guide rail 174 are each provided with a mover and a stator of a linear motor. A linear motor drive mechanism 176 for driving the linear motor is provided at the end of the guide rail 174. A controller 190 is connected to the linear motor drive mechanism 176. Thus, the linear motor drive mechanism 176 is driven based on the control signal from the control unit 190, and the transport unit side transport mechanism 170 moves along the guide rail 174 in the direction of the arrow together with the base 172.

  Similarly to the processing unit side transfer mechanism 180, the transfer unit side transfer mechanism 170 is also composed of a double arm mechanism having two picks so that two wafers can be handled at a time. Thus, for example, when a wafer is carried in / out of the cassette container 134, the orienter 137, the load lock chambers 160M, 160N, etc., the wafer can be carried in / out so as to be exchanged. Note that the number of picks of the processing unit side transport mechanism 180 is not limited to the above, and for example, a single arm mechanism having only one pick may be used.

  In the substrate processing apparatus 100, in addition to the control of the transfer mechanisms 170 and 180, the gate valves 136, 144, 154, 162, the orienter 137 and the like, a process for obtaining the transfer timing of the wafer from the cassette container 134, which will be described later, A control unit 190 is provided for controlling the operation of the entire substrate processing apparatus including control for unloading the wafer from the cassette container 134 based on the wafer transfer timing. The control unit 190 includes, for example, a microcomputer that constitutes the main body of the control unit 190, a memory that stores various data, and the like.

(Operation of substrate processing equipment)
Next, the operation of the substrate processing apparatus configured as described above will be described. The wafer W carried out of the cassette container 134A or 134B by the transfer unit side transfer mechanism 170 is transferred to the orienter 137, transferred to the rotary mounting table 138 of the orienter 137, and positioned there. The positioned wafer is unloaded from the orienter 137 and loaded into the load lock chamber 160M or 160N. At this time, if the processed wafer is in the load lock chamber 160M or 160N, the processed wafer is unloaded and then the unprocessed wafer is loaded.

  The wafers loaded into the load lock chamber 160M or 160N are unloaded from the load lock chamber 160M or 160N by the processing unit side transfer mechanism 180, and loaded into the processing chamber 140A or 140B where the wafer is processed, and subjected to predetermined processing. Is done. The processed wafer that has been processed in the processing chamber 140A or 140B is unloaded from the processing chamber 140A or 140B by the processing unit side transfer mechanism 180 and returned to the load lock chamber 160M or 160N. The processed wafer returned to the load lock chamber 160M or 160N is returned to the cassette container 134A or 134B by the transfer unit side transfer mechanism 170.

  In order to improve the throughput of processing in the processing chamber 140A or 140B, it is desirable to place the unprocessed wafer as close as possible to the processing chamber and wait, so that processing in the processing chamber 140A or 140B is performed. In the meantime, unprocessed wafers are unloaded one after another from the cassette container 134A or 134B, and these wafers are put on standby in the common transfer chamber 150, the load lock chamber 160M or 160N, the orienter 137, and the like. When the processing of one wafer is completed in the processing chamber 140A or 140B, the processed wafer is immediately returned to the cassette container 134A or 134B, and the standby unprocessed wafers are sequentially fed and waiting in the common transfer chamber 150. The next unprocessed wafer is immediately carried into the process chamber 140A or 140B.

  In such a substrate processing apparatus 100, when wafers are processed in parallel in the processing chambers 140A and 140B, the processing chambers 140A and 140B are also used to improve the operating rate of the processing chambers 140A and 140B. It is important to determine at what transfer timing the wafers to be processed are transferred from the cassette container 134A or 134B. Therefore, a substrate transfer method according to the present embodiment including processing for obtaining such transfer timing will be described below.

(Substrate processing method for substrate processing equipment)
The substrate transfer method according to the present embodiment is characterized in that the wafer is transferred from each cassette container 134 by the transfer unit side transfer mechanism 170 based on the wafer transfer timing obtained in advance based on the processing time of each processing chamber. is there. As described above, since the wafer is unloaded from each cassette container 134 at the wafer transfer timing corresponding to the processing time of each processing chamber, continuous processing of wafers is performed in parallel in a plurality of processing chambers having different processing times. Even in this case, since no extra waiting time is generated in each processing chamber due to a difference in processing time, the throughput of the entire substrate processing apparatus can be improved. The processing time in each processing chamber here refers to the time required for processing one wafer (for example, including the processing time). For example, from the time when one wafer is loaded into each processing chamber, This is the time from when the processing of the wafer is completed and unloaded, and the next wafer can be loaded.

The wafer transfer timing is determined by, for example, the wafer transfer number ratio and the wafer transfer interval. Here, the ratio of the number of wafers carried out is the ratio of the number of wafers carried out for each processing chamber carried out from the cassette container 134, and the wafer carrying-out interval means the wafer carrying-out interval for each processing chamber carried out from the cassette container 134. It is. For example, let P1 be the processing chamber with the longest processing time per wafer, let Pk (k = 2, 3,...) Be the other processing chambers, and let T _{P1 be} the processing time per wafer in the processing chamber P1. with the processing time per wafer in another processing chamber Pk and T _Pk, when the wafer to be processed in the processing chamber P1 to the wafer to be processed in another processing chamber Pk and W _Pk with the W _P1, the wafer out ratio is out ratio of the wafer _{W P1} and the wafer _{W Pk} which is unloaded from the cassette container 134 according to the processing time _{T P1, T Pk} of each of the processing chambers P1, Pk. The wafer unloading interval is the unloading interval of the wafers W _P1 and _WPk that are unloaded from the cassette container 134 at the wafer unloading number ratio.

When the number of processing chambers provided in the substrate processing apparatus is three or more, the wafer transfer timing is obtained for each of the other processing chambers Pk in relation to the processing chamber P1 having the longest wafer processing time. If specifically a substrate processing apparatus including, for example, three process chambers P1, P2, P3, obtains the conveyance timing of the wafer W _P1 and the wafer W _P2 in relation to the processing chamber P1 and the processing chamber P2. The transport timing of the wafer _{W P3} is determined in relation to the processing chamber P1 and the processing chamber P3. As described above, the wafer transfer timing is obtained in the relationship between the processing chamber P1 having the longest wafer processing time and the other processing chamber Pk. The processing is performed in each processing chamber based on the longest processing time _TP1. This is because it is easy to obtain the optimum transfer timing of the wafer.

Next, how to determine the wafer transfer timing will be described. The wafer transfer timing can be obtained as follows according to the processing times T _P1 and T _Pk of the processing chambers P1 and Pk. Here, for example, a substrate processing apparatus 100 having two processing chambers as shown in FIG. 1 will be described as an example. Of the processing chambers 140A and 140B of the substrate processing apparatus 100, the processing chamber with the longest processing time is P1, and the other processing chamber is P2.

For example the ratio of the processing time of the processing chambers _{P1, P2 T P1, T P2} (T P1: T P2) is 2: if 1, the processing time for one wafer _{W P1} in the processing chamber P1 _{T P1} In the processing chamber P2, two wafers _WP2 can be processed. Therefore, the wafer carry-out number ratio is set to 1: 2. In this case, since the next wafer is processed after the processing in the processing chambers P1 and P2 is completed, the wafer unloading interval of the wafers W _P1 and W _P2 is set to each processing time T _P1 and T _P2 . .

As a result, the wafers W _P1 and W _P2 processed in the processing chambers P1 and P2 are unloaded one by one at unloading intervals for the respective processing times T _P1 and T _P2 . At this time, since the processing time _TP1 is twice the processing time _TP2 , every time one wafer _WP1 processed in the processing chamber P1 is unloaded, the number of wafers _WP2 processed in the processing chamber _P2 is two. It is carried out.

As described above, in this embodiment, since the wafer transfer timing from the cassette container 134 is obtained according to the process times T _P1 and T _Pk of the process chambers P1 and _Pk , according to such wafer transfer timing, the process time The wafer W _P1 processed in the processing chamber P1 having a long processing time is unloaded from the cassette container 134 at a long interval corresponding to the processing time T _P1 and the wafer W _Pk processed in the processing chamber Pk having a short processing time is processed by the processing time T _Pk. It is possible to carry out the cassette container 134 at short intervals according to the above. Thus, the wafer _{W P1} is common transfer chamber 150 as in the conventional process time is long processing chamber P1, load-lock chambers 160M, 160 N, for a long time waiting in such orienter 137, the wafer processing time is short processing chamber Pk since the W _Pk can be eliminated a situation which can not be unloaded from the cassette container 134 to improve the operating rate of the respective processing chambers P1, Pk, it is possible to improve the throughput of the entire substrate processing apparatus.

Incidentally, since there is only one transfer unit side transfer mechanism 170, for example, in the substrate processing apparatus 100 having two process chambers as shown in FIG. 1, for example, the first wafer to be processed in the process chamber P1 as shown in FIG. from the start timing _{t 11} of W _P1 is unloaded, the first wafer _{W P2} until the start timing _{t 12} which is carried out, the operation cycles shifted time _{T S2} of the transfer unit-side transfer mechanism 170 to be processed in another processing chamber P2 is Arise. The operation cycle of the transport unit side transport mechanism 170 indicates, for example, the following series of operations. First, the wafer is transferred from the cassette container 134 by the transfer unit side transfer mechanism 170 and transferred to the orienter 137. Next, the orienter 137 is accessed to replace the wafer with a positioned wafer. Next, the positioned wafer is transferred toward the load lock chamber 160N or 160M, and the positioned wafer is replaced with a processed wafer in the load lock chamber 160N or 160M. Finally, the processed wafer is returned to the cassette container 134. In the specific example shown in FIG. 5, the time required for such a series of operations, that is, the start timing deviation time T _{S2 is set} to 20 sec, for example.

Moreover, the carry-out interval wafer W _P1 is unloaded one by one to be processed in the processing chamber P1, since the wafer W _P2 is equal to the carry-out interval that is unloaded by two to be processed in the processing chamber P2, these out Each interval is always shifted by the start timing shift time T _Sk described above. Therefore, the timing at which the wafer W _P1 is unloaded from the cassette container 134, and when the wafer W _P2 is unloaded from the cassette container 134 do not become simultaneously. Therefore, if the wafers W _P1 and W _Pk are unloaded from the cassette container 134 at such a wafer transfer timing, there is no waiting time due to wafer unloading in each of the processing chambers P1 and P2.

Thus, when the processing time T _P1 of the processing chamber _P1 is exactly an integral multiple (for example, n times) of the processing time T _Pk of the processing chamber Pk, one wafer _WP1 to be processed in the processing chamber P1 is obtained. and out interval is carried out by, since the wafer W _Pk processed in the processing chamber Pk is equal to the carry-out interval that is unloaded by the number of the integer multiples (e.g. n sheets), deviation time of unloading interval start timing mentioned above It will always shift by the amount of T _Sk . For this reason, there is no waiting time due to wafer unloading in each of the processing chambers P1 and Pk. Incidentally, as this wafer transfer timing when the wafer _{W P1, W} respectively wafer unloading interval for _Pk respective processing chambers P1, Pk processing time _{T P1, T Pk} Gototo processed in the process chambers P1, Pk All you need is enough. This is because the ratio of the number of unloaded wafers for the wafers W _P1 and W _Pk is naturally determined.

However, when actually wafer processing, the processing time T _P1 of the processing chamber P1 is just not be an integral multiple of the processing time T _Pk processing chamber Pk often. In such a case, even if even if the wafer _{W P1, W Pk} shift start timing as mentioned above time unloading, since each discharge interval of the wafer _{W P1, W Pk} is different, the wafer _{W P1} cassette container There is a case where the timing at which the wafer _WPk is unloaded from the cassette 134 and the timing at which the wafer _WPk is unloaded from the cassette container 134 occur simultaneously. In this case, since wafers waiting to be carried out are generated in one of the wafers W _P1 and W _{P k} , as a result, a waiting time is generated in one of the processing chambers P 1 and P k , and the substrate is transferred by that amount. The throughput of the entire apparatus is reduced.

Therefore, in the present invention, a cassette container 134 wafers _{W P1, W P k} such that the wafer unloading waiting does not occur when it is unloaded from the cassette container 134 wafers _{W P1, W Pk} one by one or by a plurality The transport timing is obtained so that the transport is carried out at the same reference carry-out interval Tx.

Specifically, first, based on the processing times T _P1 and T _Pk of the processing chambers P1 and Pk, the reference unloading interval Tx serving as a reference for unloading the wafers W _P1 and _WPk from the cassette container 134 is determined. To do. Then, the maximum numbers m and n of wafers W _P1 and W _{Pk that} can be processed within the reference carry-out interval Tx are obtained.

In this case, for example, as wafer transfer timing, the wafer transfer number ratio of the wafers W _P1 and W _Pk is m: n, and the wafer transfer interval is the processing times T _P1 and T _Pk , respectively. Thus, m wafers W _P1 to be processed in the processing chamber P1 are unloaded one by one at the reference unloading interval Tx from the cassette container 134 every processing time T _{P1 and} are processed in the processing chamber Pk. As for the wafers _WPk , n wafers are carried out from the cassette container 134 at the same reference carry-out interval Tx as described above, one by one for each processing time _TPk . In this case, the wafers W _P1 and W _Pk are unloaded continuously if the timing of unloading m and n wafers in each section of the reference unloading interval Tx is every processing time T _P1 and _TPk , respectively. Alternatively, it may not be carried out continuously.

As described above, when the wafers W _P1 and W _Pk are processed in parallel in the processing chambers P1 and Pk, the wafer transfer timing from the cassette container 134 is set to the processing times T _P1 and T _Pk of the processing chambers P1 and Pk. Can be matched. Moreover, according to the wafer transfer timing as described above, for example, into the processing chamber P1 in time to perform the processing of the wafer W _P1, the processing of only the wafer W _Pk number up that can be processed by another processing chamber Pk Since it can be performed, the processing waiting time of each processing chamber P1, Pk can be reduced, and the operating rate of each processing chamber can be improved. Thereby, the throughput of the entire substrate processing apparatus can be improved.

Furthermore, by unloading from the cassette container 134 at the wafer _{W P1, W Pk} one by one or a plurality every timing of same reference out interval Tx (cycle), the wafer _{W P1, W Pk} is unloaded from the cassette container 134 Since each timing is always shifted by the above-described start timing shift time T _Sk , the timing at which the wafers W _P1 and W _Pk are unloaded from the cassette container 134 does not coincide. Thereby, it is possible to prevent the waiting time due to the wafer unloading waiting in each of the processing chambers P1 and P2.

Also, the above case, each number from the reference discharge interval Tx wafer _{W P1, W Pk} m, remainder obtained by subtracting the processing time of the n time is a waiting time of each processing chamber Pk, P1 in the reference discharge interval Tx . Therefore, it is preferable to determine the reference carry-out interval Tx so that this waiting time is minimized. For example, if the processing time _{T P1} of the processing chamber P1 and m multiplied by _{T P1} · m based unloaded interval Tx, it is possible to eliminate the waiting time of the processing chamber P1, also the processing time _{T Pk} × n or processing time _{T Pk} If T _Pk · (n + 1) obtained by multiplying (n + 1) by the reference carry-out interval Tx, the waiting time of the processing chamber Pk can be eliminated.

In this way, according to the combination of the processing times T _P1 and T _P2 of the processing chambers P1 and P2, the reference carrying-out interval Tx is determined so that the waiting time of either of the processing chambers P1 and P2 is the shortest, and the reference carrying-out is performed. Based on the interval Tx, the transfer timing of the wafer from the cassette container 134 (for example, the wafer transfer number ratio and the wafer transfer interval) is obtained. Thereby, since the waiting time of each processing chamber P1, P2 can be optimized, the throughput of the whole substrate transfer apparatus can be further improved. Incidentally, how to obtain such a wafer transfer timing, the processing time T _P1 of the processing chamber P1 can be applied regardless of whether exactly an integer multiple of the processing time T _Pk processing chamber Pk.

When the number of processing chambers provided in the substrate processing apparatus is three or more, the wafer transfer timing is obtained for each of the other processing chambers Pk in relation to the processing chamber P1 having the longest wafer processing time. However, in this case, in order to unify the reference carry-out interval Tx, for example, when the reference carry-out interval Tx is first determined when obtaining the wafer transfer timing for the other process chamber P2, the other process chambers P3, P4,. , Pk _end , the previously determined reference carry-out interval Tx is used. The waiting time may be obtained for each of the other processing chambers Pk in relation to the processing chamber P1, and the reference carry-out interval Tx may be obtained so that this waiting time is minimized.

(Specific example of processing for obtaining wafer transfer timing)
Next, a specific example of the process for obtaining the wafer conveyance timing performed based on the above-described method for obtaining the wafer conveyance timing will be described with reference to the drawings. FIG. 2 is a flowchart showing processing for obtaining the wafer transfer timing according to the present embodiment. Note that the processing for obtaining the wafer transfer timing is constituted by, for example, a predetermined program, and is executed by the control unit 190 based on this program. For example, the program is stored in advance in a storage medium such as a memory of the control unit 190 or a hard disk device of an externally connected host device, and the control unit 190 reads and executes these programs from the recording medium.

As shown in FIG. 2, the processing for obtaining the wafer transfer timing is as follows. First, in step S110, the wafer processing times in the respective processing chambers are compared, and the processing chamber having the longest processing time per wafer is defined as P1. Let other processing chambers be Pk (k = 2, 3,..., K _end ). Here, k _end is the number of processing chambers provided in the substrate processing apparatus 100. For example, since the substrate processing apparatus 100 shown in FIG. 1 includes two processing chambers 140A and 140B, if the processing chamber 140A has the longest processing time per wafer, the processing chamber 140A is the processing chamber P1. The processing chamber 140B is referred to as a processing chamber P2.

Subsequently, the processing time of the wafer per one processing chamber P1 at step S120 and T _P1, the processing time of the wafer per one in another processing chamber Pk and T _Pk. Note that the order of the processing chamber P1 and the other processing chambers Pk (k = 2, 3,..., K _end ) is preferably the order of the processing chambers with longer processing times. For example, in a substrate processing apparatus having three processing chambers, the processing chamber P1, the processing chamber P2, and the processing chamber P3 are set in order of increasing processing time per wafer.

Next, in steps S130 and S140, processing for obtaining the wafer transfer timing is performed. That is, a process for obtaining the wafer carry-out number ratio is performed in step S130, and a process for obtaining the wafer carry-out interval is performed in step S140. Here, a specific example of the process for obtaining the wafer carry-out number ratio in step S130 is shown in FIG. 3, and a specific example of the process for obtaining the wafer carry-out interval in step S140 is shown in FIG. 3 and 4, when the maximum number m of wafers W _{P1 that} can be processed at the reference carry-out interval Tx is 1, that is, the processing time T _P1 of the processing chamber P1 having the longest processing time per wafer is determined. This is a process for determining a reference carry-out interval Tx as a reference. FIG. 5 is a diagram showing a processing schedule of the wafers W _P1 and W _P2 processed in the processing chambers P1 and P2 when the wafer is unloaded from the cassette container 134 at the wafer transfer timing obtained from FIGS. It is. FIG. 5 shows the processing schedules of the wafers W _P1 and W _P2 processed in the two processing chambers P1 and P2 as bar graphs with time on the horizontal axis.

(Specific example of processing for obtaining the wafer unloading number ratio)
Here, a specific example of the processing for obtaining the wafer carry-out number ratio will be described with reference to FIG. As shown in FIG. 3, if the processing time T _P1 of processing time per one wafer longest processing chamber P1 when a reference out interval Tx in step S210, the interval in the reference discharge interval Tx (wherein in the processing time _{T P1)} to determine the maximum number n of processable wafer _{W Pk} in another processing chamber Pk. In the processing time T _P1 of the processing chamber P1, by unloading the only wafer W _Pk processable number in another processing chamber Pk from the cassette container, in order to reduce as far as possible the waiting time of the processing chamber Pk.

Specifically, for example, the number n of wafers _{WPk is obtained} so that both the following mathematical formulas (1-1) and (1-2) are satisfied. In the following formulas (1-1) and (1-2), T _P1 is the processing time of one wafer W _P1 in the processing chamber P1, and T _Pk is one wafer W in another processing chamber Pk. The processing time of _Pk , n is an integer that satisfies n ≧ 1, and k is an integer that satisfies k ≧ 2 as described above. In addition, the dot “•” in the following mathematical formulas (1-1), (1-2), etc. represents a product symbol (the same applies hereinafter).

T _P1 ≧ T _Pk · n (1-1)

T _P1 <T _Pk · (n + 1) (1-2)

Of the following step S220~S280 and processing time _{T P1} of the processing chamber P1 processing chamber Pk processing time _{T Pk · (n + 1)} , the reference direction which waiting time is short (Write reference out interval Tx becomes short) The unloading interval Tx is determined, and the wafer unloading number ratio of the wafers W _P1 and W _Pk processed in the processing chambers P1 and Pk is obtained. Thus, by adopting the shorter waiting time of the processing chambers P1 and Pk as the reference carry-out interval Tx, the waiting time of processing can be shortened in all of the processing chambers P1 and Pk. Thereby, the waiting time can be optimized in the entire substrate processing apparatus.

Specifically, obtains a waiting time _{T Wk} other processing chamber Pk in the case where the tentatively processing time _{T P1} criteria out interval Tx processing chamber P1 at step S220 by the following equation (1-3), step S230 If determined by the processing time of the processing chamber _{Pk T Pk · (n + 1} ) following equation (1-4) the waiting time _{T W1} of the processing chamber P1 in the case of a reference out interval Tx of at.

T _Wk = T _P1 −T _Pk · n (1-3)

T _W1 = T _Pk · (n + 1) −T _P1 (1-4)

Next, in step S240, the waiting times T _W1 and T _Wk are compared to determine which waiting time is shorter. Specifically, for example, it is determined whether or not the waiting time T _Wk is equal to or less than the waiting time T _W1 (T _Wk ≦ T _W1 ). If it is determined in step S240 that T _Wk ≦ T _W1, that is, if it is determined that the waiting time T _Wk is shorter (or the waiting times T _W1 and T _Wk are both equal), each step S250 The reference unloading interval Tx of the wafers W _P1 and W _Pk is determined as the processing time T _P1 of the processing chamber P1 as shown in the following formula (1-5), and the number of wafer unloading of each of the wafers W _P1 and W _Pk is determined in step S260 The ratio (W _P1 : W _Pk ) is 1: n.

Tx = T _P1 = T _Pk · n + T _Wk (1-5)

According to the reference carry-out interval Tx (= T _P1 = T _Pk · n + T _Wk ) obtained in this way, one wafer W _P1 to be processed in the processing chamber _P1 is carried out for each section and waits in the processing chamber P1. While the time becomes zero, n wafers _WPk to be processed in the processing chamber Pk are unloaded, and the waiting time of the processing chamber Pk becomes _TWk .

On the other hand, if it is determined in step S240 that T _Wk ≦ T _W1 is not satisfied, that is, if it is determined that the waiting time T _W1 is shorter, the reference unloading of each wafer W _P1 and W _Pk is performed in step S270. determining an interval Tx processing time _T Pk · (n + 1) of the processing chamber Pk as shown in the following equation (1-6), the wafer unloading ratio of each wafer _{W P1, W Pk} in step S280 _{(W P1:} Let W _Pk ) be 1: n + 1.

Tx = T _P1 + T _W1 = T _Pk · (n + 1) (1-6)

Thus obtained reference out interval _{Tx (= T P1 + T W1} = T Pk · (n + 1)) in accordance, in each the interval, the wafer _{W P1} to be processed in the processing chamber P1 is unloaded one, the processing chamber P1 Is waiting time T _W1, and n + 1 wafers _WPk to be processed in the processing chamber _Pk are unloaded, and the waiting time of the processing chamber Pk becomes zero. Note that the reference unloading interval Tx and the wafer unloading number ratio obtained by the processing shown in FIG. 3 are stored in the memory of the control unit 190 or the like.

(Specific example of processing for obtaining wafer unloading interval)
Next, a specific example of processing for obtaining the wafer carry-out interval will be described with reference to FIG. Here, the wafers W _P1 , W when the wafers are actually carried out from the cassette container 134 based on the wafer carry-out number ratio based on the reference carry-out interval Tx determined by the processing for obtaining the wafer carry-out number ratio shown in FIG. _{The Pk} wafer unloading interval is obtained.

Specifically, first, as shown in FIG. 4, the wafer carry-out number ratio (W _P1 : W _Pk ) obtained by the processing shown in FIG. 3 in step S310 is taken out from the memory of the control unit 190, and the wafer carry-out number ratio is obtained. It is determined whether (W _P1 : W _Pk ) is 1: n or 1: n + 1.

Wafer out ratio in step S310 _{(W P1:} W _Pk) is 1: If it is determined that n, the wafer unloading interval for the wafer _{W P1} to be processed in the processing chamber P1 at step S320, the reference out An interval for carrying out one sheet at an interval Tx. Thereby, the wafers W _P1 are unloaded from the cassette container 134, for example, one by one at the reference unloading interval Tx, that is, one for each processing time _TP1 . In this case, the reference discharge interval Tx becomes the processing time T _P1 of the processing chamber P1, for example, as shown in the upper of the processing schedule of FIG. 5 (a), the wafer W _P1 in the processing chamber P1 in latency 0 Processed continuously.

Next, in step S330, the wafer unloading interval for the wafer _WPk processed in the processing chamber Pk is set to an interval for unloading the n wafers at the reference unloading interval Tx one by one for each processing time _TPk . Thus, for example, the wafer _WPk is unloaded from the cassette container 134 continuously for each section of the reference unloading interval Tx, and waits for unloading for a waiting time _TWk . That is, after n sheets are continuously unloaded from the cassette container 134, after waiting for the waiting time _{TWk, the} next n sheets are unloaded from the cassette container 134 continuously. In this case, since the reference carry-out interval Tx is the processing time T _Pk · n + T _Wk of the processing chamber Pk, for example, as shown in the lower processing schedule of FIG. wafer W _Pk is processed successively by n copies in waiting time T _Wk for each section of the. FIG. 5A is a specific example in the case of k = 2 and n = 3.

In contrast, the wafer unloading ratio at step S310 _{(W P1:} W _Pk) is 1: If it is determined that the n + 1, the wafer unloading of the wafer _{W P1} to be processed in the processing chamber P1 at step S340 The interval is set as an interval for carrying out one sheet at a time in the reference carrying-out interval Tx. Thereby, for example, the wafer _WP1 is unloaded from the cassette container 134 one by one for each section of the reference unloading interval Tx and waits for unloading for the waiting time _TW1 . That is, after one sheet is unloaded from the cassette container 134, after waiting for the waiting time _TW 1, the next sheet is unloaded from the cassette container 134. In this case, since the reference carry-out interval Tx is the processing time T _P1 + T _W1 of the processing chamber P1, for example, as shown in the upper processing schedule of FIG. One wafer _WP1 is processed at a waiting time _TW1 for each section.

Next, in step S350, the wafer unloading interval for the wafer _WPk processed in the processing chamber Pk is set as an interval for unloading n + 1 sheets each for the reference unloading interval Tx for each processing time _TPk . As a result, the wafers _WPk are unloaded from the cassette container 134 continuously, for example, n + 1 sheets for each section of the reference unloading interval Tx. In this case, since the reference carry-out interval Tx is the processing time T _Pk · (n + 1) of the processing chamber Pk, for example, as shown in the lower processing schedule of FIG. For each section, n + 1 wafers _WPk are successively processed with a waiting time of zero. FIG. 5B is a specific example when k = 2 and n = 2.

Thus, the wafer carry-out number ratio and the wafer carry-out interval obtained by the processing shown in FIGS. 3 and 4 are stored in the memory or the like by the control unit 190. When the wafer is actually processed, the control unit 190 acquires the wafer carry-out number ratio and the wafer carry-out interval obtained in FIG. 3 and FIG. 4 from the memory, and the wafer carry-out number ratio and the wafer carry-out interval. Based on the above, the transfer unit side transfer mechanism 170 is controlled to carry out the wafers W _P1 and W _Pk from the cassette container 134, respectively.

Thus, for example, a wafer W _P1 processing time is processed in long processing chamber P1 is unloaded from the cassette container 134 at long intervals corresponding to the processing time T _P1, the wafer processing time is processed in a short processing chamber W _Pk since W _Pk is unloaded from the wafer at short intervals in accordance with the processing time _{T Pk,} the wafer _{W P1} is common transfer chamber 150 as in the conventional process time is long processing chamber P1, load-lock chambers 160M, 160 N, orienter 137 for a long time waiting such a situation where it becomes impossible to unload the wafer W _Pk processing time shorter processing chamber T _Pk from the cassette container 134 does not occur. Therefore, it is possible to improve the operation rate in each of the processing chambers P1 and Pk and to improve the throughput of the entire substrate processing apparatus more than before.

Further, since the wafers W _P1 and W _Pk are each unloaded from the cassette container 134 at the same timing (cycle) of the reference unloading interval Tx, each section of the reference unloading interval Tx in the wafers W _P1 and _WPk is the first. The wafers W _P1 and W _Pk to be processed are shifted by the start timing shift time T _Sk generated when the wafers W _P1 and W _Pk are unloaded. For this reason, the timing at which the wafers W _P1 and W _Pk are unloaded is not simultaneous. Note that the processing shown in FIGS. 3 and 4 is performed not only when the processing time T _P1 of the processing chamber _P1 is not an integral multiple of the processing time T _Pk of the processing chamber Pk, but also in the processing schedule of FIG. As shown, the present invention is applicable even when the processing time T _P1 of the processing chamber _P1 is exactly an integral multiple of the processing time T _Pk of the processing chamber Pk.

(When applied to a substrate processing apparatus having two processing chambers)
Next, in the substrate processing apparatus having two processing chambers as shown in FIG. 1, specific numerical values will be described with reference to FIG. Will be described. In FIG. 5, the case where the processing time of one wafer in each of the processing chambers 140A and 140B is 200 sec and 60 sec is shown in FIG. 5A, the case of 200 sec and 70 sec is shown in FIG. The case of 50 sec is shown in FIG. In any of these cases, the processing chamber 140A is the processing chamber with the longest processing time. Therefore, according to steps S110 and S120 in FIG. 2, the processing chamber 140A is the processing chamber P1, and the processing time is T _P1 . The processing chamber 140B is the processing chamber P2, and the processing time is _TP2 .

  When the transfer timing is obtained in step S130 (for example, the process shown in FIG. 3) and step S140 (for example, the process shown in FIG. 4) in FIG. 2, it depends on the processing time of each processing chamber. The description will be divided into a), (b), and (c).

First, a specific example of FIG. 5A will be described. This embodiment is better to reference out interval Tx and processing time T _P1 of the processing chamber P1 is when the waiting time of the processing chamber is shortened. The case shown in FIG. 5 (a), the processing time _{T P1} of the processing chamber P1 is 200 sec, since the processing time _{T P2} of the processing chamber P2 is a 60 sec, in step S210 shown in FIG. 3, formula as k = 2 When applied to (1-1) and (1-2), n = 3 satisfies these mathematical expressions.

Subsequently, in Steps S220 and S230, when k = 2 and numerical values are applied to the equations (1-3) and (1-4), the waiting time T _W2 of the processing chamber P2 = 200−60 × 3 = 20 sec, The waiting time T _W1 of the processing chamber P1 = 60 × 4-200 = 40 sec. Waiting time _T W1 latency _T W2 (= 20sec) towards the processing chamber P1 processing chamber P2 (= 40 sec) for less than, in step S240, S250, S260, reference unloaded spacing wafer _{W P1, W P2} Tx is the processing of the processing chamber P1 time _T P1 (= 200 sec), and the wafer unloading ratio of the processing chamber wafer _{W P1} to be processed at P1, _{W P2} to be processed in the processing chamber _{P2 (W P1:} W P2) is 1 : 3.

Then, in step S310, S320, S330 shown in FIG. 4, the wafer unloading interval for the wafer _{W P1} to be processed in the processing chamber P1 becomes the interval for unloading one by one to the reference discharge interval Tx (= 200 sec), the processing chamber The wafer unloading interval for the wafer WP2 to be processed in _P2 is an interval for unloading three wafers at the reference unloading interval Tx (= 200 sec) one by one at the processing time T _P2 (= 60 sec).

When the wafers W _P1 and W _P2 are unloaded from the cassette container 134 at such a wafer transfer timing, the processing schedule of the processing chambers P1 and P2 is as shown in FIG. In this case, the wafer W _P1 is continuously processed in the processing chamber P1 with a waiting time of zero. On the other hand, the wafer _{W P2} is continuously processed one by three in the processing chamber P2 in the reference discharge interval Tx (= 200 sec) waiting time for each _T W2 (= 20sec).

Next, a specific example of FIG. 5B will be described. This specific example is a case where the waiting time of the processing chamber becomes shorter when the reference carry-out interval Tx is set to the processing time _TP2 · (n + 1) of the processing chamber P2. In the case shown in FIG. 5B, the processing time TP1 of the processing chamber _P1 is 200 sec and the processing time TP2 of the processing chamber _P2 is 70 sec. Therefore, in step S210 shown in FIG. When applied to (1-1) and (1-2), n = 2 satisfies these mathematical expressions.

Subsequently, according to step S220 and step S230, when k = 2 and numerical values are applied to equations (1-3) and (1-4), the waiting time T _W2 of the processing chamber P2 = 200−70 × 2 = The waiting time T _W1 = 70 × 3−200 = 10 sec for the processing chamber P1 is 60 sec. Since the waiting time T _W1 (= 10 sec) of the processing chamber P1 is less than the waiting time T _W2 (= 60 sec) of the processing chamber P2, the reference unloading interval of the wafers W _P1 and W _P2 is determined in steps S240, S270, and S280. Tx is a processing time of 70 sec × 3 (= 210 sec) in the processing chamber P2, and the wafer unloading ratio (W _P1 : W _P2 ) of the wafers W _P1 and W _P2 is 1: 3.

Then, in step S310, S340, S350 shown in FIG. 4, the wafer unloading interval for the wafer _{W P1} to be processed in the processing chamber P1 becomes the interval for unloading one by one to the reference discharge interval Tx (= 2 1 0sec), wafer unloading interval for the wafer _{W P2} to be processed in the processing chamber P2 is a reference out interval Tx (= 2 1 0sec) in three portions and the processing time _T P2 (= 70 sec) intervals for unloading one by one for each .

When the wafers W _P1 and W _P2 are unloaded from the cassette container 134 at such a wafer transfer timing, the processing schedule of the processing chambers P1 and P2 is as shown in FIG. In this case, the processing chamber P1 in the reference discharge interval Tx (= 2 1 0sec) per latency _T W1 (= 10sec) wafer _{W P1} in is processed sequentially. On the other hand, the wafer _{W P2} is continuously processed one by three in latency 0 for each processing chamber P2 in the reference discharge interval Tx (= 2 1 0sec).

Next, a specific example of FIG. In this specific example, the processing time T _P1 of the processing chamber _P1 is equal to the processing time T _P2 · n of the processing chamber P2. In this case, by setting the processing time T _P2 · n of the processing chamber P2 (or the processing time T _P1 of the processing chamber _P1 ) as the reference carry-out interval Tx, the waiting time of each processing chamber becomes zero. In the case shown in FIG. 5C, since the processing time TP1 of the processing chamber _P1 is 200 sec and the processing time TP2 of the processing chamber _P2 is 50 sec, k = 2 according to step S210 shown in FIG. Are applied to the equations (1-1) and (1-2), n = 4 satisfies these equations.

Subsequently, in Steps S220 and S230, when k = 2 and numerical values are applied to Formulas (1-3) and (1-4), the waiting time T _W2 of the processing chamber P2 = 200−50 × 4 = 0 sec, The waiting time T _W1 of the processing chamber P1 = 50 × 5-200 = 50 sec. Since the waiting time T _{W 2} (= 0 sec) of the processing chamber P 2 is smaller than the waiting time T _{W 1} (= 50 sec) of the processing chamber P 1 , the wafers W _P1 , W _P2 are obtained in steps S240, S270, S280. The reference unloading interval Tx is the processing time T _P2 · n (= 200 sec) of the processing chamber P2, and the wafer unloading number ratio (W _P1 : W _P2 ) of the wafers W _P1 and W _P2 is 1: 4.

Then, in step S310, S340, S350 shown in FIG. 4, the wafer unloading interval for the wafer _{W P1} to be processed in the processing chamber P1 becomes the interval for unloading one by one to the reference discharge interval Tx (= 200 sec), the processing chamber The wafer unloading interval for the wafer WP2 to be processed in _P2 is an interval for unloading four wafers at the reference unloading interval Tx (= 200 sec) one by one at the processing time T _P2 (= 50 sec).

When the wafers W _P1 and W _P2 are unloaded from the cassette container 134 at such a wafer transfer timing, the processing schedule of the processing chambers P1 and P2 is as shown in FIG. In this case, the wafer _{W P1} in latency 0 for each processing chamber P1 in the reference discharge interval Tx (= 200 sec) are processed sequentially. On the other hand, the wafer _{W P2} is successively processed one by four in the processing chamber at P2 reference out interval Tx (= 200 sec) waiting 0 per.

(When applied to a substrate processing apparatus having three or more processing chambers)
Next, a description will be given of a case where the processing for obtaining the transfer timing as shown in FIGS. FIG. 6 is a diagram showing a schematic configuration of a substrate processing apparatus including three or four processing chambers. The substrate processing apparatus 200 shown in FIG. 6 has substantially the same configuration as the substrate processing apparatus 100 shown in FIG. 1, and further has chambers 140C and 140D connected to both sides of the common transfer chamber 150 via gate valves 144C and 144D. It is. Here, for example, when the chamber 140C is configured as a processing chamber for processing wafers and the chamber 140D is configured as an inspection chamber for performing various inspections such as measurement of processing results of processed wafers, three processing chambers are provided. When the chambers 140C and 140D are both configured as processing chambers for processing wafers, the substrate processing apparatus 200 includes four processing chambers. In addition, in the substrate processing apparatus 200 shown in FIG. 6, a cassette stage 132C is further provided on one side of the transfer chamber 130 that forms a long side having a substantially polygonal cross section, and another cassette container 134C can be placed. Yes. For example, the cassette container 134C may store a wafer to be processed in the chamber 140C or the chamber 140D configured as a processing chamber.

  First, the substrate processing apparatus 200 shown in FIG. 6 is configured as a substrate processing apparatus having three processing chambers, and the processing for obtaining the transfer timing shown in FIGS. 2 to 4 is performed with reference to FIG. Explain with numerical values. FIG. 7 shows a wafer processing schedule in each processing chamber to be processed according to the transfer timing obtained from FIGS. FIG. 7 shows the processing schedule of wafers processed in the three processing chambers P1, P2, and P3 by bar graphs with time on the horizontal axis, respectively. FIG. 7 shows the case where the processing time of one wafer in each of the processing chambers 140A, 140B, and 140C is 200 sec, 70 sec, and 50 sec.

In this case, since the processing chamber with the longest processing time is the processing chamber 140A, according to steps S110 and S120 in FIG. 2, the processing chamber 140A is the processing chamber P1, and the processing time is _TP1 , and the processing chamber 140B is the processing chamber. chamber P2, the processing time _{T P2,} and the processing chamber 140C processing chamber P3, the processing time is _{T P3.} Therefore, in this case determines the conveying timing of the wafer W _P1 and the wafer W _P2 in relation to the processing chamber P1 and the processing chamber P2, the conveyance timing of the wafer W _P3 is in relation to the processing chamber P1 and the processing chamber P3 Ask. However, when obtaining the transfer timing of the wafer W _P3 is to unify the standards out interval Tx, using the reference discharge interval Tx determined when determining the transport timing of the wafer W _P1 and the wafer W _P2. Details of how to determine the wafer transfer timing will be described below.

First, a transport timing of the wafer _{W P1} and the wafer _{W P2} in relation to the processing chamber P1 and the processing chamber P2. In this case, since it is the same as the specific example of FIG. 5B, the reference carry-out interval Tx of the wafers W _P1 and W _P2 becomes the processing time 70 sec × 3 (= 210 sec) of the processing chamber P2, and the wafers W _P1 and W _{P The P2} wafer unloading ratio (W _P1 : W _P2 ) is 1: 3. Wafer unloading interval for the wafer _{W P1} becomes the interval for unloading one by one to the reference discharge interval Tx (= 210 sec), the wafer unloading interval for the wafer _{W P2} is a three pieces based out interval Tx (= 210 sec) It becomes an interval for carrying out one sheet every processing time T _P2 (= 70 sec).

Next, the transfer timing of the wafer _WP3 to be processed in the processing chamber P3 is obtained from the relationship between the processing chamber P1 and the processing chamber P3. In this case, since already the reference discharge gap are determined to Tx = 210 sec, obtaining a transport timing of the wafer _{W P3} using the same. Specifically, for example, the standard carry-out interval is fixed to Tx = 210 sec, the processes of steps S210, S220, and S260 shown in FIG. 3 are performed, and steps S310 and S330 shown in FIG. 4 are performed.

That is, in step S210, when k = 3 and applied to equations (1-1) and (1-2), n = 4 satisfies these equations. Subsequently, when k = 3 and numerical values are applied to the equation (1-3) in step S220, the waiting time T _W3 of the processing chamber P3 = 210−50 × 4 = 10 sec is obtained, and processing is performed in the processing chamber P1 in step S260. The wafer unloading number ratio (W _P1 : W _P3 ) of the wafer W _P1 to be processed and the W _P3 to be processed in the processing chamber P3 is 1: 4. Then, in step S310, S330 shown in FIG. 4, the wafer unloading interval for the wafer _{W P3} to be processed in the processing chamber P3 is a reference out interval Tx (= 210sec) processing the four copies of time _T P3 (= 50 sec) It becomes an interval to carry out one sheet at a time.

When the wafers W _P1 , W _P2 , W _P3 are unloaded from the cassette container 134 at such a wafer transfer timing, the processing schedules of the processing chambers P1, P2, P3 are as shown in FIG. In this case, the wafer W _P1 is continuously processed at the waiting time T _W1 (= 10 sec) in the processing chamber P1 at every reference carry-out interval Tx (= 210 sec), and the wafer W P2 is waiting at the waiting time 0 in the processing chamber _P2. There are consecutively processed by three, the wafer _{W P3} is processed successively by four in the processing chamber P3 in waiting time _T W3 (= 10sec).

  Next, a case where the substrate processing apparatus 200 shown in FIG. 6 is configured as a substrate processing apparatus having four processing chambers and the processing for obtaining the transfer timing shown in FIGS. 2 to 4 is performed with reference to FIG. A description will be given with specific numerical values. FIG. 8 shows a wafer processing schedule in each processing chamber to be processed according to the transfer timing obtained from FIGS. FIG. 8 shows the processing schedules of wafers processed in the four processing chambers P1, P2, P3, and P4 as bar graphs with time on the horizontal axis. FIG. 8 shows the case where the processing time of one wafer in each of the processing chambers 140A, 140B, 140C, and 140D is 200 sec, 70 sec, 60 sec, and 50 sec.

In this case, since the processing chamber with the longest processing time is the processing chamber 140A, according to steps S110 and S120 in FIG. 2, the processing chamber 140A is the processing chamber P1, and the processing time is _TP1 , and the processing chamber 140B is the processing chamber. chamber P2, the processing time _{T P2,} and the processing chamber 140C processing chamber P3, the processing time _{T P3,} and the processing chamber 140D processing chamber P4, the processing time is _{T P4.} Therefore, in this case determines the conveying timing of the wafer W _P1 and the wafer W _P2 in relation to the processing chamber P1 and the processing chamber P2, the conveyance timing of the wafer W _P3 is determined in relation to the processing chamber P1 and the processing chamber P3 , transport timing of the wafer _{W P4} is determined in relation to the processing chamber P1 and the processing chamber P4. However, when determining the transfer timings of the wafers W _P3 and W _P4 , the reference transfer interval Tx determined when determining the transfer timings of the wafers W _P1 and W _P2 is used in order to unify the reference transfer intervals Tx. Details of how to determine the wafer transfer timing will be described below.

First, a transport timing of the wafer _{W P1} and the wafer _{W P2} in relation to the processing chamber P1 and the processing chamber P2. In this case, since it is the same as the specific example of FIG. 5B, the reference carry-out interval Tx of the wafers W _P1 and W _P2 becomes the processing time 70 sec × 3 (= 210 sec) of the processing chamber P2, and the wafers W _P1 and W _{P The P2} wafer unloading ratio (W _P1 : W _P2 ) is 1: 3. Wafer unloading interval for the wafer _{W P1} becomes the interval for unloading one by one to the reference discharge interval Tx (= 210 sec), the wafer unloading interval for the wafer _{W P2} is a three pieces based out interval Tx (= 210 sec) It becomes an interval for carrying out one sheet every processing time T _P2 (= 70 sec).

Next, the transfer timing of the wafer _WP3 to be processed in the processing chamber P3 is obtained from the relationship between the processing chamber P1 and the processing chamber P3. In this case, since already the reference discharge gap are determined to Tx = 210 sec, obtaining a transport timing of the wafer _{W P3} using the same. Specifically, for example, the standard carry-out interval is fixed to Tx = 210 sec, the processes of steps S210, S220, and S260 shown in FIG. 3 are performed, and steps S310 and S330 shown in FIG. 4 are performed.

That is, in step S210, when k = 3 and applied to equations (1-1) and (1-2), n = 3 satisfies these equations. Subsequently, in step S220, when k = 3 and numerical values are applied to the equation (1-3), the waiting time T _W3 of the processing chamber P3 = 210−60 × 3 = 30 sec is obtained. In step S260, processing is performed in the processing chamber P1. The wafer unloading ratio (W _P1 : W _P3 ) of the wafer W _P1 to be processed and the W _P3 to be processed in the processing chamber P3 is 1: 3. Then, in step S310, S330 shown in FIG. 4, the wafer unloading interval for the wafer _{W P3} to be processed in the processing chamber P3 is a reference out interval Tx (= 210 sec) to three by the processing time _T P3 (= 6 0 sec ) Is the interval to carry out one sheet at a time.

Next, the transfer timing of the wafer _WP4 to be processed in the processing chamber P4 is obtained based on the relationship between the processing chamber P1 and the processing chamber P4. Also in this case, since already the reference discharge gap are determined to Tx = 210 sec, obtaining a transport timing of the wafer W _P4 with this. Specifically, for example, the standard carry-out interval is fixed to Tx = 210 sec, the processes of steps S210, S220, and S260 shown in FIG. 3 are performed, and steps S310 and S330 shown in FIG. 4 are performed.

In other words, when k = 4 is applied to equations (1-1) and (1-2) in step S210, n = 4 satisfies these equations. Subsequently, when k = 4 and numerical values are applied to Equation (1-3) in step S220, the waiting time T _W4 of the processing chamber P4 = 210−50 × 4 = 10 sec is obtained, and processing is performed in the processing chamber P1 in step S260. The wafer unloading number ratio (W _P1 : W _P4 ) between the wafer W _P1 to be processed and the W _P4 processed in the processing chamber P 4 is 1: 4. Then, in step S310, S330 shown in FIG. 4, the wafer unloading interval for the wafer _{W P4} to be processed in the processing chamber P4 is a reference out interval Tx (= 210sec) processing the four copies of time _T P4 (= 50 sec) It becomes an interval to carry out one sheet at a time.

When the wafers W _P1 , W _P2 , W _P3 , and W _P4 are unloaded from the cassette container 134 at such a wafer transfer timing, the processing schedules of the processing chambers P1, P2, P3, and P4 are as shown in FIG. Become. In this case, the wafer W _P1 is continuously processed at the waiting time T _W1 (= 10 sec) in the processing chamber P1 at every reference carry-out interval Tx (= 210 sec), and the wafer W P2 is waiting at the waiting time 0 in the processing chamber _P2. There are processed by three consecutive, in the processing chamber P3 latency _T W3 (= 30sec) wafer _{W P3} is continuously processed one by three, the wafer in the processing chamber P4 waiting time _T W4 (= 10sec) _WP4 is successively processed four by four.

(Other specific example of processing for obtaining wafer transfer timing)
Next, another specific example of the processing for obtaining the wafer transfer timing performed based on the above-described principle of the present invention will be described with reference to the drawings. Since the main routine of the other specific example is the same as that shown in FIG. 2, its detailed description is omitted. 9 shows another specific example of the process for obtaining the wafer carry-out number ratio in step S130 shown in FIG. 2, and FIG. 10 shows another specific example of the process for obtaining the wafer carry-out interval in step S140 shown in FIG. . The processing of FIGS. 9 and 10 is performed when the wafer unloading ratio and the wafer unloading interval are obtained based on the processing time _TP1 · m of the processing chamber P1 having the longest processing time per wafer, that is, at the reference unloading interval Tx. the number of processable wafer W _P1 is a case of a m. Note that m may be 1. The wafer conveyance timing when m = 1 is the same as the result obtained by the processing shown in FIGS.

(Other specific examples of processing for obtaining the wafer unloading number ratio)
First, another specific example of the process for obtaining the wafer carry-out number ratio will be described with reference to FIG. As shown in FIG. 9, if the processing time _TP1 · m of the processing chamber P1 having the longest processing time per wafer is set as the reference unloading interval Tx in step S410, the interval within the reference unloading interval Tx. The maximum number n of wafers W _{Pk that} can be processed in another processing chamber Pk within the processing time T _P1 · m is obtained. This is to reduce the waiting time of the processing chamber Pk as much as possible by unloading the wafer _WPk from the cassette container within the processing time T _P1 · m of the processing chamber P1 by the number of wafers _WPk that can be processed in the other processing chamber Pk. is there.

Specifically, for example, the number n of wafers _{WPk is obtained} so that both the following mathematical formulas (2-1) and (2-2) are satisfied. In the following equation (2-1) and _{(2-2), T P1} is the processing time of the wafer _{W P1} per sheet in the processing chamber _{P1, T Pk} wafer W per sheet in the other processing chamber Pk The processing time of _Pk , n is an integer that satisfies n ≧ 1, m is an integer that satisfies ≧ 1, and k is an integer that satisfies k ≧ 2 as described above.

T _P1 · m ≧ T _Pk · n (2-1)

T _P1 · m <T _Pk · (n + 1) (2-2)

In steps S420 to S490 below, m and n are determined such that the waiting time of each processing chamber is the shortest, and the processing time T _P1 of the processing chamber _P1 and the processing time T _Pk · (n + 1) of the processing chamber Pk are determined. Of these, the shorter waiting time (the shorter the reference unloading interval Tx) is determined as the reference unloading interval Tx, and the wafer unloading ratio of the wafers W _P1 and _WPk processed in the processing chambers P1 and Pk is determined. Ask. Thereby, the processing waiting time can be shortened in all of the processing chambers P1 and Pk. For this reason, the waiting time can be optimized in the entire substrate processing apparatus.

Specifically, in step S420, the waiting time _TWk of another processing chamber Pk when the processing time _TP1 · m of the processing chamber P1 is set as the reference carry-out interval Tx is obtained by the following equation (2-3). the waiting time _{T W1} of the processing chamber P1 in a case where if the processing time of the processing chamber Pk _T Pk · an (n + 1) as a reference out interval Tx in step S430 obtained by the following equation (2-4).

T _Wk = T _P1 · m−T _Pk · n (2-3)

T _W1 = T _Pk · (n + 1) −T _P1 · m (2-4)

Subsequently, in step S440, while further changing the value of m (for example, increasing the value of m by 1), in each case of m, the maximum number n and the waiting time T _Wk , in steps S410, S420, and S430. T _W1 is obtained, and m and n are determined so that one of the waiting times T _Wk and T _W1 is minimized.

Next, in step S450, the waiting times T _W1 and T _Wk in the case of m and n determined in step S440 are compared to determine which waiting time is shorter. Specifically, for example, it is determined whether or not the waiting time T _Wk is equal to or less than the waiting time T _W1 (T _Wk ≦ T _W1 ). When it is determined in step S450 that T _Wk ≦ T _W1, that is, when it is determined that the waiting time T _Wk is shorter (or both waiting times T _W1 and T _Wk are equal), each step S 460 The reference carry-out interval Tx of the wafers W _P1 and W _Pk is determined as the processing time T _P1 · m of the processing chamber P1 as shown in the following formula (2-5), and the wafers W _P1 and W _Pk in step S470 The carry-out number ratio (W _P1 : W _Pk ) is m: n.

Tx = T _P1 · m = T _Pk · n + T _Wk (2-5)

According to the reference carry-out interval Tx (= T _P1 · m = T _Pk · n + T _Wk ) obtained in this way, m wafers W _P1 to be processed in the processing chamber _P1 are carried out for each section, and the processing chamber P1 The waiting time in the processing chamber Pk becomes 0, n wafers _WPk to be processed in the processing chamber Pk are unloaded, and the waiting time in the processing chamber Pk becomes _TWk .

On the other hand, if it is determined in step S450 that T _Wk ≦ T _W1 is not satisfied, that is, if it is determined that the waiting time T _W1 is shorter, the reference unloading of each wafer W _P1 and W _Pk is performed in step S480. The interval Tx is determined to be the processing time T _Pk · (n + 1) of the processing chamber Pk as shown in the following formula (2-6), and the wafer unloading ratio (W _P1 :) of each of the wafers W _P1 and W _Pk in step S490. Let W _Pk ) be m: n + 1.

Tx = T _P1 · m + T _W1 = T _Pk · (n + 1) (2-6)

According to the reference carry-out interval Tx (= T _P1 · m + T _W1 = T _Pk · (n + 1)) obtained in this way, m wafers W _P1 to be processed in the processing chamber _P1 are carried out for each section, and the processing chamber P1 with latency becomes _{T W1} of the wafer _{W Pk} processed in the processing chamber Pk is carried out of one n +, latency of the processing chamber Pk becomes 0. Note that the reference unloading interval Tx and the wafer unloading number ratio obtained by the processing shown in FIG. 3 are stored in the memory of the control unit 190 or the like.

(Other specific example of processing for obtaining wafer unloading interval)
Next, another specific example of the process for obtaining the wafer carry-out interval will be described with reference to FIG. Here, based on the wafer unloading ratio by the reference discharge interval Tx determined by the process of obtaining the wafer unloading ratio shown in FIG. 9, when carried out actually wafers from the cassette container 134, the wafer W _P1, W _{The Pk} wafer unloading interval is obtained.

Specifically, as shown in FIG. 10, first, the wafer carry-out number ratio (W _P1 : W _Pk ) obtained by the process shown in FIG. 9 in step S510 is taken out from the memory of the control unit 190 and the wafer carry-out number ratio. It is determined whether (W _P1 : W _Pk ) is m: n or m: n + 1.

Step S510 in the wafer unloading ratio _{(W P1:} W _Pk) is m: If it is determined that n, the wafer unloading interval for the wafer _{W P1} to be processed in the processing chamber P1 at step S520, the reference out An interval of m sheets at the interval Tx is set as an interval for carrying out one sheet at every processing time _TP1 . As a result, the wafer _WP1 is unloaded from the cassette container 134 continuously, for example, m for each section of the reference unloading interval Tx. In this case, since the reference unloading interval Tx is the processing time _TP1 · m of the processing chamber P1, in the processing chamber P1, m wafers _WP1 are continuously provided for each section of the reference unloading interval Tx at a waiting time of 0 m. It is processed.

Next, in step S530, the wafer unloading interval for the wafer _WPk processed in the processing chamber Pk is set to an interval for unloading the n wafers at the reference unloading interval Tx one by one for each processing time _TPk . Thus, for example, the wafer _WPk is unloaded from the cassette container 134 continuously for each section of the reference unloading interval Tx, and waits for unloading for a waiting time _TWk . That is, after n sheets are continuously unloaded from the cassette container 134, after waiting for the waiting time _{TWk, the} next n sheets are unloaded from the cassette container 134 continuously. In this case, since the reference carry-out interval Tx is the processing time T _Pk · n + T _Wk of the processing chamber Pk, n wafers _WPk are provided at the waiting time _TWk for each section of the reference carry-out interval Tx in the processing chamber Pk. Processed continuously.

On the other hand, if it is determined in step S5 10 that the wafer unloading ratio (W _P1 : W _Pk ) is m: n + 1, in step S540, the wafer W _P1 processed in the processing chamber P1 is determined. The wafer unloading interval is defined as an interval for unloading one sheet at a reference unloading interval Tx for each processing time _TP1 . As a result, for example, the wafer _WP1 is unloaded from the cassette container 134 for each section of the reference unloading interval Tx and waits for unloading for the waiting time _TW1 . That is, the next m sheets after waiting only waiting time T _W1 is unloaded consecutively from the cassette container 134 for each processing time T _P1 after the m sheets is unloaded from the cassette container 134 continuously in each processing time T _P1 The In this case, the reference discharge interval Tx is the processing time of the processing chamber P1 _T P1 · m _{+ T W1,} for each section of the processing chamber P1 in the reference discharge interval Tx in waiting time _{T W1} wafer _{W P1} is by m Like It is processed.

Next, in step S550, the wafer unloading interval for the wafer _WPk processed in the processing chamber Pk is set as an interval for unloading the n + 1 wafers for the reference unloading interval Tx one by one for the processing time _TPk . As a result, the wafers _WPk are unloaded from the cassette container 134 continuously, for example, n + 1 sheets for each section of the reference unloading interval Tx. In this case, since the reference unloading interval Tx is the processing time T _Pk · (n + 1) of the processing chamber Pk, in the processing chamber Pk, n + 1 wafers _WPk are continuously provided for each interval of the reference unloading interval Tx with 0 waiting time. Processed.

Thus, the wafer carry-out number ratio and the wafer carry-out interval obtained by the processing shown in FIGS. 9 and 10 are stored in the memory or the like by the control unit 190. When the wafer is actually processed, the controller 190 obtains the wafer carry-out number ratio and the wafer carry-out interval obtained in FIGS. 9 and 10 from a memory or the like, and the wafer carry-out number ratio and the wafer carry-out interval. Based on the above, the transfer unit side transfer mechanism 170 is controlled to carry out the wafers W _P1 and W _Pk from the cassette container 134, respectively.

Thus, for example, a wafer W _P1 processing time is processed in long processing chamber P1 is unloaded from the cassette container 134 at long intervals corresponding to the processing time T _P1, the wafer processing time is processed in a short processing chamber W _Pk since W _Pk is unloaded from the wafer at short intervals in accordance with the processing time _{T Pk,} the wafer _{W P1} is common transfer chamber 150 as in the conventional process time is long processing chamber P1, load-lock chambers 160M, 160 N, orienter 137 for a long time waiting such a situation where it becomes impossible to unload the wafer W _Pk processing time shorter processing chamber T _Pk from the cassette container 134 does not occur. Therefore, it is possible to improve the operation rate in each of the processing chambers P1 and Pk and to improve the throughput of the entire substrate processing apparatus more than before.

Further, since the wafers W _P1 and W _Pk are unloaded from the cassette container 134 at the same timing (cycle) of the reference unloading interval Tx, each section of the reference unloading interval Tx in each of the wafers W _P1 and _WPk is the first. The wafers W _P1 and W _Pk to be processed are shifted by the start timing shift time T _Sk that occurs when the wafers W _P1 and W _Pk are unloaded. For this reason, the timing at which the wafers W _P1 and W _Pk are unloaded is not simultaneous. The processing shown in FIGS. 9 and 10 is performed not only when the processing time T _P1 of the processing chamber _P1 is not an integral multiple of the processing time T _Pk of the processing chamber Pk, but also when it is an integral multiple. Applicable.

  Next, in the case where the substrate processing apparatus 200 shown in FIG. 6 is configured as a substrate processing apparatus having four processing chambers, the case where the processing for determining the transfer timing shown in FIGS. Explain with numerical values. FIG. 11 shows a wafer processing schedule in each processing chamber to be processed according to the transfer timing obtained from FIG. 2, FIG. 9, and FIG. FIG. 11 shows the processing schedule of wafers processed in the four processing chambers P1, P2, P3, and P4 as bar graphs with time on the horizontal axis. FIG. 11 shows the case where the processing time of one wafer in each of the processing chambers 140A, 140B, 140C, and 140D is 100 sec, 70 sec, 60 sec, and 50 sec.

In this case, since the processing chamber with the longest processing time is the processing chamber 140A, according to steps S110 and S120 in FIG. 2, the processing chamber 140A is the processing chamber P1, and the processing time is _TP1 , and the processing chamber 140B is the processing chamber. chamber P2, the processing time _{T P2,} and the processing chamber 140C processing chamber P3, the processing time _{T P3,} and the processing chamber 140D processing chamber P4, the processing time is _{T P4.} Therefore, in this case determines the conveying timing of the wafer W _P1 and the wafer W _P2 in relation to the processing chamber P1 and the processing chamber P2, the conveyance timing of the wafer W _P3 is determined in relation to the processing chamber P1 and the processing chamber P3 , transport timing of the wafer _{W P4} is determined in relation to the processing chamber P1 and the processing chamber P4. However, when determining the transfer timings of the wafers W _P3 and W _P4 , the reference transfer interval Tx determined when determining the transfer timings of the wafers W _P1 and W _P2 is used in order to unify the reference transfer intervals Tx. Details of how to determine the wafer transfer timing will be described below.

First, a transport timing of the wafer _{W P1} and the wafer _{W P2} in relation to the processing chamber P1 and the processing chamber P2. That is, when m and n that minimize the waiting times T _Wk and T _W1 are obtained in steps S410 to S440 shown in FIG. 9, m = 2 and n = 3. Subsequently, at step S450~ step S470, the wafer _{W P1, W} process time 70 sec × 3 criteria out interval Tx processing chamber P2 in _P2 (= 210 sec), and the wafer unloading ratio of wafer _{W P1, W P2} (W _P1 : W _P2 ) is 2: 3. Wafer unloading interval for the wafer _{W P1} is a reference out interval Tx (= 210sec) one by two processing time _T P1 (= 100sec) becomes the interval for unloading one by one for each wafer unloading interval for the wafer _{W P2} is , The interval for unloading 3 sheets each at the reference unloading interval Tx (= 2 10 sec) for each processing time T _P2 (= 70 sec).

Next, the transfer timing of the wafer _WP3 to be processed in the processing chamber P3 is obtained from the relationship between the processing chamber P1 and the processing chamber P3. In this case, since already the reference discharge gap are determined to Tx = 210 sec, obtaining a transport timing of the wafer _{W P3} using the same. Specifically, it is the same as the case shown in FIG. Therefore, the processing chamber wafer _{W P1} to be processed at P1, the wafer unloading ratio of _{W P3} being processed in the processing chamber _{P3 (W P1:} W P3) is 1: 3, and the wafer unloading interval for the wafer _{W P3} is This is the interval at which three sheets are taken out at the reference carry-out interval Tx (= 210 sec) one by one every processing time T _P3 (= 60 sec).

Next, the transfer timing of the wafer _WP4 to be processed in the processing chamber P4 is obtained based on the relationship between the processing chamber P1 and the processing chamber P4. In this case, since already the reference discharge gap are determined to Tx = 210 sec, obtaining a transport timing of the wafer W _P4 with this. Specifically, it is the same as the case shown in FIG. Accordingly, the wafer unloading ratio (W _P1 : W _P4 ) between the wafer W _P1 processed in the processing chamber P1 and the W _P4 processed in the processing chamber P4 is 1: 4, and the wafer unloading interval for the wafer W _P4 is This is an interval for carrying out four sheets at a reference carry-out interval Tx (= 210 sec) one by one every processing time T _P4 (= 50 sec).

When the wafers W _P1 , W _P2 , W _P3 , and W _P4 are unloaded from the cassette container 134 at such wafer transfer timing, the processing schedules of the processing chambers P1, P2, P3, and P4 are as shown in FIG. Become. In this case, each reference out interval Tx (= 210 sec), each wafer _{W P1} is two in the processing chamber P1 waiting time _T W1 (= 10sec) are continuously processed, the processing chamber P2 in latency 0 wafer _{W P2} is continuously processed one by three, in the processing chamber P3 latency _T W3 (= 30sec) wafer _{W P3} is continuously processed one by three, the processing chamber P4 in waiting time _T W4 (= 10 sec ), Four wafers _WP4 are successively processed.

As described in detail above, according to the present embodiment, it is obtained in advance for each processing chamber P1, Pk based on the processing times T _P1 , T _Pk of the wafers W _P1 , W _{Pk in} the processing chambers P1, Pk. Since the wafers W _P1 and W _Pk are unloaded from the cassette container 134 in accordance with the wafer transfer timing, the wafer transfer timing from the cassette container 134 is set in each processing chamber P1 and Pk when the wafers are processed in parallel. It can be optimized according to the processing times T _P1 and T _Pk of the chambers P1 and Pk. For example the wafer W _P1 processing time is processed in long processing chamber P1 is unloaded from the cassette container 134 at long intervals corresponding to the processing time T _P1, the wafer W _Pk processing time is processed in a short processing chamber W _Pk is The wafer can be unloaded from the wafer at short intervals according to the processing time _TPk .

Therefore, the wafer _{W P1} is common transfer chamber 150 as in the conventional process time is long processing chamber P1, load-lock chambers 160M, 160 N, for a long time waiting in such orienter 137, the processing time is shorter processing chamber _{T Pk} The situation in which the wafer _WPk cannot be unloaded from the cassette container 134 can be eliminated. Thereby, the operation rate in each processing chamber P1, Pk can be improved, and the throughput of the whole substrate processing apparatus can be improved.

  Note that the processing for obtaining the wafer transfer timing according to the present embodiment as described above is performed prior to the actual wafer processing. For example, this is performed in a warm-up process when the power of the substrate processing apparatus is turned on. Further, when maintenance such as component replacement or cleaning is performed on the substrate processing apparatus thereafter, the maintenance may be performed after the maintenance.

  In this embodiment, since the wafer transfer timing is determined according to the processing time of each processing chamber, when the wafer transfer timing is determined before actual wafer processing is performed, the predicted value of the processing time of each processing chamber is used. Ask based. However, depending on the processing environment such as particles adhering to the processing chamber, the actual wafer processing time may deviate from the predicted value. In addition, depending on the process, some of the basic process conditions (for example, parameters such as process chamber pressure, temperature, process gas flow ratio, applied voltage to electrodes, etc.) may be changed or new process conditions may be used. It is also possible to add (parameters, etc.). Even in such a case, there is a possibility that the processing time may deviate from the predicted value.

  As described above, when the processing time of each processing chamber becomes different from the predicted value, the wafer transfer timing is obtained again. Thereby, the wafer transfer timing can be obtained according to the actual processing time of each processing chamber, and it is possible to prevent an unexpected waiting time due to a deviation from the actual processing time from occurring in each processing chamber.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  For example, in the above-described embodiment, a so-called cluster tool type substrate processing apparatus in which a plurality of processing chambers are connected around a common transfer chamber has been described as an example. However, for example, a load lock chamber is provided in the processing chamber. The present invention can be applied to various types of substrate processing apparatuses that include a plurality of processing chambers and perform parallel processing, such as a so-called tandem type substrate processing apparatus in which a plurality of processing units are connected in parallel to a transfer unit. is there.

  The present invention is applicable to a substrate processing apparatus for performing a predetermined process on a substrate to be processed and a substrate transfer method of the substrate processing apparatus.

It is a figure which shows the structural example of the substrate processing apparatus concerning embodiment of this invention. 4 is a flowchart showing processing for obtaining wafer transfer timing in the embodiment. FIG. 3 is a flowchart showing a specific example of processing for obtaining a wafer carry-out number ratio in FIG. 2. FIG. 3 is a flowchart showing a specific example of processing for obtaining a wafer carry-out interval in FIG. 2. It is a figure which shows the process schedule of the wafer in two process chambers. It is a figure which shows the other structural example of the substrate processing apparatus concerning embodiment of this invention. It is a figure which shows the process schedule of the wafer in three process chambers. It is a figure which shows the process schedule of the wafer in four process chambers. 6 is a flowchart showing another specific example of the process for obtaining the wafer carry-out number ratio in FIG. 2. 6 is a flowchart showing another specific example of the process for obtaining the wafer carry-out interval in FIG. 2. It is a figure which shows the process schedule of the wafer in four process chambers.

Explanation of symbols

100, 200 Substrate processing apparatus 110 Processing unit 120 Transfer unit 130 Transfer chamber 132 (132A to 132C) Cassette stand 134 (134A to 134C) Cassette container 136 (136A to 136C) Gate valve 137 Orienter 138 Rotation mounting table 139 Optical sensor 140 ( 140A to 140C) Processing chamber 140D Processing chamber or inspection chamber 142 (142A to 142D) Mounting table 144 (144A to 144D) Gate valve 150 Common transfer chamber 160 (160M, 160N) Load lock chamber 170 Transfer unit side transfer mechanism 172 Base 174 Guide rail 176 Linear motor drive mechanism 180 Processing unit side transport mechanism 190 Control unit

Claims (9)

A processing unit having a plurality of processing chambers for performing a predetermined process on a substrate to be processed, a transfer unit connected to the processing unit, and the substrate to be processed provided in the transfer unit and accommodated in a substrate storage container A substrate processing apparatus comprising: a transport unit side transport mechanism that transports the substrate to the processing unit; and a processing unit side transport mechanism that is provided in the processing unit and transports the substrate to be processed transported from the transport unit to the processing chamber. Because
The transfer timing of the substrate to be processed, which is transferred from the substrate storage container to the processing chambers, is carried out for unloading the substrate to be processed for each processing chamber when the substrate to be processed is unloaded from the substrate storage container. calculated based on the number ratio and unloading intervals, a control means for unloading the substrate to be processed from the substrate storage container according to this conveying timing,
The control means determines the reference carry-out interval based on the processing time of the substrate to be processed in each processing chamber with respect to the carry-out number ratio of the substrates to be processed, and then includes the reference transfer interval within each section of the reference transfer interval. Obtained based on the maximum number of substrates to be processed that can be processed in each processing chamber,
With respect to the unloading interval of the substrates to be processed, the number of substrates to be processed at the reference unloading interval is set for each processing chamber, and the number of substrates to be processed in each processing chamber is one for each processing time. A substrate processing apparatus characterized by having an interval for carrying out . The ratio of the number of substrates to be processed is based on the processing time of the substrate to be processed in each processing chamber, and the processing time of the processing chamber having the longest processing time among the processing chambers is defined as the reference unloading interval. 2. The substrate processing apparatus according to claim 1 , wherein the substrate processing apparatus is obtained based on the maximum number of substrates to be processed that can be processed in another processing chamber within the interval of the reference carry-out interval. The reference discharge interval on the basis of the waiting time in each section of the reference discharge spaces at each of the processing chambers, the substrate processing according to claim 1 or 2, wherein the determining so that the waiting time is shortened apparatus. A processing unit having a plurality of processing chambers for performing a predetermined process on a substrate to be processed, a transfer unit connected to the processing unit, and the substrate to be processed provided in the transfer unit and accommodated in a substrate storage container A substrate processing apparatus comprising: a transport unit side transport mechanism that transports the substrate to the processing unit; and a processing unit side transport mechanism that is provided in the processing unit and transports the substrate to be processed transported from the transport unit to the processing chamber. The substrate transport method of
The transfer timing of the substrate to be processed, which is transferred from the substrate storage container to the processing chambers, is carried out for unloading the substrate to be processed for each processing chamber when the substrate to be processed is unloaded from the substrate storage container. Based on the number ratio and the carry-out interval ,
The unloading number ratio of the substrates to be processed can be processed in each processing chamber within each section of the reference unloading interval after determining a reference unloading interval based on the processing time of the substrate to be processed in each processing chamber. And obtained based on the maximum number of substrates to be processed.
The unloading interval of the substrates to be processed is the number of substrates to be unloaded at the reference unloading interval for each processing chamber, and the number of unloading substrates is unloaded one by one for each processing time of the substrates to be processed in each processing chamber. Interval,
A substrate transport method for a substrate processing apparatus, wherein when the substrate to be processed is processed, the substrate to be processed is unloaded from the substrate storage container according to the transport timing. The ratio of the number of substrates to be processed is based on the processing time of the substrate to be processed in each processing chamber, and the processing time of the processing chamber having the longest processing time among the processing chambers is defined as the reference unloading interval. 5. The substrate transfer method for a substrate processing apparatus according to claim 4 , wherein the determination is made based on the maximum number of substrates to be processed that can be processed in another processing chamber within the interval of the reference carry-out interval. The reference discharge interval on the basis of the waiting time in each section of the reference discharge spaces at each of the processing chambers, the substrate processing according to claim 4 or 5, wherein determining as the latency is shortened A substrate transport method of the apparatus. Each of the plurality of substrates to be processed stored in the substrate storage container is sequentially transferred to a processing chamber to be processed at a predetermined transfer timing, so that the substrates to be processed are concurrently processed in the plurality of processing chambers. A substrate transport method for a substrate processing apparatus for processing a substrate,
Obtaining a ratio of the number of substrates to be processed for each processing chamber within a reference unloading interval determined based on the processing time of the substrate to be processed in each processing chamber;
Obtaining the unloading interval of the substrate to be processed for each processing chamber based on the unloading number ratio of the substrate to be processed ;
The substrate transfer method for a substrate processing apparatus, wherein the transfer timing is obtained based on a carry-out number ratio and a carry-out interval of the substrates to be treated obtained in the respective steps . The step of obtaining the ratio of the number of substrates to be processed is as follows:
If the processing time for processing one substrate to be processed in the processing chamber having the longest processing time among the processing chambers is set as the reference unloading interval, the other unloading chambers within the interval of the reference unloading interval. Obtaining a maximum number n of the substrates to be processed that can be processed;
Temporarily determining the waiting time of the other processing chamber within the interval of the reference carry-out interval when the processing time for processing one substrate in the treatment chamber having the longest processing time is set as the reference carry-out interval;
Temporarily obtaining the waiting time of the processing chamber having the longest processing time within the reference unloading interval when the processing time for processing the n + 1 substrates to be processed in the other processing chamber is set as the reference unloading interval; ,
When these waiting times are compared and the waiting time of the processing chamber with the longest processing time is equal to or shorter than the waiting time of the other processing chamber, the reference carry-out interval is set to 1 in the processing chamber with the longest processing time. The processing time for processing a single substrate to be processed is determined, the ratio of the number of substrates to be processed is 1: n, and the waiting time of the processing chamber with the longest processing time is larger than the waiting time of the other processing chamber. In this case, the step of determining the reference unloading interval as a processing time for processing the n + 1 substrates to be processed in the other processing chamber and setting the unloading number ratio of the substrates to be processed to 1: n + 1. ,
The step of obtaining the unloading interval of the substrate to be processed includes:
When the ratio of the number of substrates to be processed is 1: n, the interval between the numbers of substrates to be processed in the processing chamber with the longest processing time is the interval at which the substrates are unloaded one by one at the reference unloading interval. The unloading interval of the substrates to be processed in another processing chamber is an interval for unloading the n substrates at the reference unloading interval one by one for each processing time,
When the ratio of the number of substrates to be processed is 1: n + 1, the interval between the numbers of substrates to be processed in the processing chamber with the longest processing time is the interval at which the substrates are unloaded one by one at the reference unloading interval. out interval number of the target substrate in another processing chamber, according to claim 7, characterized in that it comprises a step of one by n + 1 sheets and spacing of carrying out one by one for each processing time in the reference discharge gap Substrate transport method of the substrate processing apparatus of the present invention. The step of obtaining the ratio of the number of substrates to be processed is as follows:
If the processing time for processing the m substrates to be processed in the processing chamber having the longest processing time among the processing chambers is set as a reference unloading interval, the processing is performed in another processing chamber within the interval of the reference unloading interval. Obtaining a maximum number n of possible substrates to be processed;
A step of obtaining a waiting time of the other processing chamber in the interval of the reference carry-out interval when a processing time for processing m substrates to be processed is set as a reference carry-out interval in the treatment chamber having the longest processing time;
Temporarily obtaining the waiting time of the processing chamber having the longest processing time within the reference unloading interval when the processing time for processing the n + 1 substrates to be processed in the other processing chamber is set as the reference unloading interval; ,
The m is changed to obtain the maximum number n of the substrates to be processed, the waiting time of the other processing chamber, the waiting time of the processing chamber with the longest processing time, the waiting time of the other processing chamber and the processing time. Determining m, n such that the longest waiting time of the processing chamber is minimized;
The waiting time of the processing chamber having the longest processing time is compared with the waiting time of the processing chamber having the longest processing time by comparing the waiting time of the other processing chamber at the determined m and n and the waiting time of the processing chamber having the longest processing time. In the case where the waiting time is equal to or shorter than the waiting time, the reference unloading interval is determined as a processing time for processing m substrates to be processed in the processing chamber having the longest processing time, and the unloading number ratio of the substrates to be processed is m: n. When the waiting time of the processing chamber with the longest processing time is longer than the waiting time of the other processing chamber, the processing time for processing the n + 1 substrates to be processed in the other processing chamber is set to the reference carry-out interval. And a step of setting the carry-out number ratio of the substrate to be processed to m: n + 1,
The step of obtaining the unloading interval of the substrate to be processed includes:
When the ratio of the number of substrates to be processed is m: n, the number of substrates to be processed in the processing chamber with the longest processing time is set to m at the reference unloading interval for each processing time. The interval for unloading the substrates in the other processing chambers is the interval for unloading the substrates to be processed, and the interval for unloading the n substrates at the reference unloading interval is one interval for each processing time.
When the ratio of the number of substrates to be processed is m: n + 1, the interval of the number of substrates to be processed in the processing chamber with the longest processing time is set to m at the reference unloading interval for each processing time. The interval for unloading the substrates one by one is set, and the interval for unloading the substrates to be processed in the other processing chamber is n + 1 for the reference unloading interval, and the interval for unloading one for each processing time. The substrate transport method for a substrate processing apparatus according to claim 7 , further comprising the step of:

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