TWI402937B - 互連結構及其製造的方法 - Google Patents
互連結構及其製造的方法 Download PDFInfo
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- 229910052719 titanium Inorganic materials 0.000 claims description 13
- 239000007769 metal material Substances 0.000 claims description 12
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- 230000008021 deposition Effects 0.000 claims description 11
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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Description
本發明係關於半導體裝置製程領域。特別是,關於具有溝渠與介層的互連結構及其製造的方法。
在半導體裝置製程領域中,主動式半導體裝置(例如電晶體)係由一般眾所皆知的前段製程(FEOL)技術來製造。在主動式裝置形成以後,互連或互連結構(在此整個申請案中,這些名稱可交替使用)可使用眾所皆知的後段製程(BEOL)技術來形成或產生。互連例如包括溝渠及/或介層,由傳導性與/或金屬材料製成,其可使用來選擇性連接一組主動式裝置,以達成所希望的功能或效能或其組合。此外,兩層或更多層互連結構可一起形成,以產生互連區塊,在此稱為互連單元。
習知上,在層間介電材料層中首先產生一或多個介層開口以形成互連結構或互連結構層。層間介電材料層可形成或沈積在前層的互連層或互連結構的表面上,係譬如經由在技藝中眾所皆知的習知化學氣相沈積或有機金屬化學氣相沈積技術。然後,在相同的層間介電層之至少一或多個介層開口產生的區域或面積中,產生一或多個溝渠開口。因此溝渠開口可至少部分與介層開口重疊。在介層與溝渠開口之結構形成以後,但在某種傳導材料充填開口以前,襯層(可為金屬襯層)可沈積在層間介電層中之開口的底部上與/或側壁。誠如該項技藝中所熟悉,例如在互連結構的製造期間內,可將襯層沈積沉積到層間介電層,以減少與/或避免傳導材料(其在後續步驟中充填介層與溝渠開口)擴散到層間介電材料。傳導金屬材料擴散至層間介電層尤其會造成裝置匱乏與效能降低。
習知上,金屬襯層的厚度係沈積到足以對介層開口提供相當好覆蓋。然而,在溝渠區域中的金屬襯層與在介層區域中的同時沈積,且因此具有受沈積於介層區域中之金屬襯層厚度所支配的厚度,其可能比所需要的厚度更厚,誠如在已知技藝中,溝渠一般需要較小的襯層覆蓋。因此,在溝渠區域中較厚的金屬襯層,結合襯層材料相對低的傳導率,可導致在隨後溝渠區域中所形成的金屬線整體的高電阻。
除了可能的高電阻以外,在該技藝中同樣眾所皆知的,如上述習知形成互連結構的製程,會導致溝渠或金屬線,具有粗糙的溝渠底部。在溝渠底部的粗糙係為已知,如以下所詳細說明,其係藉由在施加金屬襯層到介層與溝渠開口前進行介層挖鑿所造成。當使用超低介電k常數(ULK)材料層作為層間介電層時,此粗糙會變得特別嚴重。粗糙的溝渠底部會造成裝置效能降低,例如增加電阻與可能缺乏鄰近主動式裝置,且嚴重時會造成溝渠形成具有較小的深度。
因此,在技藝中需要在形成互連結構的期間內修改使用於溝渠區域與介層區域中的襯層厚度,以達到較佳的裝置效能。此亦需要在形成互連結構的期間內,減緩以上習知製程所造成之溝渠底部粗糙。
本發明實施例提供一種在層間介電材料層中形成互連結構方法。該方法的實施例教示在層間介電材料層中產生一或多個介層開口;形成第一襯層,以覆蓋一或多個介層開口之至少其中一個;產生一或多個溝渠開口在第一襯層所覆蓋之一或多個介層開口之至少一個的頂部上;以及形成第二襯層覆蓋一或多個溝渠開口之至少其中一個與第一襯層之至少一部分。該方法進一步教導以傳導材料來充填介層開口與溝渠開口,並且平坦化傳導材料,致使與層間介電材料層頂表面共面,以形成互連結構,其中介層開口係由第一與第二襯層覆蓋,且溝渠開口係由第二襯層覆蓋。
根據一實施例,該方法教導在形成第一襯層前,挖鑿介層開口,以產生一鑿穴於一前層互連結構之傳導區域中介層開口的底部,其中挖鑿包含離子濺射介層開口之底部,以產生適合第一襯層沈積之鑿穴。
根據另一實施例,形成第一及/或第二襯層包括將金屬襯層材料層沈積在介層開口上。金屬襯層材料可選自鉭、氮化鉭、鈦、氮化鈦、鎢、氮化鎢與釕所組成之群組。金屬襯層材料層的厚度範圍從1個金屬原子單層至數十個原子單層,且較佳地介於1個與5個原子單層之間。
根據再另一實施例,產生一或多個介層開口包括形成代表介層開口之頂視圖的光遮罩圖案,以及施加濕式蝕刻將圖案複製到層間介電材料,以產生介層開口。同樣地,產生一或多個溝渠開口包括形成代表溝渠開口之頂視圖的光遮罩圖案,以及施加濕式蝕刻將圖案部分地複製到與介層開口重疊的層間介電層材料,以產生溝渠開口。
本發明實施例亦在半導體晶片中提供連接一個或多個半導體裝置之互連結構。互連結構包括一或多個介層;形成在一或多個介層之至少其中一個之頂部上的一或多個溝渠;第一襯層襯在一或多個介層之至少其中一個之週邊;以及第二襯層襯在一或多個溝渠與第一襯層週邊。根據一實施例,第一及/或第二襯層包
括鉭、氮化鉭、鈦、氮化鈦、鎢、氮化鎢與釕材料。
本發明實施例進一步提供一種互連結構,在溝渠與介層具有修改的襯層厚度,以用來提高信賴度之介層的結構性完整,且透過較為改善的襯層範圍以減少寄生電性降低,同時使溝渠的傳導性能最佳化。
在以下的詳細說明中提供數個特定細節的說明,以便提供對本發明實施例的完整理解。然而,那些熟諳該技藝者將理解到,本發明實施例可在無需這些特定細節之下實施。在其他實例中,眾所皆知的方法與程序不詳細說明,以不混淆本發明實施例。
習知的後段製程包括以下眾所皆知的操作或步驟,尤其是例如介電阻障(〝帽蓋〞)沈積、層間介電沈積、硬遮罩或光遮罩沈積、光學微影、濕式蝕刻或乾式蝕刻以及沈積。然而,為了不混淆本發明本質的呈現,在該技藝中眾所皆知的製程步驟可一起合併呈現及/或顯示,且在一些實例中不詳細說明。熟諳該技藝者將能理解到,以下的說明聚焦在本發明的特殊特徵及/或元件。
圖1-5係說明習知形成互連單元與/或互連結構的
製程及/或方法。例如,圖1說明可在前層互連結構10頂部上形成互連結構20。如圖1所示,介電阻障層21可直接形成或沈積在前層互連結構10的頂部上,而層間介電層22則可連續地形成於其上。接著,經由例如蝕刻製程,可產生或形成一或多個介層開口23在層間介電層22中。介層開口23可或可不向下蝕刻至介電阻障層21。當介層開口23蝕刻入介電阻障層21時,介電阻障層21可不被蝕刻穿來導致前層互連結構10之溝渠及/或介層14的暴露。前層互連結構10亦可被稱為前層互連層或前層金屬層10,其可包括嵌入在前層之層間介電層12中的一或多個金屬溝渠及/或介層14。
介電阻障層21可形成或沈積在前層互連層10的頂部上,以致使層間介電層22有適當的過度蝕刻,並且提供變異所造成的製程容差。根據習知製程,介電阻障層21提供保護給金屬結構,例如前層互連層10的銅結構,使其免於破壞性的裝置製程環境,譬如光阻(resist)移除,以及藉由將化學物加工處理入金屬結構而造成結構可靠度問題的可能表面擴散。因此,介電阻障層21可能不會被蝕刻穿,且蝕刻製程可不需要充分控制。
圖2說明在產生以後,介層開口23可以某種平坦
化材料充填,例如抗反射塗層(ARC)材料32。抗反射塗層材料32可充填介層開口23並且覆蓋層間介電層22的頂表面。誠如在習知技藝中所皆知的,光阻污染可能發生在此階段,如一般在進階的整合結構中所見的。由於譬如介層開口23的介電結構與譬如抗反射塗層材料32的光阻材料之間的不適當互動,會發生光阻污染。光阻污染妨礙光阻材料32特徵中適當的顯影,假如可能的話應避免。
在施加或使用後製程技術的期間內,抗反射塗層材料32的頂表面可被平坦化。平坦化包括但不限於旋塗程序最佳化、熱回流或化學機械研磨。在抗反射塗層材料32的平坦化頂表面上,光遮罩34隨後可使用這樣的技術來形成,例如微影技術或者在該技藝中已知的其他習知技術。在形成以後,代表所需的及/或預定的溝渠形狀的光遮罩34圖案,可藉由使用例如反應性離子蝕刻技術的技術複製到或轉移到層間介電層22,如圖3所示。溝渠圖案的蝕刻可停止在預定深度,其比介層開口23更淺,因而在介層開口23的頂部上形成一或多個溝渠開口25。在形成溝渠開口25以後,留在介層開口23中的抗反射塗層材料32會被移除或剝去,其使用眾所皆知的濕式蝕刻或其他技術,以暴露出在介層開口23底部的介電阻障層21(如圖1)。在介層開口23底部的介電阻障層21隨後可藉由其中
一習知蝕刻製程來移除,以暴露在前層互連結構10的溝渠及/或介層14的金屬元件。
習知上,沈積襯層30在溝渠開口25與介層開口23之暴露表面上以前,如圖4所示,可進行譬如離子濺射的介層挖鑿,以減緩在介層開口23底部上的應力,以便改善襯層30到前層互連層10中之溝渠及/或介層14之金屬元件的黏著度。然而,改善襯層30到金屬元件之黏濁度的同時,介層挖鑿可使溝渠25底部變粗糙,以形成粗糙32’。當多孔超低k-常數材料使用當作層間介電層22時,粗糙32’會變得特別嚴重。如在該技藝中眾所皆知的,多孔超低k-常數層間介電層經常會使用來減少互連結構的寄生電容,且常增強由裝置操作速度裝置來度量的效能。
圖5說明在形成襯層30以後,傳導性金屬材料24會根據習知製程而充填在介層與溝渠開口中。傳導性金屬材料24可藉由襯層30而與例如多孔超低k常數材料的層間介電層22分隔或與隔絕。在將傳導金屬材料24沈積或充填於介層與溝渠開口23與25以後,可利用譬如化學機械研磨製程的平坦化製程,而產生互連層或互連結構20的平坦頂表面26。
根據以上習知製程,因為襯層30設計成具有足夠
厚度,以便提供對介層開口23的良好覆蓋。在溝渠開口中的襯層30厚度,在相同製程期間內沈積並且因此藉由介層開口23的厚度所限制,對溝渠開口25而言一般不適合或不能修改。例如,在溝渠開口25側壁上的襯層30會比所需的還厚,因此造成溝渠整個電阻的增加,溝渠包括傳導性金屬材料24與襯層30。襯層30係為一金屬襯層。
同樣地亦如圖5所示,在溝渠開口25底部的粗糙32’會造成裝置效能降低,例如電阻增加與可能缺乏相鄰的主動式裝置。在嚴重的情形中,這會造成所形成溝渠之可能深度的限制。
根據本發明一實施例,提供了一種產生互連層或結構的方法或製程,其溝渠與介層分別具有不同厚度的雙重襯層。根據本發明另一實施例,可提供一種在介層底部但不在溝渠底部產生介層挖鑿的互連結構的方法與製程。
圖6-11說明根據本發明一實施例所設計之雙重襯層互連結構及/或互連單元及其製造製程。在圖6中,介電阻障層41可形成或沈積在前層互連層10的頂部上。介電阻障層41可包括例如氮化矽、氮碳氫化矽或其他合適的含矽及/或含氮材料的材料。圖6進一步顯
示藉由沈積層間介電層42於介電阻障層41頂部上,互連結構40經由介電阻障層41而形成在前層互連層10上。一或多個介層開口43隨後可經由例如在層間介電層42中的蝕刻而產生或形成。介層開口43可蝕刻入與蝕刻穿介電阻障層41。根據本發明一實施例,介電阻障層41可在此階段移除(相較於圖2所示的習知製程),而不會引起可靠度以及/或者對前層互連層或前層金屬層10之介層14金屬結構的損壞,如以下參考圖7的詳細說明。前層金屬層10可包括一或多個溝渠及/或介層14,其由金屬或金屬元件製成,譬如銅(Cu)或其他適合的傳導材料。溝渠及/或介層14係嵌入在層間介電層12中。
圖7說明在產生之後,襯層材料層或襯層50可沈積在介層開口43的底部與側壁上,以及互連結構40的頂部上。襯層50可為金屬襯層,其並且包括譬如鉭、氮化鉭、鈦、氮化鈦、鎢、氮化鎢與釕的材料。襯層50的厚度範圍從1個金屬原子單層至數十個原子單層,較佳地介於1個與5個原子單層之間。然而,本發明不限於呈此態樣,且可依據其他因子(例如襯層50材料)而使用其他厚度。可組合多層的上述襯層材料,以形成較佳效能的多層複合阻障結構。根據本發明實施例,藉由保護前層金屬層或前層互連層10的介層14金屬(例如,銅)結構並且覆蓋層間介電層42
的介電介層開口43之結構,金屬襯層50的施加促使介電阻障層41在此階段能夠移除(如圖6),而不會造成可能的可靠度及/或對介層14金屬結構的損壞,並避免在隨後製程步驟中光阻的污染。
在金屬襯層50沈積以前,可進行介層挖鑿以減緩在介層開口43底部的壓力,以改善金屬襯層50到前層互連層10之介層14金屬元件的黏著度。根據本發明實施例,因為介層挖鑿在溝渠開口55產生以前進行(如圖9),所以可避免如圖4所示由介層挖鑿所造成之溝渠底部的粗糙。根據本發明另一實施例,因為金屬襯層50可在光阻材料52充填介層開口43以前沈積(如圖8),所以金屬襯層50可避免光阻材料52直接接觸介電材料(41與42)以及介層14金屬元件,從而避免介電材料(41與42)以及介層14金屬元件與光阻材料的潛在負面及/或不適當的互動,如在圖2所示的習知製程中所發生的。
圖8說明在襯層50覆蓋以後,介層開口43隨後可充填適合平坦化的材料52。材料52包括但不限於OPL(有機平坦化層)、IPL(無機平坦化層)、ARC(抗反射塗層)、或其組合。材料52的頂表面隨後會平坦化,且在材料52的平坦化頂表面上,可使用在該技藝
中眾所皆知的習知微影顯影技術之顯影光遮罩54。
接著形成代表所需及/或預定形成之溝渠圖案的光遮罩54,經由所知為線層蝕刻的製程以及使用一或多個習知例如反應性離子蝕刻的方法,可複製溝渠圖案到層間介電層42,如圖9所示。可使用複數個技術的組合,譬如一致性蝕刻製程,其為非選擇性,以打開抗反射塗層、金屬襯層與層間介電材料。或者,可使用選擇性製程,其首先打開抗反射塗層,接著為金屬蝕刻化學,以移除在微影定義圖案區域中的金屬襯層。蝕刻可為富含氟以避免可能的金屬殘渣。然後,個別的介電質蝕刻製程,在比介層開口43更淺的預定或所需的深度停止,可用來形成一或多個溝渠開口55於介層開口43頂部上。
根據本發明一實施例,選擇性與非選擇性蝕刻製程的組合可用來控制在介層區域中抗反射塗層材料52之凹處的範圍,以確保在介層底部的金屬襯層50受到保護。溝渠開口55產生或形成在至少一介層開口43的頂部上,其具有與底下介層開口43之直徑大約相等的寬度,並且在至少一側上,垂直對準介層開口43。然而,熟諳該技藝者將理解到,本發明不限於此態樣,且溝渠開口55會具有與介層開口43不同的寬度,此外,其不一定會垂直對準介層開口43,如圖9所示。
再者,介層開口43會具有除了像圓筒以外的形狀。在溝渠開口形成以後,留在層間介電層42頂表面上的光遮罩54與留在介層開口43中的抗反射塗層材料52,會藉由施加在該技藝中眾所皆知的技術來移除,例如濕式蝕刻技術。
接著,第二層襯層51會施加或沈積在溝渠開口55的暴露側壁上以及介層開口43內之第一層襯層50的頂部上,如圖10所示。襯層51係為金屬襯層,其並且包括譬如鉭、氮化鉭、鈦、氮化鈦、鎢、氮化鎢與釕的材料。由於襯層51的沈積主要應用於覆蓋溝渠開口55,因此不會受到覆蓋介層開口43之襯層50的厚度所限制,襯層51的厚度可獨立調整。例如,襯層51的厚度會最佳化以達到相對的低,以及可能的最小電阻。一般而言,襯層51的厚度範圍從1個金屬原子單層至數十個原子單層,較佳地介於1個與5個原子單層之間,但是本發明不限於在此態樣,且可依據其他因子(包括但不限於襯層51材料)來使用其他厚度。可合併複數層上述襯層材料,以形成最佳效能的多層複合阻障結構。
在第二層襯層51沈積以後,介層開口43與溝渠開口55可充填適合互連主動式裝置之金屬材料,譬如銅、金、銀、鎢與其合金以及/或者化合物,如圖11
所示。開口43與55的充填可經由電鍍或晶種,形成互連金屬線44。充填介層開口43與溝渠開口55之金屬材料的頂表面可平坦化,例如經由化學機械研磨製程而與互連結構40的頂表面共面。最終平表面46可適合隨後的裝置製程,譬如下一層互連層的製造。
本發明所提供的額外優點係為複數個金屬襯層沈積可修改,以提供較厚的襯層於場內。在上述的銅化學機械研磨期間內,較厚的襯層會提供較寬的製程窗。例如,在兩步驟的銅化學機械研磨拋光期間內,該製程會設計成停止在場襯層或襯層50上(如圖10)。在無需與下方介電材料完整性妥協之下,較厚的場襯層50促使更多積極銅拋光。此外,在銅拋光步驟與襯層之間缺乏選擇性,為導致非平坦化之因。本發明所提供的較厚襯層會改善平坦化。
雖然本發明的特定特徵在此已經顯示與說明,但是熟諳該技藝者可知仍有許多修改、替代、改變與等同物。因此,要理解的是,附加申請專利範圍意圖包含所有此種修改與改變在本發明範圍內。
10‧‧‧前層互連結構、前層互連層、前層金屬層
12‧‧‧層間介電層
14‧‧‧介層
20‧‧‧互連結構
21‧‧‧介電阻障層
22‧‧‧層間介電層
23‧‧‧介層開口
25‧‧‧溝渠開口
30‧‧‧襯層
32’‧‧‧粗糙
32‧‧‧抗反射塗層(ARC)材料
34‧‧‧光遮罩
40‧‧‧互連結構
41‧‧‧介電阻障層
42‧‧‧層間介電層
43‧‧‧介層開口
44‧‧‧金屬襯層
46‧‧‧平表面
50‧‧‧襯層
51‧‧‧第二層襯層
52‧‧‧光阻材料
54‧‧‧光遮罩
55‧‧‧溝渠開口
本發明可從結合以下附圖與本發明詳細說明來作更完整的理解與領會:
圖1-5係說明習知形成互連單元及/或互連結構的製程及/或方法;以及圖6-11係說明根據本發明一實施例所設計之雙襯層互連結構及/或互連單元及其製造製程。
將可會理解為了簡化與清楚顯示,在圖式中所顯示的元件不一定按比率繪製。例如,為了清楚起見,相對於其他元件,一些元件的尺寸可被誇大。
10...互連結構
12...層間介電層
14...介層
40...互連結構
41...介電阻障層
42...層間介電層
44...金屬襯層
46...平表面
50...襯層
51...第二層襯層
Claims (30)
- 一種於層間介電(ILD)材料層形成互連結構的方法,該方法包含:產生一或多個介層開口在該層間介電材料層中;形成一第一襯層覆蓋該一或多個介層開口之至少其中一個;產生一或多個溝渠開口在該一或多個介層開口之至少其中一個的頂部上,該一或多個介層開口的底部及側壁被該第一襯層所覆蓋,其中該一或多個之溝渠開口之至少一個係離開或不在該一或多個介層開口頂部;以及形成一第二襯層覆蓋該一或多個溝渠開口及該第一襯層之至少一部分。
- 如申請專利範圍第1項之方法,進一步包含:以一傳導材料來充填該介層開口與該溝渠開口;以及平坦化該傳導材料,致使與該層間介電材料層之一頂表面共面,以形成該互連結構,其中該介層開口係由該第一與第二襯層覆蓋,且該溝渠開口係由該第二襯層覆蓋。
- 如申請專利範圍第1項之方法,其中該傳導材料係選自銅、金、銀、鎢或其組合所組成之群組。
- 如申請專利範圍第1項之方法,進一步包含在形成該第一襯層前,挖鑿該介層開口,以產生一鑿穴於一前層互連結構之一傳導區域中之該介層開口的底部。
- 如申請專利範圍第4項之方法,其中該挖鑿包含離子濺射該介層開口的該底部,以產生適合該第一襯層沈積的該鑿穴。
- 如申請專利範圍第1項之方法,其中形成該第一襯層包含沈積一金屬襯層材料層到該介層開口上,且該金屬襯層材料係選自鉭、氮化鉭、鈦、氮化鈦、鎢、氮化鎢與釕所組成之群組。
- 如申請專利範圍第6項之方法,其中該金屬襯層材料層具有厚度範圍從1個金屬原子單層至數十個原子單層,且較佳地介於1個與5個原子單層之間。
- 如申請專利範圍第1項之方法,其中形成該第二襯層包含沈積一金屬襯層材料層在該介層開口與該溝渠開口上,且該金屬襯層材料係選自鉭、氮化 鉭、鈦、氮化鈦、鎢、氮化鎢與釕所組成之群組。
- 如申請專利範圍第8項之方法,其中該金屬襯層材料層具有厚度範圍從1個金屬原子單層至數十個原子單層,且較佳地介於1個與5個原子單層之間。
- 如申請專利範圍第1項之方法,其中產生該一或多個介層開口包含形成代表該介層開口之一頂視圖的一光遮罩圖案,以及施加濕式蝕刻將該光遮罩圖案複製到該層間介電材料,以產生該介層開口。
- 如申請專利範圍第1項之方法,其中產生該一或多個溝渠開口包含形成代表該溝渠開口之一頂視圖的一光遮罩圖案,以及施加濕式蝕刻將該光遮罩圖案部分地複製到與該介層開口重疊的該層間介電材料,以產生該溝渠開口。
- 一種形成包括至少一第一與一第二互連結構層之多層互連單元的方法,該方法包含:形成一層間介電材料層在該第一互連結構層上;產生一或多個介層開口在該層間介電材料層中;形成一第一襯層覆蓋該一或多個介層開口之 至少其中一個;產生一或多個溝渠開口於該一或多個介層開口之至少其中一個的頂部上,該一或多個介層開口的底部及側壁被該第一襯層所覆蓋,其中該一或多個之溝渠開口之至少一個係離開或不在該一或多個介層開口頂部;以及形成一第二襯層覆蓋該一或多個溝渠開口與該第一襯層之至少一部分。
- 如申請專利範圍第12項之方法,進一步包含在形成該層間介電材料層前,形成一介電阻障層。
- 如申請專利範圍第12項之方法,進一步包含:電鍍一金屬材料在該層間介電材料層中所產生的該介層開口與溝渠開口;以及平坦化該金屬材料,致使與該層間介電材料之一頂表面共面,以形成該第二互連結構層,其中該介層開口係由該第一與第二襯層所覆蓋,且該溝渠開口係由該第二襯層所覆蓋。
- 如申請專利範圍第14項之方法,進一步包含在形成該第一襯層前,挖鑿該介層開口,以暴露該第一互連結構層的金屬互連元件。
- 如申請專利範圍第15項之方法,其中該挖鑿包含離子濺射該介層開口之一底部,以準備沈積該第一襯層之一鑿穴。
- 如申請專利範圍第12項之方法,其中形成該第一襯層包含沈積一金屬襯層材料層在該介層開口上,該金屬襯層材料係選自鉭、氮化鉭、鈦、氮化鈦、鎢、氮化鎢與釕所組成之群組。
- 如申請專利範圍第17項之方法,其中該金屬襯層材料層具有厚度範圍從1個金屬原子單層至數十個原子單層,且較佳地介於1個與5個原子單層之間。
- 一種形成互連單元的方法,該方法包含:直接在一第一互連層上形成一介電阻障層;形成一層間介電材料層在該介電阻障層上;產生一或多個介層開口在該層間介電材料層中;形成一第一金屬襯層以覆蓋該一或多個介層開口之至少其中一個;產生一或多個溝渠開口在該一或多個介層開口之至少其中一個的頂部上,該一或多個介層開口的底部及側壁被該第一金屬襯層所覆蓋,其中該一 或多個之溝渠開口之至少一個係離開或不在該一或多個介層開口頂部;以及形成一第二金屬襯層,以覆蓋該一或多個溝渠開口以及該第一金屬襯層之至少一部分。
- 如申請專利範圍第19項之方法,進一步包含:電鍍一金屬材料在該層間介電材料層中所產生的該介層開口與溝渠開口中;以及平坦化電鍍有該金屬材料之該層間介電材料之一頂表面,以形成該第二互連結構層,其中該介層開口係由該第一與第二襯層所覆蓋,且該溝渠開口係由該第二襯層所覆蓋。
- 如申請專利範圍第20項之方法,其中該平坦化該層間介電材料的該頂表面包含利用一化學機械研磨製程,使該頂表面變平。
- 如申請專利範圍第19項之方法,進一步包含在形成該第一襯層前,挖鑿該介層開口,以暴露該第一互連結構層的一金屬互連元件。
- 如申請專利範圍第22項之方法,其中該挖鑿包含離子濺射該介層開口的一底部,以準備沈積該第一襯層之一鑿穴。
- 如申請專利範圍第19項之方法,其中形成該第一襯層包含沈積一金屬襯層材料層到該介層開口上,該金屬襯層材料係選自鉭、氮化鉭、鈦、氮化鈦、鎢、氮化鎢與釕所組成之群組。
- 如申請專利範圍第24項之方法,其中該金屬襯層材料層具有厚度範圍從1個金屬原子單層至數十個原子單層,且較佳地介在1個與5個原子單層之間。
- 一種半導體晶片中連接一或多個半導體裝置之互連結構,該互連結構包含:一或多個的介層,形成在一層的層間介電材料中;一或多個溝渠,形成在該一或多個介層之至少其中一個的頂部上,其中該一或多個之溝渠開口之至少一個係離開或不在該一或多個介層開口頂部;一第一襯層,襯在該一或多個介層之至少其中一個之週邊,其包含底部及側壁;以及一第二襯層,襯在該一或多個溝渠與該第一襯層之週邊。
- 如申請專利範圍第26項之互連結構,進一步包含 在該層間介電材料與一前層互連結構之間的一層介電阻障層。
- 如申請專利範圍第26項之互連結構,其中該第一襯層包含鉭、氮化鉭、鈦、氮化鈦、鎢、氮化鎢、釕材料或其組合。
- 如申請專利範圍第26項之互連結構,其中該第二襯層包含鉭、氮化鉭、鈦、氮化鈦、鎢、氮化鎢、釕材料或其組合。
- 如申請專利範圍第26項之互連結構,其中該一或多個介層具有鑿穴,形成在一前層互連結構之一傳導區域。
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US7955971B2 (en) * | 2009-06-11 | 2011-06-07 | International Business Machines Corporation | Hybrid metallic wire and methods of fabricating same |
US8232196B2 (en) * | 2009-10-29 | 2012-07-31 | International Business Machines Corporation | Interconnect structure having a via with a via gouging feature and dielectric liner sidewalls for BEOL integration |
US20110204517A1 (en) * | 2010-02-23 | 2011-08-25 | Qualcomm Incorporated | Semiconductor Device with Vias Having More Than One Material |
US8609534B2 (en) | 2010-09-27 | 2013-12-17 | International Business Machines Corporation | Electrical fuse structure and method of fabricating same |
US10199232B2 (en) | 2011-02-24 | 2019-02-05 | United Microelectronics Corporation | Conductor line structure |
US9418886B1 (en) * | 2015-07-24 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming conductive features |
US9373543B1 (en) * | 2015-10-06 | 2016-06-21 | Globalfoundries Inc. | Forming interconnect features with reduced sidewall tapering |
US10541204B2 (en) | 2015-10-20 | 2020-01-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnection structure and method of forming the same |
US9653345B1 (en) * | 2016-01-07 | 2017-05-16 | United Microelectronics Corp. | Method of fabricating semiconductor structure with improved critical dimension control |
US9953865B1 (en) | 2016-10-26 | 2018-04-24 | International Business Machines Corporation | Structure and method to improve FAV RIE process margin and electromigration |
US11264325B2 (en) * | 2017-09-28 | 2022-03-01 | Intel Corporation | Interconnects having a portion without a liner material and related structures, devices, and methods |
US11069562B1 (en) * | 2020-01-15 | 2021-07-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Passivation layer for integrated circuit structure and forming the same |
US11876047B2 (en) * | 2021-09-14 | 2024-01-16 | International Business Machines Corporation | Decoupled interconnect structures |
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