TWI382531B - 用於改良式收集之光偵測器以及n層結構 - Google Patents
用於改良式收集之光偵測器以及n層結構 Download PDFInfo
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Description
本發明大體而言係關於影像感應器之領域,且更特定言之,係關於具有一輕微摻雜層之影像感應器,其中該摻雜層之導電類型與用於降低串擾之光偵測器之收集區的導電類型相同。
如此項技術中所熟知:主動CMOS影像感應器通常由一像素陣列組成。通常,每一像素由一光偵測器元件及一或多個讀出表示在光偵測器中所感應之光的電壓之電晶體組成。圖1a展示一用於主動像素影像感應器之典型像素布局。該像素由一光二極體光偵測器(PD)、一用於將光生電荷讀出至浮動擴散(FD)上之轉移閘極(TG)組成,該浮動擴散(FD)將電荷轉換為電壓。使用一重設閘極(RG)以在自光二極體讀出信號之前,將浮動擴散重設為電壓VDD。源極隨耦器電晶體之閘極(SF)連接至浮動擴散,以緩衝來自浮動擴散之信號電壓。此經緩衝的電壓經由一用於選擇待讀出之像素列之列選擇電晶體閘極(RS)連接至VO U T
處之行通路(未展示)。
隨著對於在一給定光學格式中之愈來愈高之解析度的需求推動像素大小變得愈來愈小,維持該裝置之其他關鍵效能態樣日益變得更加困難。詳言之,像素之量子效率及串擾開始隨著像素大小之減小而嚴重降級。(量子效率下降且像素之間的串擾增加。)將串擾定義為非照明像素中之信號與照明像素中之信號的比率,且可將其表達為分數或百分比。因此,串擾表示未被其下產生信號之像素收集之信號的相對量。近來,已出現改良量子效率,但以增加的串擾為代價之方法的描述。(參看美國專利第6,225,670 B1號中之圖4)。或者,已採用用於圖像浮散保護(blooming protection)之垂直溢出汲極(VOD)結構,其以量子效率為代價降低了串擾(S.Inoue等人在Eisoseiho Media Gakkai Gijutsu Hokoku(Technology Report,Image Information Media Association)Eiseigakugiko中之"A 3.25 M-pixel APS-C size CMOS Image Sensor",第25卷,第28號,第37至41頁,2001年3月。ISSN 1342-6893。)。
提高光偵測器之耗盡深度將提高裝置之收集效率,藉此改良量子效率及串擾屬性。過去,此藉由降低製造偵測器之散裝材料之摻雜濃度而實現。然而,已知該方法導致電荷容量降低且增加(自散裝擴散組件)產生之暗電流,進而降低偵測器之動態範圍及曝光寬容度。
美國專利第6,297,070號避免了該等特定困難且描述一光偵測器結構,其中光二極體摻雜比用於製造CMOS影像感應器之其他源極及汲極n型摻雜物更深。增加的耗盡深度提高了收集效率,藉此在降低串擾的同時提高了量子效率。然而,當使用高能植入構建該結構時,n型二極體至p型磊晶接合深度(且因此,耗盡深度)受限於用於阻止來自該裝置之其他區之植入的屏蔽層(通常為光阻)的厚度。因此,可在該步驟中使用之最大阻擋厚度及縱橫比(阻擋高度比阻擋開度)變為一限制因素。
此外,在先前技術中,使用一如藉由圖1b及圖1c中之實例之方式說明之單一、相對淺的植入形成一釘紮光二極體之n型區。圖1d中展示了所得之用於該先前技術之空載光二極體之電位分佈。自該圖中,可見用於該例示性先前技術像素結構之耗盡深度(電位之斜率趨於零之點)僅為約1.2 μm。對於綠色及紅色波長,矽中之吸收深度大於該耗盡深度。因此,產生之大於該耗盡深度之載流子可側向地擴散至相鄰感光單元中,此引起串擾。
因此,此技術中存在提供以下結構之需要:該結構同時改良量子效率及串擾屬性,而不影響其他成像效能特性且不存在上述之製造問題。
本發明係針對克服上文陳述之問題中之一或多個問題。簡要言之,根據本發明之一態樣,本發明在於一種具有一影像區域之影像感應器,該影像區域具有複數個為一第一導電類型之光偵測器,該影像感應器包含:一為第二導電類型之基板;一為該第一導電類型之第一層,其橫跨該影像區域;一為該第二導電類型之第二層;其中該第一層係位於該基板與該第二層之間,且該複數個光偵測器係安置於該第二層中且鄰接該第一層。
本發明具有以下優點:其提供一種同時改良量子效率及串擾屬性兩者而不影響其他成像效能特性的結構。
在詳細論述本發明之前,瞭解影像感應器中之串擾係有益處的。在此點上,將串擾定義為非照明像素中信號與照明像素中之信號之比率,且可將其表達為分數或百分比。因此,串擾表示未被其下產生信號之像素收集之信號相對量。圖2說明例示性像素之串擾及內部量子效率(自覆蓋該光偵測器之任何層無反射或吸收損失)對耗盡深度之依賴關係。串擾計算假定沿一直線之每隔一像素發光(且交替的、相間的像素不發光)。假定波長為650 nm,因為串擾在較長波長中問題更嚴重。自該圖可見,增加耗盡深度可顯著降低串擾同時提高量子效率。此外,本文使用之耗盡深度界定為距離該表面最遠之點,電位之斜率在該點處趨於零。
因此,自圖2可見對於先前技術結構,串擾將為~36%且內部量子效率將為~68%。自圖2亦可見,藉由增加耗盡深度,可顯著降低串擾。
本發明描述一用於主動CMOS影像感應器之光偵測器結構,該光偵測器結構具有延伸的耗盡深度以在維持良好電荷容量及動態範圍特性的同時,提高量子效率且降低像素至像素之串擾。圖3中展示本發明之併入該光偵測器結構之CMOS影像感應器像素之俯視圖,其形成一俯視圖且看上去類似於圖1。此是因為圖3之本發明包括圖1中未展示之額外層,因為額外層位於頂面之下,且因此在俯視圖中不可見(最顯著地為第一層及第二層)。雖然展示之較佳實施例包括一釘紮光二極體,其由p-/p++磊晶基板中之p+釘紮(頂面)層及n型嵌入收集區組成,但熟習此項技術者應瞭解可使用其他結構及摻雜類型而不背離本發明之範疇。舉例而言,需要時,可使用形成於p型基板中之簡單非釘紮n型二極體,或形成於n型基板中之p型二極體。亦應注意,為清晰起見,僅展示本發明之影像感應器之一部分。舉例而言,雖然僅展示一光偵測器,但存在排列於一維陣列或二維陣列中之複數個光偵測器。
參看圖3,其展示本發明之像素10,該像素具有一光二極體光偵測器(PD),一用於將光生電荷讀出至浮動擴散(FD)上之轉移閘極(TG),該浮動擴散將電荷轉換為電壓。重設閘極(RG)用於在自光二極體讀出信號之前將浮動擴散重設為電壓VDD。將源極隨耦器電晶體之閘極(SF)連接至浮動擴散,以緩衝來自浮動擴散之信號電壓。該緩衝電壓藉由一用於選擇待讀出之像素列之列選擇電晶體閘極(RS)連接至VO U T
處之行通路(未展示)。在平面圖(圖3)中,將位於光偵測器外,但在該像素內之區界定為像素電路區。
參看圖4a,其展示本發明之一影像感應器20之橫截面中之側視圖。影像感應器20包括一具有複數個光偵測器30(僅展示其中之一)之成像部分,該複數個光偵測器30較佳地係為兩種導電類型之釘紮光二極體30,較佳地具有n型收集區40及p型釘紮層50。一種導電類型(對於較佳實施例較佳地為p型)之基板60為影像感應器20形成基礎部分。一種導電類型(較佳為n型)之第一層70橫跨該影像區域。應注意,該第一層70實體上接觸光二極體30之n型收集區40,藉此擴展光二極體30之耗盡區及光收集區。一種導電類型(較佳為p型)之第二層80係垂直而與第一層70相鄰地安置,以較佳地為(諸如)電晶體部分形成整個或部分電力組件。視情況,第三層90(較佳為p型磊晶層)可位於該第一層70與該基板60之間。
特別指出:該第一層70係位於該基板60與該第二層80之間,且複數個光偵測器30係安置於該第二層80中且其鄰接該第一層70。該第一層70尤其適於大體上降低自光偵測器30散逸至此層中之電子的串擾。第一層70將引導該等雜散電子中之所有或大體上所有雜散電子返回至最近的光偵測器30中,該光偵測器30係最有可能為電子最初自其散逸出之候選者。
為完整起見,應注意影像感應器20包括一具有一種導電類型(較佳為p型)之通道100的轉移閘極(TG)。如上文論述,該通道由第二層80形成且電荷自光偵測器30經由通道100傳遞至一種導電類型(較佳為n型)之浮動擴散110,該浮動擴散將電荷轉換為電壓。一種導電類型(較佳為p型)之通道阻絕層120側向地與光偵測器30相鄰。如此項技術中所熟知,頂層130形成介電質。
因此,本發明延長了耗盡深度,藉此降低了串擾而不會降低量子效率。本發明添加較深且濃度相對較低的層(第一層70),其接觸光偵測器30中之摻雜分佈之主要、較高濃度之表面部分的背面,如圖4a中及圖4b中展示之例示性結構所示。換言之,由於光偵測器30之下的第一層70具有相對低的摻雜物濃度,其耗盡了自由載子。該較深、側向均勻的低濃度層(第一層70)可藉由一系列或一連串相對低劑量的多個高能植入及/或熱驅而形成。本發明之一替代實施例將為經由磊晶成長,形成第一層70及第二層80及位於基板60之頂部的可選第三層90。因為該較深的第一層70形成於整個像素及影像區域下,所以單個像素中之轉移閘極(TG)、浮動擴散110、源極隨耦器(SF)及任何及所有其他支援電路形成於第二層80中。雖然第一層70無疑能夠延伸,但其無需延伸至影像區域之外側的裝置周邊,在該影像區域中通常具有列及行定址電路、A/D轉換器、類比緩衝器等。較深且均勻的第一層70僅需形成於含有所有成像(及暗參考等)像素之影像區域中。
圖5展示降至偵測器之底部之所得電位分佈,自該圖中可見:新結構之此實例的耗盡深度約為2.3 μm。此耗盡深度可藉由增加金相接合之深度(該深度為第一實施例之植入能量及/或熱驅時間之函數)或僅改變用於替代實施例之各種磊晶層的厚度而進一步增加。
本發明之額外益處為第一層70可在第二層80與第三層90之間耗盡釘紮光二極體區域(亦即,像素電路)之外的區域中的自由載子。耗盡像素電路區下方之區域降低了載流子之側向擴散且導致較低的串擾。
參看圖6,其展示一其中安置有本發明之影像感應器20的數位相機140,以說明本發明之典型商業實施例。
10...像素
20...影像感應器
30...光偵測器/光二極體
40...n型收集區
50...p型釘紮層
60...基板
70...第一層
80...第二層
90...第三層
100...通道
110...浮動擴散
120...通道阻絕層
130...頂層
140...數位相機
圖1a為先前技術影像感應器之俯視圖;圖1b為先前技術影像感應器之二維摻雜;圖1c為先前技術影像感應器之摻雜分佈;圖1d為先前技術影像感應器之電位分佈;圖2為串擾對耗盡深度之圖表;圖3為本發明之影像感應器之俯視圖;圖4a為本發明之影像感應器之橫截面;圖4b為本發明之光偵測器之中心下方之摻雜分佈;圖5為本發明之光偵測器之電位分佈;及圖6為用於說明本發明之一典型商業實施例之普通消費者所習慣使用之數位相機的圖解。
20...影像感應器
30...光偵測器/光二極體
40...n型收集區
50...p型釘紮層
60...基板
70...第一層
80...第二層
90...第三層
100...通道
110...浮動擴散
120...通道阻絕層
130...頂層
Claims (12)
- 一種具有一影像區域之影像感應器,該影像區域具有複數個光偵測器,每一光偵測器具有為一第一導電類型之一收集區,該影像感應器包含:(a)一為一第二導電類型之基板;(b)一為該第一導電類型之側向均勻第一層,其橫跨該影像區域;及(c)一為該第二導電類型之第二層;其中,該第一層係位於該基板與該第二層之間,且該複數個收集區係安置於該第二層中且鄰接該第一層。
- 如請求項1之影像感應器,其中每一光偵測器進一步包含一為該第二導電類型之釘紮層。
- 如請求項1之影像感應器,其中該第一導電類型為n型且該第二導電類型為p型。
- 如請求項1之影像感應器,其進一步包含一為該第二導電類型之磊晶層,該磊晶層位於該基板與該第一層之間。
- 如請求項1之影像感應器,其中該第一層耗盡該光偵測器之下方的自由載子。
- 如請求項5之影像感應器,其中該第一層耗盡該光偵測器及像素電路區之下方的自由載子。
- 一種數位相機,其包含:一具有一影像區域之影像感應器,該影像區域具有複數個光偵測器,每一光偵測器具有為一第一導電類型之一收集區,該影像感應器包含: (a)一為一第二導電類型之基板;(b)一為該第一導電類型之側向均勻第一層,其橫跨該影像區域;及(c)一為該第二導電類型之第二層;其中,該第一層係位於該基板與該第二層之間,且該複數個收集區係安置於該第二層中且鄰接該第一層。
- 如請求項7之數位相機,其中每一光偵測器進一步包含一為該第二導電類型之釘紮層。
- 如請求項7之數位相機,其中該第一導電類型為n型且該第二導電類型為p型。
- 如請求項7之數位相機,其進一步包含一為第二導電類型之磊晶層,該磊晶層位於該基板與該第一層之間。
- 如請求項7之數位相機,其中該第一層耗盡自由載子。
- 如請求項11之數位相機,其中該第一層完全耗盡自由載子。
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US11/453,354 US7875916B2 (en) | 2005-09-28 | 2006-06-15 | Photodetector and n-layer structure for improved collection efficiency |
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TW200721474A (en) | 2007-06-01 |
WO2007038107A3 (en) | 2007-10-04 |
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US20070069315A1 (en) | 2007-03-29 |
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