TWI372999B - Method and apparatus for fixing hold time violations in a circuit design - Google Patents

Method and apparatus for fixing hold time violations in a circuit design

Info

Publication number
TWI372999B
TWI372999B TW094117740A TW94117740A TWI372999B TW I372999 B TWI372999 B TW I372999B TW 094117740 A TW094117740 A TW 094117740A TW 94117740 A TW94117740 A TW 94117740A TW I372999 B TWI372999 B TW I372999B
Authority
TW
Taiwan
Prior art keywords
circuit design
hold time
time violations
fixing hold
fixing
Prior art date
Application number
TW094117740A
Other languages
English (en)
Other versions
TW200620115A (en
Inventor
Yigang Sun
Chih-Tung Chen
Jie Gong
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of TW200620115A publication Critical patent/TW200620115A/zh
Application granted granted Critical
Publication of TWI372999B publication Critical patent/TWI372999B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
TW094117740A 2004-05-28 2005-05-30 Method and apparatus for fixing hold time violations in a circuit design TWI372999B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US57526304P 2004-05-28 2004-05-28
US11/030,352 US7278126B2 (en) 2004-05-28 2005-01-05 Method and apparatus for fixing hold time violations in a circuit design

Publications (2)

Publication Number Publication Date
TW200620115A TW200620115A (en) 2006-06-16
TWI372999B true TWI372999B (en) 2012-09-21

Family

ID=34971410

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094117740A TWI372999B (en) 2004-05-28 2005-05-30 Method and apparatus for fixing hold time violations in a circuit design

Country Status (5)

Country Link
US (1) US7278126B2 (zh)
CN (1) CN1985257B (zh)
MX (1) MX2007000249A (zh)
TW (1) TWI372999B (zh)
WO (1) WO2005119530A2 (zh)

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US7325211B1 (en) * 2005-09-02 2008-01-29 Sun Microsystems, Inc. Clock skew modelling using delay stamping
WO2007029051A1 (en) * 2005-09-07 2007-03-15 Freescale Semiconductor Inc. Method and a computer readable medium for analyzing a design of an integrated circuit
US7424693B2 (en) * 2005-10-20 2008-09-09 Agere Systems Inc. Methods for measurement and prediction of hold-time and exceeding hold time limits due to cells with tied input pins
US7406669B2 (en) * 2005-12-06 2008-07-29 Lsi Corporation Timing constraints methodology for enabling clock reconvergence pessimism removal in extracted timing models
US7506293B2 (en) * 2006-03-22 2009-03-17 Synopsys, Inc. Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysis
US8051352B2 (en) * 2006-04-27 2011-11-01 Mentor Graphics Corporation Timing-aware test generation and fault simulation
US7590957B2 (en) * 2006-08-24 2009-09-15 Lsi Corporation Method and apparatus for fixing best case hold time violations in an integrated circuit design
US7844931B2 (en) * 2007-03-01 2010-11-30 International Business Machines Corporation Method and computer system for optimizing the signal time behavior of an electronic circuit design
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US7761832B2 (en) * 2007-11-16 2010-07-20 International Business Machines Corporation Method for incremental, timing-driven, physical-synthesis optimization under a linear delay model
US7966592B2 (en) * 2007-11-29 2011-06-21 Lsi Corporation Dual path static timing analysis
US7913213B2 (en) * 2008-04-10 2011-03-22 Oracle America, Inc. Tool and method for automatically identifying minimum timing violation corrections in an integrated circuit design
US8255851B1 (en) * 2008-06-24 2012-08-28 Marvell Israel (M.I.S.L) Ltd. Method and system for timing design
US7996812B2 (en) * 2008-08-14 2011-08-09 International Business Machines Corporation Method of minimizing early-mode violations causing minimum impact to a chip design
US8079004B2 (en) * 2009-04-30 2011-12-13 Synopsys, Inc. Efficient exhaustive path-based static timing analysis using a fast estimation technique
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US8316340B2 (en) * 2009-07-13 2012-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fixing full-chip violations using flip-flops
US8316334B2 (en) * 2010-02-04 2012-11-20 Qualcomm Incorporated Segment and bipartite graph based apparatus and method to address hold violations in static timing
CN102456087B (zh) * 2010-11-03 2013-12-04 上海华虹集成电路有限责任公司 一种建立时序修复方法
US8347250B2 (en) * 2010-12-22 2013-01-01 Advanced Micro Devices, Inc. Method and apparatus for addressing and improving holds in logic networks
US8448124B2 (en) * 2011-09-20 2013-05-21 International Business Machines Corporation Post timing layout modification for performance
US8468483B2 (en) 2011-10-24 2013-06-18 International Business Machines Corporation Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence
CN102436525B (zh) * 2011-10-27 2014-10-15 西安华芯半导体有限公司 一种集成电路设计过程中多节点并行自动修复保持时间违例的方法
CN102332048B (zh) * 2011-10-27 2013-03-20 山东华芯半导体有限公司 集成电路设计过程中单节点并行自动修复保持时间违例的方法
JP2013175029A (ja) * 2012-02-24 2013-09-05 Fujitsu Semiconductor Ltd 半導体集積回路のレイアウト設計装置、レイアウト設計方法およびレイアウト設計プログラム
US9058456B2 (en) 2012-09-25 2015-06-16 International Business Machines Corporation Method and system to fix early mode slacks in a circuit design
WO2014105988A1 (en) * 2012-12-26 2014-07-03 Synopsys, Inc. Timing bottleneck analysis across pipelines to guide optimization with useful skew
US10810790B1 (en) * 2013-02-28 2020-10-20 TheMathWorks, Inc. Identification and correction of temporal ages in separate signal paths of a graphical model
TWI493370B (zh) * 2013-03-05 2015-07-21 Univ Nat Chiao Tung 工程變更之保持時間修復方法
US9122823B2 (en) 2013-12-20 2015-09-01 International Business Machines Corporation Stacked multiple-input delay gates
US9607122B2 (en) * 2014-01-30 2017-03-28 Mentor Graphics Corporation Timing driven clock tree synthesis
CN104881507B (zh) 2014-02-28 2018-01-19 格芯公司 修复电路中的保持时间违例的方法和装置
US9280630B1 (en) 2014-11-07 2016-03-08 International Business Machines Corporation Modified standard cells to address fast paths
CN105701266B (zh) * 2014-11-28 2019-05-07 国际商业机器公司 用于电路设计中的静态时序分析的方法和系统
US9519746B1 (en) 2015-06-11 2016-12-13 International Business Machines Corporation Addressing early mode slack fails by book decomposition
CN106777441B (zh) * 2015-11-24 2020-04-21 龙芯中科技术有限公司 时序约束管理方法及装置
US10002225B2 (en) * 2016-02-12 2018-06-19 Synopsys, Inc. Static timing analysis with improved accuracy and efficiency
CN105787213B (zh) * 2016-04-01 2019-02-05 中国人民解放军国防科学技术大学 一种保持时间违反的修复方法
US10089194B2 (en) * 2016-06-08 2018-10-02 Qualcomm Incorporated System and method for false pass detection in lockstep dual core or triple modular redundancy (TMR) systems
US10001523B2 (en) 2016-08-16 2018-06-19 International Business Machines Corporation Adjusting latency in a scan cell
US10060971B2 (en) 2016-08-16 2018-08-28 International Business Machines Corporation Adjusting latency in a scan cell
US10416232B1 (en) * 2018-06-19 2019-09-17 Xilinx, Inc. Timing optimizations in circuit designs using opposite clock edge triggered flip-flops
CN110111020B (zh) * 2019-05-16 2021-03-02 天津飞腾信息技术有限公司 基于自动评估建立时间余量的保持时间修复方法、系统及介质
CN113626994B (zh) 2021-07-23 2022-11-22 东南大学 一种寄存器时序约束灵活建模方法
CN113673193B (zh) 2021-08-09 2022-11-22 东南大学 一种基于寄存器灵活时序库的电路时序优化方法
US11947891B2 (en) * 2021-08-20 2024-04-02 International Business Machines Corporation Balancing cycle stealing with early mode violations
US11894845B1 (en) 2022-08-30 2024-02-06 Globalfoundries U.S. Inc. Structure and method for delaying of data signal from pulse latch with lockup latch

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JP2001188819A (ja) * 2000-01-04 2001-07-10 Toshiba Microelectronics Corp ホールド違反改善方法、半導体集積回路、及びコンピュータ読み出し可能な記憶媒体
US6591407B1 (en) 2000-03-01 2003-07-08 Sequence Design, Inc. Method and apparatus for interconnect-driven optimization of integrated circuit design
JP4237434B2 (ja) 2001-11-26 2009-03-11 富士通マイクロエレクトロニクス株式会社 集積回路のホールドタイムエラー修正方法及びその修正プログラム
US6701505B1 (en) 2001-11-30 2004-03-02 Sequence Design, Inc. Circuit optimization for minimum path timing violations
EP1396801A1 (de) * 2002-09-05 2004-03-10 Siemens Aktiengesellschaft Verfahren zum Entwickeln eines elektronischen Bausteins
US6886147B2 (en) * 2002-12-31 2005-04-26 Lsi Logic Corporation Method, system, and product for achieving optimal timing in a data path that includes variable delay lines and coupled endpoints
US6990645B2 (en) * 2003-04-29 2006-01-24 International Business Machines Corporation Method for static timing verification of integrated circuits having voltage islands

Also Published As

Publication number Publication date
WO2005119530A2 (en) 2005-12-15
TW200620115A (en) 2006-06-16
CN1985257B (zh) 2011-03-30
US20050268263A1 (en) 2005-12-01
US7278126B2 (en) 2007-10-02
MX2007000249A (es) 2007-04-09
WO2005119530A3 (en) 2006-07-20
CN1985257A (zh) 2007-06-20

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