TWI369772B - Semiconductor device and display device having alignment mark - Google Patents

Semiconductor device and display device having alignment mark

Info

Publication number
TWI369772B
TWI369772B TW096140319A TW96140319A TWI369772B TW I369772 B TWI369772 B TW I369772B TW 096140319 A TW096140319 A TW 096140319A TW 96140319 A TW96140319 A TW 96140319A TW I369772 B TWI369772 B TW I369772B
Authority
TW
Taiwan
Prior art keywords
alignment mark
display device
semiconductor device
semiconductor
display
Prior art date
Application number
TW096140319A
Other languages
Chinese (zh)
Other versions
TW200834866A (en
Inventor
Hideaki Horii
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of TW200834866A publication Critical patent/TW200834866A/en
Application granted granted Critical
Publication of TWI369772B publication Critical patent/TWI369772B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Multimedia (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Liquid Crystal (AREA)
  • Structure Of Printed Boards (AREA)
TW096140319A 2006-11-28 2007-10-26 Semiconductor device and display device having alignment mark TWI369772B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006319568A JP5425363B2 (en) 2006-11-28 2006-11-28 Semiconductor device and display device

Publications (2)

Publication Number Publication Date
TW200834866A TW200834866A (en) 2008-08-16
TWI369772B true TWI369772B (en) 2012-08-01

Family

ID=39462730

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096140319A TWI369772B (en) 2006-11-28 2007-10-26 Semiconductor device and display device having alignment mark

Country Status (5)

Country Link
US (1) US7825529B2 (en)
JP (1) JP5425363B2 (en)
KR (1) KR100928856B1 (en)
CN (1) CN101192596B (en)
TW (1) TWI369772B (en)

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* Cited by examiner, † Cited by third party
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JP4378387B2 (en) * 2007-02-27 2009-12-02 Ｏｋｉセミコンダクタ株式会社 Semiconductor package and manufacturing method thereof
JP5259211B2 (en) * 2008-02-14 2013-08-07 ルネサスエレクトロニクス株式会社 Semiconductor device
US8183701B2 (en) * 2009-07-29 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Structure of stacking scatterometry based overlay marks for marks footprint reduction
US9000525B2 (en) * 2010-05-19 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for alignment marks
TWI433290B (en) * 2011-03-23 2014-04-01 Raydium Semiconductor Corp Semiconductor device
TW201240055A (en) * 2011-03-23 2012-10-01 Raydium Semiconductor Corp Semiconductor device
TWI466260B (en) * 2012-05-28 2014-12-21 Au Optronics Corp Alignment mark structure
KR20140017086A (en) 2012-07-30 2014-02-11 삼성디스플레이 주식회사 Integrated circuit and display device including thereof
TWI543328B (en) * 2012-08-01 2016-07-21 天鈺科技股份有限公司 Semiconductor device having alignment mark and display device using same
JP2015079848A (en) * 2013-10-17 2015-04-23 シナプティクス・ディスプレイ・デバイス株式会社 Semiconductor integrated circuit device for driving display device
KR102163358B1 (en) * 2014-07-21 2020-10-12 엘지디스플레이 주식회사 Display Device
CN104407742B (en) * 2014-12-12 2017-03-15 合肥鑫晟光电科技有限公司 Touch base plate and preparation method thereof, display device
CN110299345B (en) * 2018-03-22 2020-09-29 联华电子股份有限公司 Method for measuring mark and monitoring semiconductor manufacturing process
CN108878401B (en) * 2018-07-05 2020-04-21 长江存储科技有限责任公司 Optical alignment mark, optical positioning method and semiconductor device
KR20210026432A (en) * 2019-08-30 2021-03-10 에스케이하이닉스 주식회사 Semiconductor memory device
CN113725196A (en) * 2021-08-31 2021-11-30 长江存储科技有限责任公司 Semiconductor structure and forming method thereof
CN114713993B (en) * 2022-04-28 2023-05-30 江苏卡蒂罗网络科技有限公司 Adjustable CNC engraving light and shadow process

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JPS5494881A (en) * 1978-01-12 1979-07-26 Nippon Telegr & Teleph Corp <Ntt> Exposure method
JPS5890728A (en) * 1981-11-25 1983-05-30 Nippon Telegr & Teleph Corp <Ntt> Mark for alignment on semiconductor wafer and manufacture thereof
JPS6218714A (en) * 1985-07-18 1987-01-27 Nippon Telegr & Teleph Corp <Ntt> Forming method for alignment mark
JP2855868B2 (en) * 1990-03-12 1999-02-10 富士通株式会社 Laser trimming alignment mark, semiconductor device, and method of manufacturing semiconductor device
JP2650182B2 (en) 1995-01-17 1997-09-03 ソニー株式会社 Alignment mark, electronic device having the mark, and method of manufacturing the same
US5858854A (en) * 1996-10-16 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high contrast alignment marks
JP4192423B2 (en) * 1997-11-20 2008-12-10 株式会社ニコン Mark detection method, position detection apparatus, exposure method and apparatus, device manufacturing method, and device
JP2000182914A (en) * 1998-12-10 2000-06-30 Toshiba Corp Alignment mark
JP3566133B2 (en) * 1999-05-11 2004-09-15 セイコーインスツルメンツ株式会社 Manufacturing method of semiconductor device
JP3362717B2 (en) 1999-11-24 2003-01-07 日本電気株式会社 Semiconductor device and manufacturing method thereof
JP4504515B2 (en) * 2000-06-13 2010-07-14 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP2003142893A (en) * 2001-11-07 2003-05-16 Seiko Epson Corp Method and apparatus for manufacturing electro-optical panel as well as electro-optical panel, electro-optical apparatus and electronic apparatus
JP3492350B2 (en) * 2002-04-12 2004-02-03 新藤電子工業株式会社 Circuit board and method of manufacturing circuit board
KR100552455B1 (en) * 2002-09-20 2006-02-20 에이에스엠엘 네델란즈 비.브이. Alignment systems and methods for lithographic systems
US7271907B2 (en) * 2004-12-23 2007-09-18 Asml Netherlands B.V. Lithographic apparatus with two-dimensional alignment measurement arrangement and two-dimensional alignment measurement method

Also Published As

Publication number Publication date
TW200834866A (en) 2008-08-16
KR100928856B1 (en) 2009-11-30
CN101192596B (en) 2012-06-13
US20080121915A1 (en) 2008-05-29
US7825529B2 (en) 2010-11-02
KR20080048395A (en) 2008-06-02
JP5425363B2 (en) 2014-02-26
CN101192596A (en) 2008-06-04
JP2008135495A (en) 2008-06-12

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