TWI353655B - - Google Patents

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TWI353655B
TWI353655B TW096131059A TW96131059A TWI353655B TW I353655 B TWI353655 B TW I353655B TW 096131059 A TW096131059 A TW 096131059A TW 96131059 A TW96131059 A TW 96131059A TW I353655 B TWI353655 B TW I353655B
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Taiwan
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wafer
module
level packaging
packaging method
front side
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TW096131059A
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TW200910536A (en
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Priority to TW096131059A priority Critical patent/TW200910536A/zh
Priority to US11/987,147 priority patent/US20090051044A1/en
Publication of TW200910536A publication Critical patent/TW200910536A/zh
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Publication of TWI353655B publication Critical patent/TWI353655B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

I353655 。亥等晶片模組之間形成一具有一預定距離之第一寬度；提 ’、匕覆材料，其可填入έ亥等晶片模組之間之第一寬产^ ^成一包覆該晶片模組正面及側面之包覆層。 不發明亦提供一種依上述製造方法所製得之封蛛 係包括：一晶片模組，其具有一正面及一與該正面: 接之側面ϋ件區，其係成型於該正面上；以及 層其係包覆該元件區及該晶片之侧面。
本發明具有以下有益的效果：本發明提出之製造方 叙用具有延展性的貼膜，以使每—晶片模組相對移 ’步將每—晶片模組之側面顯露出來 ==整體性之包覆’故本製造方式所製作之晶 裝、，、。構能提供晶片模組更佳之保護。 、、、于 閲以2能更進—步瞭解本發明之特徵及技術内容，請灸 下有關本發明之詳細說明與附铁: 供參考盥智昍田* m + ”、、昉所附圖式僅提 ，w非用來對本發明加以限制者。 【實施方式】 方法，'該二!T:係提供-種封裝結構及其製造 -^ ^ μ "] ^11 (請同時參閱第三圖至第六圖/:、缺方法包括如下步驟 步驟（a )提供一片未切 中該未切割之模組晶们為一二^:曰圓1’此㈣ 組晶圓1具有-正面i i及_ :，、且’該未切割之模 與该正面相對之背面工 8 1353655 曰複數條切割道13以界定複數個 二 4之位置；亦即該等切割道13將該未切割之 杈:且晶圓1區分為複數個晶片模組丄4，該晶片模組14 線模組：如射頻模組等，但不以此為限；而該切 半導體製程方式成形於該未㈣之模組晶 夹士 /、不以此為限，·另外，該切割道1 3可成形於該 ί刀割之模組晶811之正面U，亦可成形於該未切割之 杈組晶圓1之背面1 2。 在該未切割之模組晶圓1上已有反覆利用半導 2程堆s形成複數個元件區！ 41於該未㈣之模組 :曰：上”面1 V每一元件區1 4 1係對應成形於每-:吳、、且4上’該元件區1 4 1係用以提供各種預定之 電性:^而該等半導體製程則包括微影製程、刪 :、二屬:_等等’上述技術均為一般半導體製程技 術’故不在此詳加說明；另外，該等元件區141亦可夢 蝴支術（SU*e删nting⑽她gy，耐）料 於该未切割之模組晶圓1上。 ^驟⑴貼附一可擴膠膜2於該未切割之模組晶圓 :面1 2 (請參閱第四及第四A圖）。該可擴膠膜2 材料，其具有一黏貼層’可將該未切割之模組 曰曰囫1之老面1 2貼附於該可擴膠膜2之黏貼層上。而該 可為半導體製程所使用之勝膜，例如晶刪 =0>_achFile，DAF) ’而該夥膜習知目的是以保 。刀割之拉組晶圓i不破片，即可固定未切割之模組晶 9 1353655 ΐ Μ/:莫组1 4飛濺切割；或是電子級膠帶⑶此 ape)’專Η應用於研磨、切割及運送時保護晶片模 4等製程。該電子級膠帶可於研磨時保護晶片模 受損傷及吸收研磨時的衝擊力確保晶片模組i、4不合破 裂，且於切割時能夠固定晶片模組1 4於膠帶上不會：生 晶片模組14流失的現象，並增進切割品質及拿取 組1 4的方便性。同時，也具有不易殘膠的特性及^曰、 同黏性的膠帶以應用於各種不同的工作物。在本發财， 相同之防止晶粒逸失功效，但本發明所 使用之可擴祕2必須能有擴張之效用 膜2受外力時’可向外延展擴張，以便進行;;::;跡 步驟。 ~ Γ 使(二)t著該等切割道13進行-切割步驟，以 使仏曰片杈組1 4相互分離；此步驟則是 :著:等切割道13進行切割以將每-晶片模組;4成 立之單元體；“藉由該可_膜2貼附於該未切 叙拉組晶圓1之背面i 2提供—固持之力量，每一
模組1 4仍然緊密貼附於該可擴膠膜2上，i R 形成一切且彼此之間則 該切割刀;之寬度見又，該切割後之切割寬度則略等於 步驟⑷擴張該可擴膠膜2，即施 擴張延伸，此步驟之目的在於利用該可二 、岡展使每-晶片模組1 4產生相對位移（如第 不）’即藉由該可擴膠膜2之延伸連帶使每一晶片 1^353655 板組1 4均向外移動而使每一晶片模組丄4之間之切割 道1 3擴寬形成該具有一預定距離之第一寬度1 $，且使 每一晶片模組1 4之側面1 4 2裸露（如第四A圖所示）， 且泫側面1 4 2係與該正面1 1相鄰接。 “接著步驟（e)提供-包覆材料，其可填人該等晶片 4之間之第-寬μ 5以形成—包覆該晶片模組 故 面1 1及側面1 42之包覆層1 6。該包覆材可 ί一向分子封裝材料，例如熱固性環氧樹脂，但並不以此 性環氧樹脂其硬化前為具有流動性黏稠流體 ΐ=剩，硬化後則形成交聯網目的固體。樹脂與 熱膨㈣數有極大的差異，因而在樹脂硬化後，冷 ::程:熱膨脹的差異，在樹脂與晶元兩者間可能產 著==致樹脂龜裂、晶元破裂、黏著分離或元件接 力，：:：二。^低封裝樹脂與晶片間的内應 (FiUer) S添加相具低熱祕錄的填充物 维或其他無機化合物粉粒... 2絲、、、威婦、石墨纖 —般知識，並非用以㈣，，上述僅為此包覆材料之 以模造方式（鳴⑻包^ _圍。且該包覆材料係 及側面1 4 2，藉此每—C組1 4之正面1 1 緊密之包覆而達成更佳之被該包覆層16 第五圖中省略該可擴勝膜2文果（如第五圖所示），但 另外’在步驟（e)之徭 具，沿著該等切割道後W —步包括提供-切割工 進仃切割步驟，以得到複數個正 1353655 面及側面均被包覆之晶片模W 4 (如第六圖所示）。而 該切割工具之寬度削、於該第-寬5，以免成形於該 晶片模組1 4之側面i 42之包覆層工6被該切割工且 一正面11及側面 該晶片模組封裝結 本發明從上述步驟後，則可以得到 1 4 2均被包覆的晶片模組封裝結構， 構包括： 丄及一與該正面期 曰曰片模組1 4，其具有 接之侧面142卜元件區141，其係成型於該正面i 1上’以及-包覆層i 6 ’其係包覆該元件區丄4丄及驾 晶片模組14之側面“2。同樣地，該元件區14 η ^復利用半導體製程堆疊而成，例如㈣、曝光、顯影考 製程；或是藉由表面黏著技術（surfaee mQuming⑽福 蕭）連結於該正面11±。，且上述晶片模組封裝結稽 則，該^切割之模組晶圓1經由切割製程所製造的；另外 該晶片模組1 4之背面1 2則可設有複數個連接點，且t| 等連接點係藉由穿設於該晶片模組1 4之穿孔與該元 區1 4 1電性連接，該連接點則是用以s成與 號的連接。 ,电給 紅上所述，本發明具有下列諸優點： 1 '具有較佳的保護作用，由於包覆層1 6本身即 具有保護晶 >；模組！ 4的功能，而本發明關用該 1 6包覆於該晶片模組1 4之側面丄4 2 ’使該側面“ 2不會裸露在外面，進而減少碰撞或其他移動時可能造成 12 的傷害。 2、 另一方面，本製裎估H 延展該可擴膠膜2的方式使每—a擴膠膜2的特性，以 位移’故本製程不需繁ί貞的製程=片模組1 4產生相對 片模組14的目的。 、^驟而達成整體包覆該晶 惟以上所述僅為本發明之較 發明之專縣護制，故舉凡運，非意欲褐限本 容所Α之a 運本發明說明書及圖式内 谷所為之荨效變化，均同理 圍内，合。 w於本發明之權利保護範 【圖式簡單說明】 第一圖係習知之封裝結構示意圖。 第二圖係本發明晶圓級封裝方法之流程圖。 第三圖係本發明未切割之模組晶圓之上視圖。 第四圖係本發明擴片步驟後之上視圖。 第四A圖係本發明擴#步驟後之側視圖。 第五圖係本發明使用—包覆材將晶片模組包覆之示意圖 第六圖係本發明可包覆晶片模組側面之封裝示意圖。 【主要元件符號說明】 1 2 —〜背面 1 4 —〜晶片模組 1———未切割之模組晶圓 1 1 —正面 13 ——切割道 13 1353655 14 1 ——元件區 1 4 2 —側面 15 ---第一寬度 16 —包覆層 16’ —包覆層 2----可擴膠膜 14

Claims (1)

11353655 十、申請專利範圍·· 1、一種晶圓級封裝方法，包括： (a)提供一未切割之模組晶圓 〜夕』白、俠貝 ·—⑼，其中該未切割之模组 =定義有複數條切割道以以複數個晶片模組之 (b)貼附一可擴膠膜於該未切割之模組 C c )沿著該笨切宝，丨；t » 圓 晶 /口著該等㈣這進行—第—㈣ =組相互分離，其中每-個分離的該晶片模組 此面一與遠正面鄰接之側面及一與該正面相對的 月面每5亥晶片模組之該正面設有一元件區，每— 組之該背面設有複數個連接點，該等連接點 “接Γ又於母一該晶片模組之穿孔與該元件區電 ⑷擴張該可擴膠膜’以於該等晶片之間形成 — 預定距離之第一寬度； ^ ⑷提供一包覆材料，其可填入該等晶片模組之間之寬 成—包覆每—該晶片模組之該元件區、該正面 及该側面之包覆層； ⑴提供-切割工具’沿著該等切割道進行第二切割步 驟’以得到複數個整體被該包覆層所 組，其中每-個該整體被該包覆層所包覆之晶= 程即可裸露該些連接點以用二 如申凊專利範圍第工-項所述之晶圓級封裝方法，其中 15 2 1353655 年月日修正替換頁100年03月16曰修正替換頁 ，1〇〇 ^.1-4- 在步驟（a)之前包括一反覆利用半導體製程堆疊形 成複數個元件區於該晶片模組之正面之步驟。 3、 如申請專利範圍第1項所述之晶圓級封裝方法，其中 在步驟（a)之前包括一利用表面黏著技術（surface mounting technology, SMT)成型複數個元件區於該 晶片核組之正面之步驟。 4、 如申請專利範圍第1項所述之晶圓級封裝方法，其中 在步驟（b)，該可擴膠膜為一高分子材料。 5、 如申請專利範圍第1項所述之晶圓級封裝方法，其中 在步驟（c)該等經切割後之晶片模組緊密貼附於該 可擴膠膜上。 6、 如申請專利範圍第1項所述之晶圓級封裝方法，其中 在步驟（d)，施加一外力使該可擴膠膜擴張，以使該 等晶片模組之間形成該具有一預定距離之第一寬度 且使每一晶片模組之側面裸露。 7、 如申請專利範圍第6項所述之晶圓級封裝方法，其中 在步驟（e )，該包覆材料係以模造方式（mo 1 d i ng ) 包覆每一晶片模組之正面及侧面。 8、 如申請專利範圍第1項所述之晶圓級封裝方法，其中 該切割工具之寬度小於該第一寬度。 16
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