TW200910536A - Wafer-level packaging method and structure - Google Patents
Wafer-level packaging method and structure Download PDFInfo
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- TW200910536A TW200910536A TW096131059A TW96131059A TW200910536A TW 200910536 A TW200910536 A TW 200910536A TW 096131059 A TW096131059 A TW 096131059A TW 96131059 A TW96131059 A TW 96131059A TW 200910536 A TW200910536 A TW 200910536A
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- wafer
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- item
- film
- packaging method
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 11
- 235000012431 wafers Nutrition 0.000 claims description 71
- 238000005520 cutting process Methods 0.000 claims description 19
- 238000005253 cladding Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 12
- 238000005516 engineering process Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000002861 polymer material Substances 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 abstract 1
- 238000009958 sewing Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 8
- 239000013078 crystal Substances 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- XTKDAFGWCDAMPY-UHFFFAOYSA-N azaperone Chemical compound C1=CC(F)=CC=C1C(=O)CCCN1CCN(C=2N=CC=CC=2)CC1 XTKDAFGWCDAMPY-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- IOVCWXUNBOPUCH-UHFFFAOYSA-M Nitrite anion Chemical compound [O-]N=O IOVCWXUNBOPUCH-UHFFFAOYSA-M 0.000 description 1
- 235000009827 Prunus armeniaca Nutrition 0.000 description 1
- 244000018633 Prunus armeniaca Species 0.000 description 1
- 241000270708 Testudinidae Species 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002484 inorganic compounds Chemical class 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 210000000496 pancreas Anatomy 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000009941 weaving Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
200910536 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一 構,尤指一種可包覆晶片 種晶圓級封裝方法及其封裝 模組側面之封裝結構。 結 【先前技術】 的功程技術能力不斷向上提升,半導體晶片 σ : 以致半導體晶片訊號的傳輸量逐漸增 著枯^亦隨之增加;進而使封裝技術必須隨 進而不斷提升。當f訊科技的發展日漸趨向於 工’丑/、的幵Μ ’尤其是筆記型電腦、行動通訊產品、數 ::機等逐漸成為現代人不可或缺的行動裝置 = 空間密度的特性,各模組的需求不僅 言口二:广穩疋的品質;如何縮个模組空間但仍保有 貝、、!生,甚至提昇更好的資料傳輸效能,便成為各 廢商的重要課題。 旦乂例如手機多媒體應用日漸增多,造成手機記憶體容 而f亦隨之增加,然而因手機輕薄短小的趨勢,所以記 =,片在Μ產品中能用的空間愈來愈小’故將手機記 讀 N〇RFlash、则D FlaSh、Low Pc>wer SRAM 及 Pseud〇 Μ堆宜封裝成一顆的多晶片封裝(Multi_Chip Paekagmg; Mcp)技術很普遍地應用在手機上,以 間達到輕薄短小的目的。 工 半‘體封裴主要是提供一個媒介,把矽晶片連接到印 200910536 刷電路板上,並保護器件免於受潮。這些年間,雖然這個 功能並未改變,但封裝技術已遠較從前複雜。由於晶 性能已經有所改善,封裝也肩貞起要將所產生的熱量安全 地排除掉的責任’並且讓這些熱量不會成為該 能的限制因素。 & 但習知的封裝結構如第一圖所示,晶片模組Η上方 之元件區141被一包覆材所包覆,該包覆材16,提供 學上之保護作用;但該包覆材16’卻沒有 包覆住该晶片模組i 4的侧面。晶片模紐i 4實際上是極 為脆弱_件’外來的應力或撞擊都有可能導致^片=組 1 4的損害,進而影響到整體的電氣特性。 、、 ▲緣是,本發明人有感上述缺失之可改善,提出 计合理且有效改善上述缺失之本發明。 又 【發明内容】 方法本ίΪ於提供一種封裝結構及其製造 較佳的保護性且成品也有更好的機械性f日日片核組 為了達成上述之㈣,本發明係提 ==:,—提供,割之= 有複數條切割道以界定複數個晶片 位
驟,以= 面;沿著該等切割道進行-W 吏料晶片模組相互分離;擴張該可擴膠膜,以於 200910536 該等晶片模組之間形成—具有—預歧離之第—寬度;提 七、包復材料,其可填入該等晶片模組之間之第一寬度以 升乂成包後1亥晶片模組正面及側面之包覆層。 .本發明亦提供-種依上述製造方法所製得之封裝結 冓係b括·曰曰片模組,其具有一正面及一與該正面鄰 接之側面;—元件區,其係成型於該正面上;以及-包覆 層,其係包覆該元件區及該晶片之侧面。 、本發明具有以下有益的效果:本發明提出之製造方 ,’使用具有延展性的貼膜,以使每—晶片模組相對移 勤,進一步將每-晶片模組之側面顯露出來,再以包霜材 料加以整體性之包覆,故本势迭方切制^材 设又不衣每方式所製作之晶片模組封 衣心構能提供晶片模組更佳之保護。 為使能更進一步瞭解本發明之特徵及技術内容,&來 :::鶴發明之詳細說明與附圖,然而所附圖式: ,、乡考人呪明用,並非用來對本發明加以限制者。 【實施方式】 Μ «1第二圖,本發明係提供—種封裝結構及 生 ,’該f造方法可包覆晶片模組裸露之惻到= =組及整體结構之功效,其製造方法包括二= (M同時參閱第三圖至第六圖): 力驟 步驟(a )提供一片未切割之模組晶圓丄,此麻 ^ίΐ' 1 ^Γ^®^? ^^^ ui具有一正面χ χ及一與該正面相對之背面i 200910536 曰以二:義有複數條切割道13以界定複數個 置;亦即該等切割道13將該未㈣^ ίΓΙ上 個晶片模組14,該晶片模組14 如射頻模組等,但不以此為限;而該切 以半導體製程方式成形於該未切割之模組晶 !=7以此為限;另外’該切割道13可成形於該 圓1之正面11 ’亦可成形於該未切割之 权組晶圓1之背面1 2。 此外,在該未切割之模組晶圓工上已有反覆利用半導 ^程堆疊形成複數個元件區丄4丄於該未切割之模組 晶圓1之正面]_ i ’每―元件區141係對應成形於每一 晶片模組14上’該元件區“1係用以提供各種預定之 :生功此而忒等半導體製程則包括微影製程、蝕刻製 私a屬沈積製程等等,上述技術均為—般半導體製程技 術,故不在此詳加說明;另外,該等元件區工4工亦可藉 由表面黏著技術(surfaee刪nting⑽⑽嫩謝)連^ 於該未切割之模組晶圓1上。 二驟(b )貼附—可擴膠膜2於該未切害彳之模組晶圓 1之^面12 (請參閱第四及第四A圖)。該可擴膠膜2 為-高分子材料,其具有—㈣層,可將該未切割之模組 晶圓1之背面12貼附於該可擴膠膜2之黏貼層上。而該 可擴膠膜2可為半導體製程所使用之_,例如晶粒钻貼 膠膜(DieAttadiFile,DAF),而該膠膜習知目的是以保 護未切割之模組晶圓i不破片,即可固定未切割之模組晶 200910536 圓1不使晶片模組i4飛濺切割;或是電子級膠 此
Tape),專Η應用於研磨、切割及
4等製程。該電子級膠帶可於研磨時保護晶片模^ ^損傷及吸收研磨日㈣衝擊力確保晶W ⑽切割時能夠固定晶片模組i 4於勝帶上不I;生皮 晶片杈組1 4流失的現象,並增進 & " 組14的方便性。同時,也且貝及拿取晶片模
了 也”有不易殘膠的特性及容士A 同黏性的膠帶以應用於各種不同的工作物。在本發=不 該可擴膠膜2亦有相同之防止晶粒逸失功效, 使用之可擴膠膜2必須能有垆苹夕4田 表月所 膜2受外力日士 用’亦即當該可擴膠 ’外延展擴張,以便進行本發明之下- 使』’Γ片等切割道13進行—切割步驟,以 使料曰曰片极w 4相互分離;此步驟則是以 3進行切割以將每-晶片陶4: 割之模組_之背面12提供 模組14仍然緊密貼附於該可擴膠膜2上,且彼此: 形成-切割後之切割寬度,該^ 該切割刀具之寬度。 傻之刀」見度則略等於 步驟(d)擴張該可擴膠膜 擴膝膜2向外擴張延伸,此:加—外力使該可 膜2之延展性,使每—;::=於利用該爾 四圖所示),即藉由該可、11 4產生相對位移(如第 «田〆了擴.胰2之延伸連帶使每—晶片 10 200910536 模組1 4均向外移動而使每一晶片模組丄4之間之切割 迢1 3擴寬形成該具有一預定距離之第—寬度丄5,且使 每-晶片模組1 4之側面1 4 2裸露(如第四A圖所示), 且該側面1 4 2係與該正面1 2相鄰接。 *接著步驟(e)提供-包覆材料,其可填人該等晶片 模組1 4之間之第一寬度1 5以拟士、 , _ 1^ 見没丄b以形成一包覆該晶片模組 上4:正面11及側面142之包覆層16。該包覆材可 :、、-问分子封裝材料,例如熱固性環氧樹脂,但並不以此 為限。而熱固性環氧樹脂其硬 或半膠化的膠體,硬化後則开^ ^、有〜動性黏稠流體 日p u 匕後則形成父聯網目的固體。樹脂盘 曰日片的熱膨脹係數有極大的差 、 入旳是異,因而在樹脂硬化後,冷 部收縮過程因熱膨脹的差里, 生内應力,導致樹脂龜曰:晶元兩者咖 者腳偏移或斷裂等。為了降妾 力,於樹脂配方中皆添加相杏晉 ^ (則㈦,如1化# :$具低熱膨脹係數的填充物 、 乳化矽粉、乳化鋁粉、氮化石朋粉、石黑織 維或其他無機化合物粉粒......等.卜、+ # '土、’ 一船知鴣 ^ , 、,上述僅為此包覆材料之 、,並非用以限制本案請求 以模造方式(,包覆每-晶片】… 及側面1 4 2,夢此备一曰犋、、且丄4之正面1 1 緊密之包覆嘯更佳物包覆層16 第五圖中省略該可擴膠膜2 /(如弟五圖所示)’但 具, 另外,在步驟(e) 沿著該等切割道1 3 之後更進一步包括提供一切割工 進行切割步驟,以得到複數個正 200910536 面及侧面均被包覆之晶片模組1 4 (如第六圖所示)。而 邊切割工具之寬度則小於該第一寬度丄5,以免成形於該 晶片模組1 4之側面1 4 2之包覆層i 6被該切割工具 所破壞。 本發明從上述步驟後,則可以得到一正面丄^及側面 1 4 2均被包覆的晶片模組封裝結構,該晶片模組封裝結 構包括: ° 一晶片模組14,其具有一正面丄丄及一與該正面鄰 接之侧面1 4 2 ; -元件區! 4工,其係成型於該正面丄 1上;以及一包覆層1 6,其係包覆該元件區1 4丄及哼 晶片模組14之側面142。同樣地,該元件區141^ 反覆利用半導體製程堆疊而成,例如㈣、曝光、顯影等 製程,或S藉由表面黏著技術(surfaee _nting 連結於該正面“上…且上述晶片模組封裝結構 則是该未切割之模組晶圓1經由切割製程所製造的;另外 該晶片模組1 4之背面1 2則可設有複數個連接點,且該 等連接點係藉由穿設於該晶片模組丄4之穿孔與該元^ 區1 4 1電性連接,該連接關是用以達成與外部 號的連接。 綜上所述,本發明具有下列諸優點: 1、具有較佳的保護作用,由於包覆fl6本身 具有保護晶片模組1 4的功能,而本發明則彻該包覆層 1 6包覆於該晶片模組χ 4之側面i 4 2,使: 2不會裸露在外面’進喊少碰撞或其他移動時可能迭成 12 200910536 的傷害。 2、另一方面,本製程使用可擴膠膜2的特性,以 延展該可擴膠膜2的方式使每一晶片模組丄4產生 =多,=製程不需繁_製程步驟而達成整體 片板組1 4的目的。 發明述僅為本發明之較佳實施例,非意欲侷限本 C護範圍’故舉凡運用本發明說明書及圖式内 二:=化,均同理皆包含於本發明之權利保護範 【圖式簡單說明】 弟—圖係習知之封裝結構示意圖 第二圖係本發明晶圓級封裝方法之流程圖。 第三圖係本發明未切割之模組晶圓之 第四圖係本發明則步驟後之上視圖。 第四Α圖係本發明擴片 弟五圖係本發明使用一 第六圖係本發明可包覆 步驟後之侧視圖。 包覆材將晶片模組包覆之示意圖。 晶片模組側面之封裝示意圖。 【主要元件符號說明】
一背面 〜晶片模組 1 —一—未切割之模組晶圓 1 1 — ~正面 1 3 ——切割道 13 200910536 1 4 1 — 一元件區 1 4 2 —側面 15---第一寬度 16 —一包覆層 16’--包覆層 2 ----可擴膠膜 14
Claims (1)
- 200910536 ‘、申請專利範園: 、一種封裝結構,係包括·· Η曰片模組,其具有一正面及一與該正面鄰接之側 面; —兀件區’其係成型於該正面上;以及 2 -包覆層’其係包覆該元件區及該晶片模組之側面。 3 、如申請專鄉JJJ第i項所述之封裝結構,其中該元件 區係反覆利用半導體製程堆疊而成。 '如申請糊範圍第:項所叙職結構, 區係利用表面黏著技f f /、节件 + , , j 者技術(surface moun1:i 4 technology,SMT)成型於該正面上 如申請專利範圍第丄項所述之封裝結構, 模組係為一未切割之模組晶圓經切割製朗製Γ =申請專利範圍第i項所述之封裝結構,其中該 模組進-步包括一與該正面相對之背面。 日日 如申請專利範圍第5項所述之封#姓 連接點設於該晶片模組之背面數個 月¢7且§亥專連接占车 7 穿設於該晶片模組之穿孔與該元件區電性連接 -種製造專利範圍第丄項所述 裝方法,包括: 丹心日日!&!、、及封 ⑷提供-未切割之模組晶圓’其包括 正面相對之背面,JL中兮丁_二A ,、或 界定複數個晶片模組之:置足義有複數條切割道以 ㈤貼附-可擴_於該未切割之模組㈣之背面; 15 200910536 (C)沿著該等切割道進行—切 組相互分離; 乂便口哀寻日日片模 ⑷,該可_膜,以於該等晶片之間形成一具有— 預疋距離之第—寬产. 、 购遍之間之寬 ^ ,, 復5亥曰曰片模組正面及侧面之包覆声。 ,晶圓級封裝其中 9成複數個元件二=::=程堆疊形 1°:=)範圍,7項所述^^ m〇unt; a之則包括—利用表面黏著技術(surface 曰曰片i 。1吼_成型複數個元件區於該 曰曰片权組之正面之步驟。 1 0φί申請專利範圍第7項所述之晶圓級封裝方法,苴 在步驟⑴,該可擴膠膜為—高分子材料。’、 中利範圍第7項所述之晶圓級封裝方法,其 該可擴該等經切割後之晶片模組緊密貼附於 中專利範圍第7項所述之晶圓級封裝方法’其 該等::广,施加一、外力使該可擴膠膜擴張,以使 Β曰5、、且之間形成该具有-預定距離之第一寬 度且使每一晶片模組之側面裸露。 3C利範圍第12項所述之晶圓級封裝方法, 、中在步驟⑷,該包覆材料係以模造方式㈤dlng) 16 200910536 匕復每-晶片模組之正面及側面。 4中=請專利麵第7項所述之晶圓 2步驟…之後更進一步包括提供且其 道進行切割步驟,以得到複數個正面及 側面均被包覆之晶片模組。 5其利範圍!14項所述之晶圓級封裝方法, /刀d工具之寬度小於該第一寬度。 17
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