1342730 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種可形成較高的凸塊，且可容易選擇 凸塊尚度之凸塊附著基板之製造方法。 【先前技術】 以下參照第7圖，來說明以往之銲錫凸塊的形成方法。 首先參照第7圖（A)’於基板1〇1的上面形成第i導 電圖案102,於下面形成帛2導電圖案1〇3,藉此來形成電 路基板100。 :接著參照第7圖⑻，於第1導電圖案102上裝載半 導體元件刚’採用金屬細線1〇5而電性連接第i導電圖 案102及半導體元件104。然後，以包覆半導體元件1〇4 ί金屬細、線105的方式’以密封樹月旨106來密封基板1011342730 IX. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing a bump-attached substrate which can form a high bump and can easily select a bump. [Prior Art] A method of forming a conventional solder bump will be described below with reference to Fig. 7. First, the i-th conductive pattern 102 is formed on the upper surface of the substrate 1A1 with reference to Fig. 7(A)', and the 帛2 conductive pattern 1?3 is formed on the lower surface, thereby forming the circuit substrate 100. Next, referring to Fig. 7 (8), the semiconductor element is mounted on the first conductive pattern 102, and the ith conductive pattern 102 and the semiconductor element 104 are electrically connected by the metal thin wires 1〇5. Then, the substrate 101 is sealed by a sealing method in such a manner as to cover the semiconductor element 1〇4 ί metal thin, the line 105.
參照第7圖（c )，以使第2導雷圖安！ . ^ i禾Z导電圖案103的所望部位 路出第2導電圖案1〇3的表面 λα . 式，开》成光阻（resist)107 的圖案。之後，在從光阻1〇7所露 1路3:5的第2導電圖幸1〇3 上，裝載銲錫球，藉由回銲而形成 '、 利文獻υ。 知而叫锡凸塊1〇8(參照專 [專利文獻1]日本特開2000_4〇764號八 【發明内容】 & a报 (發明所欲解決之課題） 然而，在上述銲錫凸塊 下的問題點。 108的形成方法中 會產生以 317238修正本 5 1342730 __ (4, ~~第94123677號專利申請^ | 99年12月20曰修正替換頁 由於係藉由銲錫來形成凸塊1 〇8，因此無法選擇凸塊 1〇8的高度。此外，在採用銲錫下，難以將凸塊的高度形 成為100 β m以上。 此外，由於係藉由裝載銲錫球並進行回銲而形成銲錫 .凸塊108，因此難以用良好精密度形成凸塊的高度。 此外，由於係藉由銲錫表形成凸塊，因此無法在安裝 基板上採用銲錫膏而與其他電路零件同時安裝。 本發明乃鑑於上述問題點而創作者，本發明之主要目 的㈣提供一種具備充分的凸塊高度之凸塊附著基板之製 造方法。 (解決課題之手段） 本發明之凸塊附著基板之製造方法的特徵為具備：準 備上面貼附有其厚度對應於凸塊高度之第丨導電箔，且下 面貼附有對應於配線厚度之第2導電羯之基板的製程，·形 成用以貫穿基板及第1導電箱及第2導電羯之貫穿孔的製 籲程；及於貫穿孔形成通孔錄覆，以電性連接第！導電箱及 第2導電箱，並將填充材填充於貫穿孔之製程；對除了形 成有貫穿孔之區域以外的第i導電須進行半姓刻，藉此形 成凸塊之製程；對除了形成有凸塊之區域以外的第雷 ^進行姓刻，藉此形成從凸塊延伸之導電線路之製程 藉由蝕刻第2導電箔而形成配線之製程。 /此外，本發明之凸塊附著基板之製造方法的特徵為， 形成用來被覆第1導電落及第2導電落的表面，且被覆* 穿孔的内壁之通孔鍍覆，而電性連接第！導電落及第 317238修正頁 6 ^42730 孔，覆及第之凸塊附者基板之製造方法的特徵為通 孔鑛覆及幻導電箱係以相同的金屬為材料 ㈣導電膜及第！導電絲形成凸塊。 :外，本發明之凸塊附著基板之製造方 错由選擇第】導電箱的厚度來選擇凸塊的高度。U為係 電後：二Γ明之凸塊附著基板之製造方法的特徵為導 電線路㈣來電性連接互相隔開設置^塊之間。 埴吞分：道本各明之凸塊附著基板之製造方法的特徵為， 填充材為導電材料。 此外’本發明之凸塊附著基板之製造方法的特徵 填充材為樹脂。 ” (發明之效果） 根據本發明之凸塊附著基板之製造方法，係藉由蝕刻 對f於凸塊高度之厚度之第1導電箔來形成凸塊。因此， :藉由所採用之第i導電的厚度，來選擇凸塊的高度。 藉=可提升凸塊的高度精確度。此外，可更容易地形成具 t付s規4。的尚度之凸塊，例如可形成較以往的輝錫凸塊 還向的ΰ?塊。 此外，根據本發明之凸塊附著基板之製造方法，係藉 由姓刻第1導㈣來形成凸塊。因此可提升凸塊的位置精 確度，而提供一種與安裝基板側的連接可靠度極高之凸塊 附著基板。此外，亦可任意決定凸塊的形狀。 此外，根據本發明之凸塊附著基板之製造方法，係藉 317238修正本 7 1342730 由對第1導電箔進行半蝕刻來形成凸塊，此外，係藉由對 形成有凸塊之區域以外的第1導電箔進行半蝕刻，來形成 冋度較凸塊還低之導電線路。因此，可藉由導電線路，來 電f生連接互相隔開而設置之凸塊之間。藉此，可使安裝基 板側的配線延伸於凸塊之間。 此外’根據本發明之凸塊附著基板之製造方法，係先 形成凸塊，然後配合所形成的凸塊之位置而形成其他配 線。因此，可提供一種凸塊的位置精確度極高之凸塊附著 基板。 此外，根據本發明之凸塊附著基板之製造方法，通孔 鍍覆係一體被覆第1導電箱及第2導電落的上面，以及貫 穿孔的内壁。因此，可確實地進行第i導電箔及第2導電 箔的電性連接。 此外，根據本發明之凸塊附著基板之製造方法，通孔 鑛覆及第1導電箔係以相同的金屬為材料。因此，可採用 相同的蝕刻劑來蝕刻通孔鍍覆及第丨導電箔，因此可簡化 製程。 【實施方式】 以下參照第1圖至第3圖，來說明本形態之電路基板 之製造方法。 首先參照第1圖（A )，係準備於上面貼附第i導電箔 12，且於下面貼附苐2導電箔13之基板u。Refer to Figure 7 (c) for the second guide to safe! The desired portion of the i-Z conductive pattern 103 is routed out of the surface λα of the second conductive pattern 1〇3, and is patterned as a resist 107. After that, solder balls were placed on the second conductive pattern of the 3:5, which was exposed from the photoresist 1〇7, and the solder balls were formed by reflowing. Known as the tin bump 1〇8 (refer to [Patent Document 1] Japanese Patent Laid-Open No. 2000_4〇764 No. 8 [Summary of the Invention] & a report (problem to be solved by the invention) However, under the above-mentioned solder bump Problem point. The formation method of 108 will be corrected by 317238. 5 1342730 __ (4, ~~ Patent Application No. 94123677 ^ | December 20, 1999 Correction Replacement Page Because the solder is used to form the bump 1 〇 8 Therefore, the height of the bumps 1 〇 8 cannot be selected. Further, it is difficult to form the height of the bumps to be 100 μm or more by using solder. Further, solder is formed by solder balls and reflow soldering. Since the block 108 is formed, it is difficult to form the height of the bump with good precision. Further, since the bump is formed by the solder watch, it is impossible to mount the solder on the mounting substrate simultaneously with other circuit components. The present invention is in view of the above problems. The main object of the present invention is to provide a method for manufacturing a bump-attached substrate having a sufficient bump height. (Means for Solving the Problem) Features of a method for manufacturing a bump-attached substrate of the present invention The method of preparing a substrate having a second conductive layer having a thickness corresponding to the height of the bump and having a substrate corresponding to the second conductive layer of the wiring thickness is attached thereto, and forming a substrate for the first conductive layer and the first conductive layer a punching process of the through hole of the box and the second conductive crucible; and forming a through hole in the through hole to electrically connect the first conductive box and the second conductive box, and filling the filling material into the through hole; The ith conductive material except the region in which the through hole is formed is subjected to a half-length engraving, thereby forming a process of the bump; the first ray of the region other than the region in which the bump is formed is formed, thereby forming an extension from the bump The process of forming a conductive line forms a wiring by etching the second conductive foil. Further, the method of manufacturing the bump-attached substrate of the present invention is characterized in that a surface for covering the first conductive drop and the second conductive drop is formed. And the through hole of the inner wall of the perforated * is plated, and the electrical connection is electrically connected to the hole 316238, and the manufacturing method of the coated substrate is the through hole ore. And the magic conduction box is the same The metal is a material (4) conductive film and the first conductive wire forms a bump. In addition, the manufacturing method of the bump-attached substrate of the present invention selects the height of the bump by selecting the thickness of the conductive box. U is after the electricity: The manufacturing method of the bump-attached substrate of the second embodiment is characterized in that the conductive lines (four) are electrically connected to each other and disposed between the blocks. 埴 分: The method for manufacturing the bump-attached substrate of the present invention is characterized in that the filler is Further, the characteristic filler of the method for producing a bump-attached substrate of the present invention is a resin. (Effect of the Invention) The method for manufacturing a bump-attached substrate according to the present invention is to etch a pair of bumps at a height of bumps. The first conductive foil having a thickness forms a bump. Therefore, the height of the bump is selected by the thickness of the ith conductive used. Borrow = can increase the height accuracy of the bumps. In addition, it is easier to form the s gauge 4. The bumps of the Shang, for example, can form a block that is more oriented than the conventional tin-copper bumps. Further, according to the method of manufacturing a bump-attached substrate of the present invention, the bumps are formed by the first guide (four). Therefore, the positional accuracy of the bump can be improved, and a bump-attached substrate having a highly reliable connection with the mounting substrate side can be provided. In addition, the shape of the bump can also be arbitrarily determined. Further, according to the method for manufacturing a bump-attached substrate of the present invention, the seventh conductive foil is half-etched to form a bump by 311238, and the bump is formed by a portion other than the region where the bump is formed. 1 The conductive foil is half-etched to form a conductive line having a lower twist than the bump. Therefore, the conductive lines can be used to electrically connect the bumps disposed apart from each other. Thereby, the wiring on the mounting substrate side can be extended between the bumps. Further, the manufacturing method of the bump-attached substrate according to the present invention is such that bumps are formed first, and then other wirings are formed in accordance with the positions of the formed bumps. Therefore, it is possible to provide a bump-attached substrate in which the positional accuracy of the bump is extremely high. Further, according to the method of manufacturing a bump-attached substrate of the present invention, the through-hole plating integrally covers the upper surface of the first conductive case and the second conductive pad, and the inner wall of the through hole. Therefore, the electrical connection between the ith conductive foil and the second conductive foil can be reliably performed. Further, according to the method of manufacturing a bump-attached substrate of the present invention, the via-hole coating and the first conductive foil are made of the same metal. Therefore, the same etchant can be used to etch the via plating and the second conductive foil, thereby simplifying the process. [Embodiment] Hereinafter, a method of manufacturing a circuit board of the present embodiment will be described with reference to Figs. 1 to 3 . First, referring to Fig. 1(A), the i-th conductive foil 12 is attached to the upper surface, and the substrate u of the second conductive foil 13 is attached to the lower surface.
關於基板11較理想為採用玻璃環氧基板或者是玻璃 聚亞醯胺基板，但可依情況而採隸基板、玻璃PPO 317238修正本 8 (P〇lypheny〗ene Oxide，聚苯醚）基板或是陶瓷基板等。 此:卜，亦可採用可撓性薄片、薄膜等。於本形態中，係採 用厚度約200//m之玻璃環氧基板。 關於第i導電洛12及第2導電辖13,只要為可進行 钱刻之金屬即可。於本形態中，係採用由銅所組成的金屬 導㈣12係採用膜厚約】75//m之銅落。此膜厚 係對應於後述的凸塊高度而決定。可採用最大約2心m =厗之導電落。因此’可藉由導電箱的厚度來決定凸塊 凸塊之高度精確度。此外，可更容易地形成 塊格的高度之凸塊’例如可形成較以往的銲錫凸 塊還商的凸塊。 於本形熊：電：13係採用對應配線高度之厚度的導電箔。 於本形態中，係將第2遙f β1 於配線厚度可藉由所安以^膜厚設為約18㈣。關 決定。糟由所文裝的電路元件的電流電容等而任意 12二l二(B)’形成用以貫穿基板U、第1導電箱 12及第2導電箔13之貫穿 ^ ^ 9 0 25mm之。在此，係形成直徑約 ，來昭孔14可採用此工作機而形成。 >…弟1圖（C )，形成用來祜 導電落13的表面，且破覆苐1導電羯12及第2 •導電膜15。藉由導電膜15^^14的内壁之通孔鑛覆之 .2糊13。於本形態 電生連導電荡12及第 銅鍍覆，乃藉由無電解錢覆法而形厚約~爪之 覆法或是無電解鍍覆法 -亦可糟由電解鍍 、_錢覆法之組合，來形成導電 317238修正本 9 獏15。 第94123677號專利申請案 _99年丨2月20日修正替桩$ 充材2第2圖（A) ’以填充材】6來填充貫穿孔】4。填 = 行填充1於填充㈣，例 1導“：材广係具備可確實地電性連接第 點。 Λ導電泊13，以及可確保電流電容等優 k，亦可採用樹脂等來做為填充材1 6。若採用樹月t ==漿等更容易填充貫穿孔。可藉由填充材二吏 可靠性。 ㈣為—樣平坦’而提升與安裝面的連接 參照第2圖（B )，可ϋ i a f, 了藉由+蝕刻而部分去除第1導電 :12及導電膜15,而形成凸塊…因此，第！導電箱12 具備一定的厚度而殘留。此外，於本形態中， ;第1導電箱12及導電膜15係由銅所組成，因此可採 ::二餘刻來形成凸塊18。再者，凸塊18包含形成有 貝牙 < 區域。在以濕式蝕刻來形成時，蝕刻劑主要係 為用氣化鐵（Ferric Chioride)或是氯化銅（c—ic ^blonde)。此外，係以導電箱所希望之部位從光阻露出的 狀態下，可浸餘關财，或是以此㈣劑進行嗔淋。 於本形態中’係以_劑進行喷淋，並以喷淋的時間來控 制蝕刻深度。 如此，以姓刻來形成凸塊18，藉此可提升凸塊的位置 精確度，而提供-種與安裝基板側的連接可靠性極高之凸 塊附著基板。此外，亦可任意決定凸塊的形狀。 凸塊18係由第1導電箱12及導電膜15的疊層體及填 317238修正頁 10 上342730 :材Μ所形成。本形態之凸幻8的高度 導電覆膜的膜厚下’大約為215// ^ 匕3後述的 于「入、马215/z m，最大可形成至 m。之後，以半蝕刻/ 謂以 〜风马#又潯之弟1導電箔】2，例如 -··， _至45/zm的膜厚。當然，亦可使 殘留為35_以下或^μ上之膜厚。$^白12Preferably, the substrate 11 is made of a glass epoxy substrate or a glass polyimide substrate, but the substrate or the glass PPO 317238 may be modified according to the situation, or the ene Oxide (polyphenylene ether) substrate may be modified or Ceramic substrate, etc. Therefore: a flexible sheet, a film, or the like can also be used. In the present embodiment, a glass epoxy substrate having a thickness of about 200 / / m is used. Regarding the i-th conductive 12 and the second conductive 13, it is only required to be a metal that can be engraved. In the present embodiment, a metal consisting of copper is used. (12) The 12 series is a copper drop having a film thickness of about 75/m. This film thickness is determined in accordance with the height of the bump to be described later. Conductive drops of up to about 2 cores m = 可采用 can be used. Therefore, the height accuracy of the bump bumps can be determined by the thickness of the conductive box. Further, the bumps of the height of the block can be formed more easily, for example, by forming bumps which are more expensive than the conventional solder bumps. In this shape bear: Electricity: 13 is a conductive foil with a thickness corresponding to the wiring height. In the present embodiment, the thickness of the second remote f β1 can be set to about 18 (four) by the thickness of the wiring. Off decision. The gap between the substrate U, the first conductive case 12, and the second conductive foil 13 is formed by the current capacitance and the like of the circuit element mounted thereon. Here, the diameter is formed so that the hole 14 can be formed by using the working machine. > Fig. 1 (C), the surface for forming the conductive pad 13 is formed, and the first conductive film 12 and the second conductive film 15 are broken. The paste is covered by a through hole of the inner wall of the conductive film 15^^14. In this form, the electro-optic connection 12 and the second copper plating are formed by the electroless gold coating method, the thickness of the coating method or the electroless plating method - or the electrolytic plating, the _ The combination of the methods to form the conductive 317238 correction of this 9 貘 15. Patent Application No. 94,123,677 _99, 丨February 20, revised replacement pile, $2, Fig. 2 (A) ‘filling hole* with filling material】4. Fill = Line Fill 1 in Fill (4), Example 1 Guide: "The material has a reliable electrical connection point. Λ Conductive Poor 13, and can ensure excellent current and capacitance, etc., can also be used as a filling Material 16. If it is easier to fill the through hole by using the tree t == slurry, etc., the reliability of the filler material can be obtained. (4) For the flatness of the flatness, the connection with the mounting surface is improved. Refer to Figure 2 (B). The first conductive material 12 and the conductive film 15 are partially removed by + etching to form a bump. Therefore, the first conductive case 12 has a certain thickness and remains. Further, in the present embodiment, 1 The conductive case 12 and the conductive film 15 are composed of copper, so that the bump 18 can be formed for two times. Further, the bump 18 includes a region formed with a beak tooth. It is formed by wet etching. When the etchant is mainly made of ferric iron (Ferric Chioride) or copper chloride (c-ic ^blonde), in addition, the desired portion of the conductive box is exposed from the photoresist, and the immersion is Wealth, or use this (four) agent to carry the dripping. In this form, 'spray with _ agent, and spray time The etch depth is controlled. Thus, the bumps 18 are formed by the surname, thereby improving the positional accuracy of the bumps, and providing a bump-attached substrate having extremely high connection reliability to the mounting substrate side. The shape of the bump is arbitrarily determined. The bump 18 is formed by the laminate of the first conductive case 12 and the conductive film 15 and the 342 730: 373 730: Μ 高度 高度 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Under the film thickness, 'approx. 215//^ 匕3 will be described later in the "input, horse 215 / zm, the maximum can be formed to m. After that, half-etched / said ~ Feng Ma #又浔之弟1 conductive foil] 2, for example, -··, _ to 45/zm film thickness. Of course, it is also possible to leave a film thickness of 35_ or less or ^μ.
#參照第2圖（C)’於凸塊18的上面形成層疊層，對 第1導電落12進行蝕刻’使基板u的上面暴露出。此蝕 刻可於露出基板U的階段停止，因而更容易進行控制钱 刻。之後電性分離第1導電箱12，而形成具備凸塊18之 第1導電圖案22。在此，凸塊18係包含形成有貫穿孔14 之區域。此外，於第1導電圖案22中，係包含與凸塊a 一體形成之導電線路。此導電線路係用來電性連接互相隔 開而設置之凸塊18之間。因此，可使安裝基板側之配線延 伸在凸塊間。 參照第3圖（A)’於第2導電箔13的表面使光阻圖 籲案化，並經由光阻來進行钱刻’藉此來形成第2導電圖案 23。第2導電圖案23係形成於安裝有電路元件等之面上之 配線’亦包含島部（Land )及鲜塾（Bonding Pad )等。 如此，由於先形成凸塊，然後配合所形成的凸塊之位 置而形成配線及導電線路，因此可提供凸塊的位置精確度 極高之凸塊附著基板。 參照第3圖（B )，係以導電覆膜24來被覆包含凸塊 18的上面之第1導電圖案22的上面。同樣地，以導電覆 膜24來被覆第2導電圖案23的上面。導電覆膜24係形成 11 3Π238修正本 1342730 =導電圖案表面的氧化。此導電覆膜⑷金 關於底層錢覆’亦包含在施加鎳鑛覆之後而 定^设之4層體等。導電覆膜24的厚度並無特別限 於本形'態中’係形成約為20 的膜厚。 金屬=之=2導電圖案23之未電性連接有電氣元件及 隻屬，，田線之部位，亦可形法 ^ 緣覆膜U。此_覆膜25 , ¥電圖案23的全面形成導電覆臈24之後，形 成於預定的部位。藉由以上 更^ 接荖夂昭楚4固 万式衣k出凸塊附著基板10。 …第4圖及第5圖，來詳細說明凸塊18。 了先參照顯示凸塊18附近的放大圖之第彳圖，來說明 ‘的厚度。在此，所謂的凸塊 ° 電落以的厚度^及導電膜 ^子度為广導 的厚声T：{々綠人 "子度1 2及導電覆膜24 的尽度T3之總合。於本形態卜由於如上述，丁乃 ^ T2為20_、了3為2〇心，因此凸塊高 215//m。因此藉 7门度马 N0及安而充分地使凸塊附著基板 著基板丨。的周端部,出時等極且裝心=分從ώ塊附 基板側突k電極乃必須具備從 裝。 、]了知用鲜錫貧並進行回銲來安 制。=二的=藉由第1導電…厚度峨 形成’若形成較厚的 電覆膜24係藉由鍍覆來 成本之故。此外，該厚花費較長時間及較高 塊附著基板之擊造‘二;、戶斤限制。若採用本形態之凸 … J可形成具備最大高度為 250# m 317238修正本 12 13,42730 之凸塊。 人田Γ外，以半鞋刻而形成較薄之第1導電落】四，係包 各1性連接形成有複數個之凸塊之間之導電線路 口此於安裝凸塊18於安裝基板之際， 側的配線延伸於凸埗夕門如丄 便女衷暴板 π…τ 間。在本形態尹，第1導電圖案 的尽度Τ4係形成約為35" m _£ 45" m。 圖（A)係顯示凸塊附著基板之凸塊形成面，第5 圖⑻係顯示凸塊附著基板之電路零件安裝面。在第^ 圖至第4圖中，係顯示第5圖⑷之χ-χ，線的剖面圖。 茶照第5圖⑷，導電線路26係電性連接凸塊1δΑ 及=塊18β。在此，係省略形成於第1導㈣案Μ的表面 膜及導電臈的圖示。於本形態中，貫穿孔係形成 ^又置有凸塊18之部位’各個凸塊18乃具備傳達電氣信 號之功能，但為了穩定地支#凸塊附著基板1()，亦可形成 虛擬凸塊等。此外，並不直接經由貫穿孔14來與第2導電 圖木22直接電性連接，而是藉由導電線路％來與其他凸 鬼18電f生連接’藉此’可形成進行電氣信號的傳達之凸 塊。亦即，藉由形成導電線路％，可容易地設計出凸塊18 的配置位置。此外’由於可形成多層配線基板，因此可達 到電路基板的小型化。 參照第5圖（B)，於第2導電圖案23安裝電氣零件 28電氣零件28A為電晶體、二極體、IC等半導體元件。 此外，亦可採用金屬細線29來進行電性連接。電氣愛件 勘為晶片電阻等電路元件。此外，係以被覆電氣料μ 317238修正本 13 13,42730 IK裝:樹脂或是襯套(C-g)來密封，藉此可形成 ^照，6圖，來說明其他形態之凸塊附著基板1〇之製 於本开“此’係以與上述製造方法的不同點為中心來說 於本㈣之凸塊附著基板1〇之製造 凸塊18於第1導雷网安9〇 i小逆接 薄的導電線路^圖木2’因此可形成厚度較凸塊18還 w首以 ==圖（A)，以填充材^來填充於貫穿孔 世 真充材I6B來填充於貫穿孔14B。貫穿孔14A及 貝穿孔14B係以與上述相 14A ^ - 之万法而同％形成。貫穿孔 塊18之預定部位，貫穿孔刚則 之材料，而填充材：L田 係採用與上述相同 要為不Λ為幻 ，、木用石貧。關於填充材16Β，只 ，為不X⑽m的影響，且可由不會對 浴劑加以去除之材料即可。 玍〜a之 參照第6圖（B)，對第】 半蝕刻，使第】導電箱12m I導電膜】5進仃 塊…此時，填充於貫穿孔1為預^厚度’藉此而形成凸 狀突出之構造。 6之填充材_，為形成柱 參照第6圖（c)’對第 進行蝕刻，藉此形成 自A弟2導U3 之後，以例如濃度約為及第2導電圖案… 性溶液來去除填充材⑽ 驗（咖加此㈣等鹼 導電膜η而設置，該導電；填充材_係用來保護 、係藉由用來形成導電圖案 317238修正本 14 13.42730 之银刻而設置於貫穿孔14的内壁。然後，在去除填充材 16B之後，可由填充材16A來填充貫穿孔i4B。如此，可 形成厚度較凸塊18還薄的導電線路26。藉此導電線路％， ：可於基板11的上面及下面，形成複雜且高密度之配線層。 . 而且，亦可在形成有凸塊18之區域未設置貫穿孔14, 而在從導電線路26延伸之部分形成凸塊丨8。 【圖式簡單說明】 第1圖（A )至（C )係用來說明本發明之凸塊附著基 板之製造方法的剖面圖。 第2圖（A )至（C )係用來說明本發明之凸塊附著基 板之製造方法的剖面圖。 第3圖（A )及（B )係用來說明本發明之凸塊附著基 板之製造方法的剖面圖。 第4圖係用來說明本發明之凸塊附著基板之製造方法 的剖面圖。 ,第5圖（A)及（B)係用來說明本發明之電路基板之 製造方法的上面圖及背面圖。 第6圖（A )至（C )係用來說明本發明之凸塊附著基 板之製造方法的剖面圖。 、第7圖（A )至（C )係用來說明以往的電路基板之製 造方法的圖式。 【主要元件符號說明】 10 凸塊附著基板 11、101基板 12 12A、12B第1導電羯13 第2導電箱 3Π238修正本 13/2730 14、14A 、：14Β貫穿孔 15 導電膜 1 6 ' 16 A 、16Β填充材 18 > 18Α、18Β 凸塊 .22 ' 102 第1導電圖案 23 ' 103 第2導電圖案 24 導電覆膜 ’，25 絕緣覆膜 26 導電線路 28 、 28A 、28Β電氣零件 29 金屬細線 100 電路基板 104 半導體元件 105 金屬細線 106 密封樹脂 107 光阻 108 銲錫凸塊 ΤΙ、T2、 Τ3、Τ4厚度 參 16 317238修正本# Referring to Fig. 2(C)', a laminated layer is formed on the upper surface of the bump 18, and the first conductive pad 12 is etched to expose the upper surface of the substrate u. This etch can be stopped at the stage of exposing the substrate U, making it easier to control the money. Thereafter, the first conductive case 12 is electrically separated, and the first conductive pattern 22 having the bumps 18 is formed. Here, the bump 18 includes a region in which the through hole 14 is formed. Further, in the first conductive pattern 22, a conductive line formed integrally with the bump a is included. The conductive traces are used to electrically connect between the bumps 18 that are spaced apart from one another. Therefore, the wiring on the mounting substrate side can be extended between the bumps. The photoresist pattern is patterned on the surface of the second conductive foil 13 with reference to Fig. 3(A)', and the second conductive pattern 23 is formed by the photoresist. The second conductive pattern 23 is formed on the surface on which the circuit element or the like is mounted, and includes a land portion, a bonding pad, and the like. Thus, since the bumps are formed first, and then the wiring and the conductive traces are formed in accordance with the positions of the formed bumps, it is possible to provide the bump-attached substrate having extremely high positional accuracy of the bumps. Referring to Fig. 3(B), the upper surface of the first conductive pattern 22 including the upper surface of the bump 18 is covered with a conductive film 24. Similarly, the upper surface of the second conductive pattern 23 is covered with the conductive film 24. The conductive film 24 is formed. 11 3 Π 238 Revision 1342730 = Oxidation of the surface of the conductive pattern. The conductive film (4) gold is also provided with a 4-layer body or the like which is fixed after application of nickel ore coating. The thickness of the conductive film 24 is not particularly limited to a film thickness of about 20 in the present state. The metal===2 conductive pattern 23 is electrically connected to the electrical component and only the part, and the part of the field line can also be shaped as the edge film U. After the conductive film 24 is formed over the entire surface of the film 25, the electric pattern 23 is formed at a predetermined portion. By the above, the substrate 10 is attached to the bumps. ... Figures 4 and 5 to illustrate the bumps 18 in detail. The thickness of ‘ is described first with reference to the second diagram showing an enlarged view of the vicinity of the bump 18. Here, the thickness of the bumps and the thickness of the conductive film are the thickness of the thick T: {々绿人"子度1 2 and the total thickness T3 of the conductive film 24 . In the present embodiment, as described above, the T2 is 20_ and the 3 is 2, so the bump height is 215/m. Therefore, the bumps are sufficiently adhered to the substrate by the seven-step horse N0 and the security. At the end of the circumference, the time is equipotential and the center of the heart = the slave electrode is attached to the side of the substrate. ,] knowing to use fresh tin and carry out reflow to secure. = = = by the first conductive ... thickness 峨 formed ' If a thicker electrical film 24 is formed by plating, the cost. In addition, the thicker takes a long time and the higher block attached substrate is hitting the second; If the protrusion of this form is used, a bump having a maximum height of 250# m 317238 and the 1213,427,030 can be formed. Outside the field, a thinner first conductive drop is formed by half-shoes. The four-way connection forms a conductive line between the plurality of bumps. The mounting bump 18 is mounted on the mounting substrate. On the other hand, the wiring on the side extends between the 埗 埗 埗 丄 女 女 女 女 女 。 。 τ τ τ 。. In the present embodiment, the first 导电4 of the first conductive pattern is formed to be approximately 35 " m _ £ 45 " m. Fig. (A) shows the bump forming surface of the bump-attached substrate, and Fig. 5(8) shows the circuit component mounting surface of the bump-attached substrate. In the first to fourth figures, a cross-sectional view of the line χ-χ of the fifth figure (4) is shown. In the fifth picture (4) of the tea photo, the conductive line 26 is electrically connected to the bump 1δΑ and the block 18β. Here, the illustration of the surface film and the conductive crucible formed in the first (4) case is omitted. In the present embodiment, the through holes are formed and the portions of the bumps 18 are provided. 'The respective bumps 18 have a function of transmitting electrical signals, but in order to stably support the bumps to attach the substrate 1 (), dummy bumps may be formed. Wait. In addition, it is not directly electrically connected to the second conductive pattern 22 via the through hole 14 , but is electrically connected to the other convex ghosts 18 by the conductive line %, thereby forming an electrical signal transmission. Bumps. That is, by forming the conductive line %, the arrangement position of the bumps 18 can be easily designed. Further, since a multilayer wiring board can be formed, the circuit board can be miniaturized. Referring to Fig. 5(B), electrical components are mounted on the second conductive pattern 23. The electrical component 28A is a semiconductor element such as a transistor, a diode, or an IC. In addition, the metal thin wires 29 can also be used for electrical connection. Electrical love parts are classified as circuit components such as chip resistors. In addition, it is sealed by the covered electrical material μ 317238 to modify the 13 13,42730 IK: resin or bushing (Cg), thereby forming a photo, and FIG. 6 to illustrate other forms of bump-attached substrate 1〇 The manufacturing "bumper" of the present invention is based on the difference from the above-described manufacturing method, and the bump 18 of the bump-attached substrate 1 of the present (4) is thinned by the first guide net. The conductive line ^Fig. 2' can thus be formed to have a thickness smaller than the bump 18 and the first head is replaced by the through hole 14B with the filling material ^1 filled with the through hole Kong I6B. The through hole 14A and the shell The perforation 14B is formed by the same method as the above-mentioned phase 14A ^ -. The predetermined portion of the through-hole block 18 penetrates the material of the hole, and the filler material: the L-field is the same as the above. For wood, the stone is 16 Β, only for the effect of not X (10) m, and can be used without removing the bath. 玍 ~ a reference to Figure 6 (B), the first half Etching, so that the first conductive box 12m I conductive film] 5 into the block... At this time, filling the through hole 1 is a pre-thickness' A structure in which a convex protrusion is formed. The filler _ of 6 is etched for forming a pillar with reference to FIG. 6(c)', thereby forming a pillar of U3 from the A, and then, for example, a concentration and a second conductive pattern. The solution is used to remove the filler (10) and is provided by adding the alkali conductive film η such as (4). The conductive material is used to protect the silver inscription by using the conductive pattern 317238 to modify the 14 13.42730. The inner wall of the through hole 14 is disposed. Then, after the filler 16B is removed, the through hole i4B can be filled with the filler 16A. Thus, the conductive line 26 having a thickness smaller than that of the bump 18 can be formed. A complicated and high-density wiring layer can be formed on the upper surface and the lower surface of the substrate 11. Further, the through hole 14 may not be provided in the region where the bump 18 is formed, and the bump may be formed in the portion extending from the conductive line 26. 8. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 (A) to (C) are cross-sectional views for explaining a method of manufacturing a bump-attached substrate of the present invention. Fig. 2 (A) to (C) are for explaining Cross section of the manufacturing method of the bump-attached substrate of the present invention Fig. 3 (A) and (B) are cross-sectional views for explaining a method of manufacturing the bump-attached substrate of the present invention. Fig. 4 is a cross-sectional view for explaining a method of manufacturing the bump-attached substrate of the present invention. Fig. 5 (A) and (B) are a top view and a rear view for explaining a method of manufacturing a circuit board of the present invention. Fig. 6 (A) to (C) are for explaining the bump of the present invention. Fig. 7(A) to Fig. 7(C) are diagrams for explaining a method of manufacturing a conventional circuit board. [Description of main components] 10 bump-attached substrate 11, 101 substrate 12 12A, 12B first conductive crucible 13 second conductive box 3Π238 correction 13/2730 14, 14A, 14Β through hole 15 conductive film 1 6 ' 16 A, 16 Β filler 18 > 18 Α, 18 凸 bump .22 ' 102 first conductive pattern 23' 103 second conductive pattern 24 conductive film ', 25 insulating film 26 conductive line 28, 28A, 28 Β electrical part 29 metal thin wire 100 circuit substrate 104 semiconductor element 105 metal thin wire 106 sealing resin 107 photoresist 108 solder bumps T, T2, Τ3, Τ 4 thickness reference 16 317238 amendment