JP2015177163A - Printed wiring board, method of manufacturing printed wiring board, package-on-package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board capable of forming the interconnection lines to an electronic component to be mounted with high density, while enhancing the mounting reliability.SOLUTION: A printed wiring board includes first high pads 58CP for connecting an upper substrate, and third low pads 48P for connecting an IC chip. Since the height of the third pad 48P (total thickness t4 of a second conductor layer 38, a second insulating layer 40, and a third conductor layer 48) is thinner than the height of the first pad 58CP (thickness t1 of the first conductor layer 58C), the second conductor layer and third conductor layer are thin. The second conductor layer and third conductor layer constituting the wiring of an IC chip can thereby be formed in fine pitch.

Description

The present invention relates to a printed wiring board having a pad for mounting an electronic component and a pad for mounting another printed wiring board (upper substrate), and a method for manufacturing the printed wiring board.

Patent document 1 is disclosing the method of arrange | positioning a metal post on the board | substrate connection pad of a printed wiring board.

JP 2009-164922 A

In Patent Document 1, a pad for mounting an electronic component and a wiring for the electronic component, and a pad for connecting the upper substrate and a wiring for the upper substrate are formed by the same process. For this reason, the wiring width for the electronic component and the wiring for the upper substrate cannot be greatly different from each other, and the wiring density for the electronic component that is required to be finer is increased. Is difficult.

The objective of this invention is providing the printed wiring board which can form the connection line to the electronic component to mount in high density, and can improve mounting reliability, and the manufacturing method of this printed wiring board.

A printed wiring board according to the present invention includes an insulating layer, a conductor layer formed on a surface of the insulating layer, and a via conductor that penetrates the insulating layer and connects the conductor layer of the insulating layer to the opposite surface. The conductor layers and the insulating layers are alternately stacked, and have a first insulating layer and a first conductor layer including a first pad formed on the first insulating layer. A second conductor layer including a second pad formed on the first insulating layer; a second insulating layer stacked on the second conductor layer; and formed on the second insulating layer. A wiring structure including a third conductor layer including a third pad and a via conductor that penetrates the second insulating layer and connects the second pad and the third conductor layer is provided. The position of the upper surface of the first pad is higher than the upper surface of the third pad.

According to the printed wiring board manufacturing method of the present invention, the conductor layers and the insulating layers are alternately built-up, the outermost insulating layer is formed, and the vias are formed on the outermost insulating layer. Forming one opening; forming a first seed layer on the outermost insulating layer and in the first opening; and on the outermost insulating layer, including a wiring structure forming position Forming a first plating resist in a portion where the first conductor layer is not formed, forming a via conductor in the first opening by electrolytic plating, and forming the first conductor layer; Stripping the plating resist, forming the second plating resist on the outermost insulating layer and not forming the second conductor layer, and forming the second conductor layer by electrolytic plating And removing the second plating resist And removing the first seed layer of the first conductor layer and the second conductor layer not formed, and having a second opening on the outermost insulating layer and the second conductor layer. Forming a second insulating layer; forming a second seed layer on the second insulating layer and in the second opening; and forming a third conductor layer on the previous second insulating layer. Forming a third plating resist at the site; and forming a via conductor in the second opening by electrolytic plating; and positioning the third conductor layer on the upper surface of the third conductor layer. Forming to be lower than the upper surface position of one conductor layer, peeling the third plating resist, and removing the second seed layer in a portion where the third conductor layer is not formed. Including.

In the printed wiring board of the present invention, the position of the upper surface of the first pad for connecting the upper substrate is higher than the upper surface of the third pad for mounting the electronic component. Since the total thickness of the second conductor layer, the second insulating layer, and the third conductor layer is thinner than the thickness of the first conductor layer, the second conductor layer and the third conductor layer constituting the wiring for the electronic component are thin. It can be formed in a fine pitch, and the wiring density for electronic components can be increased.

Further, in order to form the two conductor layers of the second conductor layer and the third conductor layer on the outermost interlayer insulating layer on which the first conductor layer is formed, a signal line for the electronic component to be mounted is configured. The second conductor layer and the third conductor layer can be formed with a fine pitch.

It is sectional drawing of the printed wiring board which concerns on 1st Embodiment of this invention. It is sectional drawing of the printed wiring board of 1st Embodiment. 3A is an enlarged cross-sectional view of the wiring structure surrounded by a broken line in FIG. 1, FIG. 3B is a plan view of the wiring structure, and FIG. It is a figure which expands and shows the site | part enclosed by the ellipse C in FIG. 3 (A). It is a manufacturing-process figure of the printed wiring board of 1st Embodiment. It is a manufacturing-process figure of the printed wiring board of 1st Embodiment. It is a manufacturing-process figure of the printed wiring board of 1st Embodiment. It is a manufacturing-process figure of the printed wiring board of 1st Embodiment. It is a manufacturing-process figure of the printed wiring board of 1st Embodiment. It is a manufacturing-process figure of the printed wiring board of 1st Embodiment. It is a top view of the printed wiring board before IC chip mounting. FIG. 11A is a plan view of the first conductor layer, FIG. 11B is a plan view of the third conductor layer, and FIG. 11C is a plan view of the second conductor layer. It is a manufacturing-process figure of the printed wiring board which concerns on the modification of 1st Embodiment. FIG. 13A is a cross-sectional view of the wiring structure of the printed wiring board according to the second embodiment, and FIG. 13B is a Y2-Y2 lateral view in FIG. 13A.

[First embodiment]
FIG. 1 shows a cross section of a printed wiring board 10 according to the first embodiment of the present invention. The printed wiring board 10 has a core substrate 80. The core substrate 80 includes an insulating substrate 80z having a first surface (F) and a second surface (S) opposite to the first surface, a conductor layer 84A on the first surface of the insulating substrate, and an insulating substrate. The conductor layer 84B on the second surface, the conductor layer 84A, and the through-hole conductor 86 connecting the conductor layer 84B are formed. The through-hole conductor 86 is formed by filling the through hole 81 formed in the insulating base material with a plating film.

The printed wiring board 10 further includes an upper buildup layer 55F on the first surface F of the core substrate 80. The upper buildup layer 50F includes an insulating layer (upper interlayer resin insulating layer) 50A formed on the first surface F of the core substrate 80, a conductive layer (upper conductive layer) 58A on the insulating layer 50A, and an insulating layer. Via conductor (upper via conductor) 60A that penetrates 50A and connects first conductor layer 84A and through-hole conductor 86 with conductor layer 58A. The upper buildup layer 50F further penetrates the insulating layer 50A, the insulating layer (outermost interlayer resin insulating layer) 50C on the conductive layer 58A, the conductive layer (uppermost conductive layer) 58C on the insulating layer 50C, and the insulating layer 50C. The via conductor (the uppermost via conductor) 60C connects the conductor layer 58A or the via conductor 60A and the conductor layer 58C.

The printed wiring board 10 further includes a lower buildup layer 55S on the second surface S of the core substrate 80. The lower buildup layer 50S includes an insulating layer (lower interlayer resin insulating layer) 50B formed on the second surface S of the core substrate 80 and a conductor layer (lower conductor layer) 58B on the insulating layer 50B. And a via conductor (lower via conductor) 60B passing through the insulating layer 50B and connecting the second conductor layer 84B and the through-hole conductor 86 to the conductor layer 58B. The lower buildup layer 50S further includes an insulating layer 50B, an insulating layer (lowermost interlayer resin insulating layer) 50D on the conductive layer 58B, a conductive layer (lowermost conductive layer) 58D on the insulating layer 50D, and an insulating layer 50D. Via conductor (bottom via conductor) 60D connecting conductor layer 58B and via conductor 60B and conductor layer 58D.

In FIG. 2, solder resist layers 70F and 70B are formed on the build-up layers 55F and 55S of the printed wiring board, the first IC chip 110A and the second IC chip 110B are mounted, and the upper substrate 210 on which the memory 290 is mounted is connected. It is sectional drawing which shows the state. FIG. 10 is a plan view of the printed wiring board 10 before mounting the IC chip and the upper substrate. The first IC chip 110A and the second IC chip 110B are processors. The bonding pad 218 of the upper substrate 210 and the memory 290 are connected by a bonding wire 216.

As shown in FIG. 2, a first conductor layer 58C is formed on a first interlayer resin insulation layer (outermost interlayer insulation layer) 50C. A solder resist layer 70F is formed on first interlayer resin insulation layer (50C), and opening (71F) of solder resist layer (70F) exposes first pad (58CP). The pads 214 of the upper substrate 210 are connected to the first pads 58CP through solder bumps 212. On the other hand, the pads 114 of the IC chips 110A and 110B are connected to the third pads 48P via the solder bumps 112. The first pad 58CP is included in the first conductor layer 58C. A solder resist layer 70S is formed on the second buildup layer 55S, and BGA bumps 76S are formed in the openings 71S of the solder resist layer 70S.

An opening 71FF is formed on the center side of the solder resist layer 70F, and the wiring structure 20 formed on the outermost interlayer insulating layer 50C is exposed. The wiring structure 20 constitutes signal lines of the first IC chip 110A and the second IC chip 110B.

FIG. 3A shows an enlarged view of the wiring structure 20 surrounded by a broken line in FIG. FIG. 3B is a plan view of the wiring structure 20, and an X1-X1 cross section in FIG. 3B corresponds to FIG. FIG. 3C is an enlarged view of a portion surrounded by an ellipse C in FIG.

The wiring structure 20 includes a second pad 38 and a second wiring line 36 formed on the outermost interlayer insulating layer 50C, and a second insulating layer 40 formed on the second pad 38 and the second wiring line 36. A third pad 48P and a third wiring line 46 formed on the second insulating layer 40, and a via conductor 48V that penetrates the second insulating layer 40 and connects the second pad 38 and the third pad 48P. Become.

The via conductor 48 </ b> V and the third wiring line 46 include a seed layer 42 and an electrolytic copper plating layer 44. The second pad 38 and the second wiring line 36 include a seed layer 32 and an electrolytic copper plating layer 34. The first conductor layer 58 </ b> C and the via conductor 60 </ b> C include the seed layer 32 and the electrolytic copper plating layer 49. The second pad 38, the second wiring line 36, the first conductor layer 58C, and the via conductor 60C have a common seed layer 32.

A plane layer 58AA that constitutes a part of the conductor layer 58A and is used as an earth layer is formed below the outermost interlayer insulating layer 50C on which the wiring structure 20 is formed. Due to the plane layer 58AA, the second wiring line 36 has a microstrip line structure. Thereby, the transmission speed of the 2nd wiring line 36 improves.

As shown in FIG. 3A, the height of the first pad 58CP on the upper surface of the first conductor layer 58C and the upper surface of the via conductor 60C, that is, the height from the upper surface of the interlayer insulating layer 50C to the first pad 58CP. The length t1 is 30 μm. On the other hand, the height t4 of the third pad 48P on the upper surface of the third conductor layer 46 and the upper surface of the via conductor 48V is 15 μm. A height t1 from the upper surface of the interlayer insulating layer 50C to the first pad 58CP is higher than a height t4 to the third pad 48P. Therefore, as shown in FIG. 2, in a state where the IC chips 110A and 110B are mounted on the third pad 48P having a low height on the wiring structure 20, the printed wiring board is formed on the first pad 58CP having a high height. Can be connected.

As shown in FIG. 3C, the height t2 of the second pad 38 and the second wiring line 36 is 2 to 3 μm. The height t3 of the via conductor 48V from the upper surface of the second insulating layer of the land 48P and the third wiring line 46 is 4 to 6 μm. As described above, the insulation distance d2 of the second insulating layer 40 is adjusted so that the height of the third pad 48P on the upper surface of the via conductor 48V is lower than the first pad 58CP on the upper surface of the via conductor 60C. Yes.

11A is a plan view of the first pad 58CP and the first wiring line 58CL constituting the first conductor layer 58C, and FIG. 11B is a third pad 48P constituting the third conductor layer 48. FIG. 11C is a plan view of the second pad 38P and the second wiring line 36 constituting the second conductor layer 38. FIG. As shown in FIG. 11A, the diameter a1 of the first pad 58CP is 70 to 300 μm, and the pitch p1 is 100 to 350 μm. The first wiring line 58CL has a line width L1 of 10 to 20 μm and a space width S1 of 10 to 20 μm. As shown in FIG. 11B, the diameter a3 of the third pad 48P is 20 to 30 μm, and the pitch p3 is 40 to 60 μm. The line width L3 of the third wiring line 46 is 3 μm, and the space width S3 is 3 μm. The minimum distance e3 between the third pad 48P and the wiring line 46 is 5 μm. As shown in FIG. 11C, the diameter a2 of the second pad 43P is 15 to 25 μm, and the pitch p2 is 40 to 60 μm. The second wiring line 36 has a line width L2 of 2 μm and a space width S2 of 2 μm. The minimum distance e2 between the second pad 38P and the wiring line 36 is 3 μm.

That is, the diameter a1 of the first pad 58CP> the diameter a3 of the third pad 48P> the diameter a2 of the second pad 88P, the pitch p1 of the first pad 58CP> the pitch p3 of the third pad 48P> the pitch of the second pad 88P. p2. Further, the line width L1 / space S1 of the first wiring line 58CL> line width L3 / space S3 of the third wiring line 46> line width L2 / space S2 of the second wiring line 36.

The third conductor layer 48 including the via conductor 48V and the third wiring line 46 and the second pad 38P are connected to the first pad 58CP constituting the first conductor layer 58C via the second wiring line 36.

In the printed wiring board of the first embodiment, the position of the upper surface of the first pad 58CP is higher than the position of the upper surface of the third pad 48P. Since the total thickness (t4) of the second conductor layer 38, the second insulating layer 40, and the third conductor layer 48 is thinner than the thickness (t1) of the first conductor layer 58C, the second conductor layer and the third conductor layer. Is thin. The second conductor layer 38 and the third conductor layer 48 constituting the wiring for an electronic component such as an IC chip can be formed thin and fine pitch, and the wiring density for the electronic component can be increased.

[Production Method of First Embodiment]
The printed wiring board of the first embodiment may be a printed wiring board having a core substrate or a coreless substrate. A printed wiring board having a core substrate and a manufacturing method thereof are disclosed in, for example, JP2007227512A. The coreless substrate and the manufacturing method thereof are disclosed in, for example, JP2005236244A.

A method for manufacturing the wiring structure 20 is shown in FIGS.
FIG. 4A shows a state in which the outermost resin insulation layer (first interlayer insulation layer) 50C shown in FIG. 1 is formed. A copper foil 47 is laminated on the outermost resin insulation layer 50C.

Via holes 50Ca are formed in the outermost resin insulation layer 50C by laser (FIG. 4B) After the copper foil is peeled off by etching, the seed layer 32 is formed by electroless plating or sputtering. It is formed on the resin insulating layer 50C and in the via opening 50Ca (FIG. 4C), and a plating resist 31 having a predetermined pattern is formed on the seed layer 32 (FIG. 4D).

By electrolytic copper plating, a copper plating layer 49 is formed in a portion where the plating resist 31 is not formed, and a via conductor 60C and a first conductor layer 58C are formed in the via opening 50Ca (FIG. 5A). . The via conductor 60 </ b> C and the first conductor layer 58 </ b> C include the seed layer 32 and the copper plating layer 49. The plating resist is peeled off (FIG. 5B). The positive plating resist solution 33α is applied on the seed layer 32 and the first conductor layer without removing the seed layer 32 (FIG. 5C).

Through the exposure / development process, a plating resist 33 is formed (FIG. 6A). The pattern of the resist 33 forms a line width L2: 2 μm and a space width S2: 2 μm of the second wiring line shown in FIG. A copper plating layer 34 is formed on a portion where the plating resist 33 is not formed, and a second conductor layer 38 including the second pad 38P and the second wiring line 36 is formed (FIG. 6B). The plating resist is peeled off (FIG. 6C).

The seed layer 32 where the first conductor layer 58C and the second conductor layer 38 are not formed is removed (FIG. 7A). A photosensitive resist solution 40α is applied onto the outermost interlayer resin insulation layer 50C (FIG. 7B), and a second insulation layer 40 having a via opening 40a is formed by exposure and development (FIG. 7B). C)).

A seed layer 42 is formed on the second insulating layer 40 and in the via opening 40a (FIG. 8A). A positive plating resist solution 43α is applied on the seed layer 42 (FIG. 8B). Through the exposure / development process, a plating resist 43 is formed (FIG. 8C). A pattern of the plating resist 43 is formed. The pattern of the plating resist 43 forms a line width L3: 3 μm and a space width S3: 3 μm of the third wiring line shown in FIG.

A copper plating film 44 is formed on a portion where the plating resist 43 is not formed, and a third conductor layer 48 including a via conductor 48V having a third pad 48P on the upper surface and a third wiring line 46 is formed (FIG. 9A). ). The plating resist is peeled off (FIG. 9B). The seed layer 42 where the third conductor layer 48 is not formed is removed (FIG. 9C). The wiring structure 20 shown in FIG. 1 is completed.

As shown in FIG. 2, a solder resist layer 70F having an opening 71F and an opening 71FF is formed on the buildup layer 55F, and a solder resist layer 70S having an opening 71S is formed on the buildup layer 55S. BGA bumps 76S are formed in the openings 71S of the solder resist layer 70S. A protective film 72 can be formed in the opening 71S. IC chips 110A and 110B are mounted on a printed wiring board. The IC chip terminals 114 are connected to the third pads 48CP of the printed wiring board via the first solder bumps 112. An upper substrate 210 is mounted. The pads 214 of the upper substrate 210 are connected to the first pads 58CP of the printed wiring board via the solder bumps 212. It is also possible to fill a sealing resin between the upper substrate 210 and the printed wiring board.

The upper surface of the first pad 58CP is located higher than the upper surface of the third pad 48P. For this reason, the upper substrate 210 does not interfere with the IC chip, and the connection reliability with the upper substrate 210 mounted on the first pad is high. The total thickness (t4) of the second conductor layer 38, the second insulating layer 40, and the third conductor layer 48 is thinner than the thickness (t1) of the first conductor layer 58C (see FIG. 3A). The second conductor layer and the third conductor layer are thin, and the second conductor layer and the third conductor layer constituting the wiring for the IC chip can be formed at a fine pitch.

In the printed wiring board according to the first embodiment, the second conductor layer and the third conductor layer are formed as a build-up layer of the printed wiring board, so that the formation is easy and the reliability is high.

[Modification of the first embodiment]
FIG. 12 shows a method for manufacturing the printed wiring board 10 according to a modification of the first embodiment of the present invention.
FIG. 12A shows a state in which the outermost resin insulating layer (first interlayer insulating layer) 50C shown in FIG. 1 is formed. Copper foil is not laminated on the outermost resin insulation layer 50C. The surface of the resin insulating layer 50C is not roughened.

Via openings 50Ca are formed in the outermost resin insulation layer 50C by laser (FIG. 12B). The seed layer 32b is formed on the outermost resin insulation layer 50C by electroless Cu plating or Ti / Cu sputtering. It is formed in the via opening 50Ca (FIG. 12C) The subsequent steps are the same as those in the first embodiment shown in FIGS.

[Second Embodiment]
FIG. 13A is a cross-sectional view of the wiring structure of the printed wiring board according to the second embodiment, and FIG. 13B is a Y2-Y2 lateral view in FIG. 13A.
In the printed wiring board of the second embodiment, as a pad for connection to the IC chip 110, a third pad 48P similar to the first embodiment, the same height (t4) as the third pad 48P, and a large diameter A fourth pad 48PL is formed. The fourth pad 48PL is connected to the pad 114L of the IC chip via the solder bump 112L. The third pad 48P and the fourth pad 48PL are connected via the second wiring line 36. A first pad 58CP is disposed outside the fourth pad 48PL, and the upper substrate 210 is mounted on the printed wiring board 10 via the first pad 58CP. The fourth pad 48PL and the first pad 58CP are connected via a fourth wiring line 48L formed simultaneously with the fourth pad 48PL.

DESCRIPTION OF SYMBOLS 10 Printed wiring board 20 Wiring structure 36 2nd wiring line 38 2nd wiring layer 38P 2nd pad 40 2nd insulating layer 46 3rd wiring line 48 3rd wiring layer 48P 3rd pad 50C 1st interlayer resin insulating layer 58C 1st 1 conductor layer 58CP 1st pad

Claims (17)

An insulating layer;
A conductor layer formed on the surface of the insulating layer;
A via conductor that penetrates through the insulating layer and connects the conductor layer of the insulating layer to the opposite surface, the conductor layer and the insulating layer are alternately stacked, and the first insulating layer and the first insulating layer A printed wiring board having a first conductor layer including a first pad formed on the layer,
A second conductor layer including a second pad formed on the first insulating layer;
A second insulating layer laminated on the second conductor layer;
A third conductor layer including a third pad formed on the second insulating layer;
A wiring structure comprising a via conductor penetrating the second insulating layer and connecting the second pad and the third conductor layer;
The position of the upper surface of the first pad is higher than the upper surface of the third pad. The printed wiring board according to claim 1,
The first insulating layer is an outermost interlayer insulating layer. The printed wiring board according to claim 1,
The second conductor layer of the wiring structure is connected to the first conductor layer. The printed wiring board according to claim 1,
The first conductor layer and the second conductor layer have the same seed layer. The printed wiring board according to claim 4,
The seed layer is composed of an electroless Cu plating layer or a Ti / Cu layer formed by sputtering. The printed wiring board according to claim 1,
The second insulating layer is made of a photosensitive resin. The printed wiring board according to claim 1,
A plane layer is formed immediately below the wiring structure and below the first insulating layer. The printed wiring board according to claim 7,
The plane layer is a ground layer. The printed wiring board according to claim 1,
The third pad is for IC chip mounting,
The first pad is for connecting another printed wiring board. The printed wiring board according to claim 1,
The first pad is disposed on the outer peripheral side of the printed wiring board,
The third pad is disposed on the inner peripheral side of the first pad. The printed wiring board according to claim 1,
The third conductor layer includes a wiring, and an insulation distance between the wiring and the third pad is wider than an insulation distance between the wirings. The printed wiring board according to claim 1,
The third pad is thicker than the second pad. The printed wiring board according to claim 1,
The wiring width of the second conductor layer is narrower than the wiring width of the third conductor layer. The printed wiring board according to claim 13,
The wiring width of the third conductor layer is narrower than the wiring width of the first conductor layer. The printed wiring board according to claim 1,
The pitch of the first pad is larger than the pitch with the third pad. A method of manufacturing a printed wiring board,
Alternately building up and laminating conductor layers and insulating layers;
Forming an outermost insulating layer;
Forming a first opening for a via on the outermost insulating layer;
Forming a first seed layer on the outermost insulating layer and in the first opening;
Forming a first plating resist on a non-formation portion of the first conductor layer on the outermost insulating layer and including a wiring structure forming position;
Forming a via conductor in the first opening by electrolytic plating and forming the first conductor layer;
Peeling off the first plating resist;
Forming a second plating resist on the outermost insulating layer and in a portion where the second conductor layer is not formed;
Forming the second conductor layer by electrolytic plating;
Peeling off the second plating resist;
Removing the first seed layer in the non-formation part of the first conductor layer and the second conductor layer;
Forming a second insulating layer having a second opening on the outermost insulating layer and the second conductor layer;
Forming a second seed layer on the second insulating layer and in the second opening;
Forming a third plating resist on the second insulating layer before forming a third conductor layer in a non-formation portion;
Via plating is formed in the second opening by electrolytic plating, and the position of the upper surface of the third conductor layer is lower than the position of the upper surface of the first conductor layer. Forming,
Peeling off the third plating resist;
Removing the second seed layer in a portion where the third conductor layer is not formed. A package-on-package comprising a lower substrate on which an IC chip is mounted and an upper substrate mounted on the lower substrate,
The lower substrate includes an uppermost interlayer resin insulation layer,
A third pad for connecting an IC chip formed on the uppermost interlayer resin insulation layer and formed on the center side of the lower substrate; a first pad for connecting an upper substrate formed on the outer peripheral side;
A solder resist layer formed on the uppermost interlayer resin insulation layer and having a first opening exposing the first pad and a second opening exposing the third pad;
A solder bump formed on the first pad and connected to the pad of the upper substrate;
An IC chip including a first bump and mounted on the third pad via the first bump;
A wiring structure formed on the uppermost interlayer resin insulation layer and in the second opening of the solder resist layer;
The wiring structure is
A second conductor layer including a second pad formed on the uppermost interlayer resin insulation layer;
A second insulating layer laminated on the second conductor layer;
A third conductor layer including the third pad formed on the second insulating layer;
A via conductor that penetrates through the second insulating layer and connects the second pad and the third conductor layer.

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