1342460 第94102845號之專利說明書修正本 修正日期：99.8.30 九、發明說明： 【發明所屬之技術領域】 本發明是關於形成有對應施加電壓的通道，電流 係通過該通道内的電流通過區域而流動的薄膜電晶體 及使用薄膜電晶體的液晶顯示裝置。 【先前技術】 在CRT顯示器中進步緩慢的顯示器的高解像度化 隨者以液晶為首的新技術的導入而有了飛躍的進步。 即液晶顯示裝置藉由施以微細加工與CRT顯示器比較 ，高精細化較容易。 液晶顯示裝置已知有使用作為開關元件的 TFT(Thin Film Transistor:薄膜電晶體）之主動矩陣 (active matrix)方式的液晶顯示裝置。此主動矩陣方式 的液晶顯示裝置係在配設掃描線與信號線成矩陣狀， 於在其交點配設有薄膜電晶體的TFT陣列基板與和該 基板隔著預定的間隔配置的對向基板之間封入液晶材 料，藉由薄膜電晶體控制給予此液晶材料的電壓，利 用液晶的光電效應而能顯示。薄膜電晶體的開/關 (on/off)係藉由被掃描線與信號線給予的電位控制，相 關的掃描線以及信號線分別連接於驅動電路。 II於液晶顯示裝置的近年來的高精細化的傾向， 伴隨著像素的增大，掃描線以及信號線的條數增大， 驅動IC的數目也有增大的傾向。相關的傾向因會招致 製造成本的上升以及良率的惡化，故對屬於不同複數 9109 A-A3 5183TWF1 (20100830) 1342460 修·^ 日期：99.8.30 第94102845號之專利說明書修正本 列的像素電極群，#由以一條信號線以時分割給予電 位降低信號線的條數以及連接於信號線的驅動1C的 數目之構造（在以下中’稱為[多重像 ^ 1豕京構造])被提出（ 例如參照專利文獻1 )。 第10圖係針對具有多重I素構造的液晶顯示裝置 所具備的丁F丁陣列基板之構造的—例所示的等價電路 圖。如第10圖所示，例如像素電極A1係經由第一薄 膜電晶體以及第二薄膜電晶體M2連接於掃描線 • Gn+1以及掃描線Gn + 2，由信號線Dm供給顯示信號 •。而且’像素電極B1係經由第三薄膜電晶體M3連接 . 於掃描線Gn+ 1，同樣地由信號線供給顯示信號。 其他的像素電極也藉由與同樣的電路構造連接，例如 由同一 t號線D m依次供給顯示信號至像素電極aI、 B 1、C 1、D 1，以顯示圖像。藉由採用相關的構造如第 1 0圖所示’因可降低信號線的條數，進而可降低連接 .φ於信號線的驅動1c的數目，故具有可降低製造成本等 的優點。 此外’在第1 0圖所示的配線構造以外，在日本特 開平6- 1 48680號公報、日本特開平丨U837號公報、 曰本特開平· 5-265 045號公報、日本特開平5_ 1 883 95 號公報、日本特開平5-3 03〗Μ號公報等中也揭示針對 使用多重像素構造的液晶顯示裝置。 [專利文獻1 ]日本特開2 0 0 2 - 1 9 6 3 5 7號公報 【發明内容】 9109A-A35183TWF1(20100830) 1342460 第94102845號之專利說明書修正本 修正曰期：99.8.30 但是，一般薄膜電晶體有起因於層間絕緣層 (Interlayer dielectric layer)的缺陷等使各電極間短路 之虞，特別是在使用上述多重像素構造的液晶顯示裝 置中，對於形成薄膜電晶體的電極之中特定的電極間 短路的情形成為大的問題。以下針對相關的問題詳細 地說明。 也如第1 0圖所示的，使用多重像素構造的液晶顯 示裝置所具備的第二薄膜電晶體 M2係具有源電極 (source electrode)與掃描線 Gn + 2 電性連接，閘電極 (gate electrode)與掃描線Gn+Ι電性連接的構成。因此 ，對於第二薄膜電晶體M2的閘極/源極間短路的情形 ，本來需獨立進行電位供給的複數條掃描線間變成短 路，對圖像顯示功能發生重大的障礙。因此，以對應 排列成行列狀的像素電極形成多數的第二薄膜電晶體 M2之中即使只有一個在閘極/源極間發生短路的圖像 顯示裝置作為製品出貨並不妥當。其結果，使用習知 的多重像素構造的液晶顯示裝置與不具有相當於第二 薄膜電晶體M2的構成要素之一般的液晶顯示裝置比 較，有信號線的條數降低但製造良率卻無法提高這種 課題。 -、 另一方面針對第二薄膜電晶體M2，在與第一薄膜 電晶體Μ 1的閘電極電性連接的汲電極與閘電極之間 會發生的短路與閘極/源極間的短路比較，嚴重度較低 。即理想上閘極/汲極間的短路不發生較佳係理所當然 9) 09Α-Α35183TWF1 (20100830) 1342460 修正日期：99.8.30 第94102845號之專利說明書修正本 ，但萬一發生短路也僅對應該情形的顯示像素的顯示 特性劣化，不會給予多數存在的其他像素的顯示特性 不良影響。因此，假設在閘極/汲極間發生短路，對於 多數存在的第二薄膜電晶體M2的一少部分的情形， 所發生的問題係目視確認極為固難的程度的輕微，一 般作為製品出貨不致於造成問題。 如此，薄膜電晶體等的半導體元件係對於在電極 間發生的短路的重要度產生差異的情形經常存在，即 φ 使是在液晶顯示裝置所使用的情形以外，在預先防止 . 短路的重要度高的特定電極間中也需要降低電性短路 的發生機率之薄膜電晶體。 而且，作為降低電性短路的發生機率之構造的情 形使薄膜電晶體的電特性下降也不佳。例如雖然藉由 提高層間絕緣膜（閘極絕緣層等）的膜厚可降低短路發 生機率，但採用相關構造因會重新發生可通過通道 | ( c h a η n e 1)之電流量減少這種問題，故不妥當。 本發明乃鑒於上述所進行的創作，其目的為實現 一邊抑制電特性的下降，一邊抑制特定電極間的短路 發生之薄膜電晶體及使用薄膜電晶體的液晶顯示裝置 〇 · 為了解決上述課題達成目的，與申請專利範圍第1 項有關的薄膜電晶體，係形成有依照施加電壓的通道 ，電流通過前述通道内的電流通過區域而流動，其特 徵包含：與前述電流通過區域的接觸側端部具有第一 9109A-A35183TWF1(20100830) 1342460 第94102845號之專利說明書修正本 修正日期：99.8.30 ^ c 長度的寬度之第一電極；與前述電流通過區域的接觸 側端部具有比前述第一長度還大，使在與前述第一電 極之間產生的電流通過區域寬度的有效值為預定值而 決定的第二長度的寬度之第二電極；在通道形成時被 施加預定電壓的第三電極；配置於前述第一電極、前 述第二電極以及前述第三電極之間，當前述第三電極 被施加預定電壓時形成通道之通道形成區域。 如果依照此申請專利範圍第1項的發明，藉由具 有第二電極的接觸側端部的寬度比第一電極的接觸側 端部的寬度還大的構成，可使第一電極與第三電極之 間的短路發生機率比第二電極與第三電極之間的短路 發生機率還降低。而且，如果依照申請專利範圍第1 項的發明，關於第二電極的寬度，不光是比第一電極 的寬度還大而已，也使在第一電極與第二電極之間所 產生的電流通過區域寬度的有效值為預定值而決定。 因此，儘管使接觸側端部的寬度變化，也能維待通過 第一電極與第二電極之間的電流量於所希望的值，可 一邊抑制電特性的下降，一邊降低特定電極間（第一電 極與第三電極之間）的短路發生機率。 -而且，與申請專利範圍第2項有關的薄膜電晶體 ，係在上述發明中前述第三電極係與發生預定的電位 變動的第一配線電性連接，前述第一電極係與電位和 前述第一配線個別獨立變動的第二配線電性連接。 如果依照此申請專利範圍第2項的發明，因採用 9109 A-A3 5183TWF1 (20100830) -10. 1342460 修正日期：99.8.30 第94102845號之專利說明書修正本 降低第一電極與第三電極之間的短路發生機率的構造 ，故可抑制電位互相個別獨立變動的第一配線與第二 配線之間的電性短路的發生，可實現不會損及第一配 線以及第二配線的功能之薄膜電晶體。 而且，與申請專利範圍第3項有關的薄膜電晶體 ，係在上述發明中前述第一電極、前述第二電極以及 前述第三電極的至少一個具有彎·曲形狀。 而且，與申請專利範圍第4項有關的薄膜電晶體， 參 係在上述發明中前述第二電極具有口字形，前述第一 . 電極係被配置，俾接觸側端部位於藉由前述3字形形 成的區域内。 而且，與申請專利範圍第5項有關的薄膜電晶體， 係在上述發明中前述第三電極具有3字形。 而且，與申請專利範圍第6項有關的薄膜電晶體 ，係在上述發明中前述第一電極在通道形成時被供給 φ 比前述第二電極還高的電位。 而且 > 與申請專利範圍第7項有關的液晶顯不裝 置’係利用液晶材料的光電效應進行圖像顯不’其特 徵為包含有如下之陣列基板：該陣列基板具備：信號線 ，傳送對應顯示色調（tone)的顯示信號；第一像素電極 以及第二像素電極，經由該信號線供給該顯示信號； 第一開關元件，控制該第一像素電極與該信號線之間 的導通狀態；第二開關元件，係由包含如下構成之用 以控制該第一開關元件之驅動狀態的薄膜電晶體所形 9109A-A35183TWF1 (20100830) 修正日期：99.8.30 於通道内的電流通過區域接觸 長度的寬度；第二電極，與該 ，並且其與該電流通過區域接 該第一長度還大的第二長度的 通道形成時被施加預定電壓； 該第一電極、該第二電極以及 第三電極被施加預定電壓時係 件，控制該第二像素電極與該 ;第一掃描線，控制該第二開 且與該第三電極一體形成，用 驅動狀態；以及第二掃描線， 該薄膜電晶體驅動時控制該第 〇 利範圍第7項的發明，因藉由 間的短路發生機率被降低的薄 元件，且第三電極連接於第一 於第二掃描線，故可降低在第 之間發生短路，可防止第一掃 的短路所產生的圖像顯示特性 範圍第8項有關的液晶顯示裝 述第二長度係使前述電流通過 應前述薄膜電晶體所要求的電 1342460 第94〗02845號之專利說明書修正本 ( 成：第一電極，其與形成 之側的端部係具有第一 第一開關元件電性連接 觸之側的端部係具有比 寬度；第三電極，係在 通道形成區域，配置於 該第三電極之間，在該 形成通道；第三開關元 信號線之間的導通狀態 關元件的驅動狀態，並 以控制該薄膜電晶體的 與該第一電極連接，在 一開關元件的驅動狀態 如果依照此申請專 第一電極與第三電極之 膜電晶體形成第二開關 掃描線，第一電極連接 一掃描線與第二掃描線 描線與第二掃描線之間 的下降。 而且，與申請專利 置，係在上述發明中前 區域的寬度的有效值對 流量的值而決定。 9109A-A35 ] 83TWF1 (20100830) 1342460 修正日期：99.8.30 第94102845號之專利說明書修正本 « 而且，與申請專利範圍第9項有關的液晶顯示裝 置，係在上述發明中包含：與前述信號線電性連接的信 號線驅動電路；與前述第一掃描線以及前述第二掃描 線電性連接的掃描線驅動電路；與前述陣列基板面對 面配置的對向基板；封入前述陣列基板與前述對向基 板之間的液晶材料。 【實施方式】 以下針對用以實施使用與本發明有關的薄膜電晶 • 體及使用薄膜電晶體的液晶顯示裝置之最佳的形態（ . 以下僅稱為[實施形態])，一邊參照圖面一邊說明。此 外，應留意圖面為模式的，與現實者不同，在圖面的 相互間當然也包含有互相的尺寸的關係或比率不同的 部分。此外，在以下的實施形態中雖然針對適用與本 發明有關的薄膜電晶體於液晶顯示裝置的構成來說明 ，惟當然與本發明有關的薄膜電晶體的適用對象不被 φ 限定於液晶顯示裝置。而且，在以下的說明中係針對 薄膜電晶體，閘電極以外的電極構造因可當作源電極 以及汲電極的任一個而發揮功能，故稱為源/汲電極 (source/drain electrode)。再者，在以下所提到的薄膜 電扃體雖然以η通道的來說明，惟當然也能適用本發 明於ρ通道的。 第1圖是顯示與本實施形態有關的液晶顯示裝置 的全體構成的模式圖。此外，第1圖是在陣列基板1 與其他構成要素分離的狀態下顯示，惟此乃是為了使 9109Α-Α35183TWF1 (20100830) 1342460 修正日期：99.8.30 第94102845號之專利說明書修正本 陣列基板1的表面構造的理解容易而權宜地顯示，在 實際的液晶顯示裝置中具有陣列基板1與配向膜5 a附 著在一起的構造。 與本實施形態有關的液晶顯示裝置如苐1圖所示 具備：形成有預定的電路構造的陣列基板];面對陣列 基板1配置的對向基板2 ;封入陣列基板1與對向基 板2之間的液晶層3。更詳細為在陣列基板1上形成 有配向膜5a，在對向基板2的底面形成有共通電極4 以及配向膜5 b，配向膜5 a、5 b係成與液晶層3直接 接觸的構成。而且，在陣列基板1的外面以及對向基 板2的外面上分別配置有偏光板6a、6b。而且，在陣 列基板1的下部配置有對陣列基板1輸出平面光的背 光（backl ight) 1 2 0 陣列基板1以及對向基板2係分別以光透射性優 良的透明塑膠基板或無鹼玻璃等為母材而形成，具有 表面為平坦性之優良的構造。此外，在對向基板2的 内表面上配置有共通電極 4，具有在與後述的顯示像 素7所具備的像素電極之間產生預定的電場之功能。 而且省略圖示，進行彩色顯示的液晶顯示裝置的情形 通常係採用在對向基板的内面上或外面上配置對應 R 、G、B的具有光透射特性之彩色濾光片（color filter) 的構成。 液晶層3係以具有配向性的液晶分子為主成分而 形成。包含於液晶層3的液晶分子的例子例如可使用 9109A-A35183TWF1(20100830) 1342460 修正日期：99.8.30 第94102845號之專利說明書修正本 氟系向列（n e m a t i c )液晶分子。其他的液晶分子一般若 為可利用於TN方式的液晶顯示裝置的液晶分子，則 可作為構成液晶層3的液晶分子而利用，針對液晶分 子無須特別限定。 配向膜5 a、5 b係用以規定包含於液晶層3的液晶 分子的配向方向。具體上配向膜5 a、5 b係分別在與液 晶層 3接觸的表面具有非等向性（anisotropic)的構造 ，依照相關的非等向性構造使配向膜5a、5b附近的液 | 晶分子的配向方向被規定。 偏光板6a、6b係具有具備僅使輸入光之中預定方 向的偏光成分通過的透過軸之構造。根據在包含於液 晶層3的液晶分子的配向方向與偏光板6 a、6 b之間所 產生的光學的相關關係，使每一後述的顯示像素7的 光透射率被控制，進行圖像顯示。 其次，針對形成於陣列基板1上的電路構造來說 φ 明。如第1圖所示在陣列基板1上具備：藉由像素電極 以及預定的電路元件形成，配置成行列狀的複數個顯 示像素7 ;延伸於由顯示像素7形成的行列的列方向 ，對顯示像素7供給預定的掃描信號之複數條掃描線 8 ;延伸於由顯示像素7形成的行列的行方向，對顯示 像素7供給依照顯示色調的顯示信號之複數條信號線 9 ;生成選擇顯示像素7用的掃描信號之掃描線驅動電 路1 0 ;生成顯示信號的信號線驅動電路1 1。 針對顯示像素7及其周邊電路構造詳細地說明。 9109A-A35183TWF1 (20100830) B42460 第94102845號之專利說明書修正本 修正日期：99.8.30 r r 第2圖係針對顯示像素7及其周邊電路的構造所示的 模式圖。如第2圖所示，顯示像素7具有顯示像素7 -] 以及顯示像素7 - 2的兩種類的構造，具有分別與掃描 線8以及信號線9電性連接的構成。此外如第2圖所 示，接鄰配置的顯示像素7 - 1、7-2具有分別與同一信 號線9電性連接的構成，藉由採用屬於不同列的顯示 像素7-1、7-2共有同一信號線9的構造，可比一般的 液晶顯示裝置還降低信號線9的數目。 顯示像素7-1具備：像素電極13(相當於申請專利 範圍中的第一像素電極）；在像素電極13連接有一方 的源/汲電極，他方的源/汲電極與信號線9電性連接 的第一薄膜電晶體1 4(相當於申請專利範圍中的第一 開關元件）。而且，顯示像素7-1具備：一方的源/汲電 極連接於後段的掃描線8 - 3，他方的源/汲電極與第一 薄膜電晶體14的閘電極電性連接，閘電極與掃描線 8_2 —體化的第二薄膜電晶體1 5(相當於申請專利範圍 中的薄膜電晶體、第二開關元件）；形成於像素電極1 3 與前段的掃描線8 - 1重疊的部分之儲存電容1 6。 像素電極1 3係藉由供給依照顯示像素7 -1中的顯 ' 示色調之顯示信號以顯示預定的色調。，具體上首先， 藉由對像素電極 1 3供給對應顯示色調的預定的電位 ，在與面對面配置的共通電極4之間產生預定的電位 差。而且，因在像素電極]3與共通電極4之間也如第 ]圖所示的配置有液晶層3，故依照像素電極1 3與共 9109 A-A3 5183TWF1 (20100830) -16- 修正日期：99,8.30 1342460 第94102845號之專利說明書修正本 通電極4之間的電位差使包含於液晶層3的液晶分 的配向方向變化。因此，通過第1圖所示的偏光板 的光的偏光方向係依照包含於液晶層3的液晶分子 變化，依照變化的強度的光由偏光板6 b輸出，變成 照色調的光被輸出。 第一薄膜電晶體1 4係作為申請專利範圍中的第 開關元件而發揮功能。具體上第一薄膜電晶體1 4具 藉由第二薄膜電晶體1 5控制驅動狀態，當被控制成 φ 通（on)狀態時，對像素電極1 3供給作為由信號線9 予的顯示信號之電位的功能。 第二薄膜電晶體1 5係作為申請專利範圍中的薄 電晶體而發揮功能。具體上第二薄膜電晶體1 5具有 由作為由掃描線8-2(相當於申請專利範圍中的第一 線以及第一掃描線的一例）供給的掃描信號之電位 制驅動狀態，當被控制成接通狀態時，對第一薄膜 φ 晶體14的閘電極供給掃描線8-3(相當於申請專利範 中的第二配線以及第二掃描線的一例）的電位的功能 儲存電容1 6係在供給依照顯示色調的電位至像 電極1 3後用以抑制像素電極1 3的電位因附近的配 構造的電位變動的影響等而變動。具體上，儲存電 1 6係以像素電極1 3的一部分區域與相關的一部分 域重疊的掃描線8 -1的一部分作為電極而形成，利 掃描線8 -1在掃描信號供給時以外的大半時間保持 定電位，抑制像素電極1 3的電位變動。 9109A-A35183TWF1 (20100830) 子 6 a 而 依 有 接 給 膜 藉 配 控 電 圍 〇 素 線 容 區 用 B42460 第94102845號之專利說明書修正本 修正日期：99.8.30 顯示像素7-2與顯示像素7- 1 —樣具備像素電極 1 3 (相當於申請專利範圍中的第二像素電極）以及儲存 電容1 6，另一方面，對像素電極1 3供給顯示信號用 的電路元件具有僅具備單一的第三薄膜電晶體1 7 (相 當於申請專利範圍中的第三開關元件）的構造。具體上 第三薄膜電晶體1 7具有一方的源/汲電極電性連接於 像素電極1 3，他方的源/汲電極電性連接於信號線9， 閘電極電性連接於掃描線8 - 2之構造。因此，顯示像 素7-2的情形係根據由掃描線8-2供給的電位使第三 薄膜電晶體1 7的驅動狀態被控制，當第三薄膜電晶體 1 7被控制成接通狀態時，將作為來自信號線9的顯示 信號之電位供給至像素電極1 3。 其次，針對顯示像素7-1所具備的第二薄膜電晶 體1 5的具體的構造詳細地說明。第3圖是說明第二薄 膜電晶體1 5的具體的構造用的模式圖。如第3圖所示 第二薄膜電晶體1 5具備：與位於後段的掃描線8 - 3電 性連接的源/汲電極1 9(相當於申請專利範圍中的第一 電極）；與第一薄膜電晶體1 4的閘電極電性連接的源/ 汲電極2 0 (相當於申請專利範圍中的第二電極）；與掃 描線8-2 —體形成的閘電極2 1 (相當於申請專利範圍中 的第三電極），具有：在形成有源/汲電極19、20的面與 形成有閘電極2 ]的面之間形成有通道形成區域（在第 3圖中省略圖示）之構造。 而且，第二薄膜電晶體1 5也如第3圖所示具有源 9109A-A35183TWF1 (20100830) -18- 1342460 w 佘94102845號之專利說明書修正本 修正日期：99X30 • < f /汲電極1 9與源/汲電極2 0為互相非對稱的構造。具 體上係使與在接通狀態時形成於通道形成區域上的通 道接觸側的端部寬度係互為不同的值而形成，使相對 於源/汲電極1 9中的接觸側端部2 2的寬度為d , 1源/ 汲電極20中的接觸側端部23的寬度為d2係比d,還 大的值而形成。再者，接觸側端部2 2的寬度d,係以 比具有同等的電特性的薄膜電晶體的源/汲電極中的 接觸側端部的寬度還小的值，接觸側端部 23的寬度 φ d 2係以比具有同等的電特性的薄膜電晶體的源/汲電 極中的接觸惻端部的寬度還大的值而形成。 其次，針對第2圖中的參考線A中的剖面構造來 說明。第4圖是顯示參考線A中的剖面構造的模式圖 。如第4圖所示，參考線A中的各構成要素係在陣列 基板1上具有以預定的半導體材料等形成的多層構造 。具體上例如第一薄膜電晶體】4係藉由：形成於陣列 φ 基板1上的一部分區域的閘電極2 5 ;形成於陣列基板 1上以及閘電極2 5上的閘極絕緣層2 6 ;形成於閘極絕 緣層 2 6的一部分區域上的通道形成區域2 7 ;形成於 通道形成區域2 7上的源/汲電極2 9、3 0以及蝕刻中止 層（6:。11丨11经5丨〇卩卩61*)31;形成於源/沒電極29、30以及 蝕刻中止層3 1上的保護層3 3而形成。 而且，第二薄膜電晶體1 5係藉由：形成於陣列基板 1上的一部分區域上的掃描線8 - 2 (閘電極2 1 );形成於 掃描線8 - 2上以及陣列基板1上的其他區域上的閘極 9109A-A35 】83TWF1 (2(M 0083D) 9- B42460 第94102845號之專利說明書修正本 修正日期：99.8.30 < t 絕緣層2 6 ;在閘極絕緣層 2 6上，形成於對應掃描 8-2的區域之通道形成區域28;在通道形成區域28 ，形成於對應閘電極2 1的區域上之蝕刻中止層3 2 形成於通道形成區域2 8的其他區域上的源/汲電極 、2 0 ;形成於源/汲電極1 9、2 0上的保護層3 3而形 。而且，也如第2圖所示因構成第一薄膜電晶體14 閘電極2 5與構成第二薄膜電晶體1 5的源/汲電極 需電性連接，故閘電極2 5具有延伸到第二薄膜電晶 1 5側的構造，源/汲電極20具有延伸到第一薄膜電 體14側的構造。而且，閘電極2 5以及源/汲電極 的互相接近側的端部具有露出於表面的構造，並且 包含露出面的表面上具有藉由連接電極34互相電 連接的構造。此外，蝕刻中止層3 1、3 2係分別在製 源/汲電極1 9等的時候的蝕刻製程中抑制在通道形 區域27、28的表面發生損傷。因此，對於通道形成 域2 7、2 8的表面損傷輕微的情形或有防止表面損傷 其他手段的情形，省略蝕刻中止層3 1、3 2也可以。 而且，如第4圖所示在掃描線8-2的後段側（在 4圖中為右側）於陣列基板〗上形成有掃描線8-3， ' 關的掃描線、8 - 3也如第2圖所示需與構成第二薄膜 晶體1 5的源/汲電極1 9電性連接。因此，源/汲電 1 9如第4圖所示具有延伸到掃描線8 - 3側的構造， 描線8 - 3側中的源/汲電極]9的端部與掃描線8 - 3係 別具有露出於表面的部分，並且形成有連接電極3 5 線 上 1 19 成 的 20 體 晶 20 在 性 作 成 區 的 第 相 電 極 掃 分 俾 9109A-A3 5183TWF1 (20100830) -20- 1342460 修正日期：99.8.30 第94102845號之專利說明書修正本 包含相關的露出部分，具有藉由連接電極35電性連接 彼此之間的構成。 此外，在第4圖所示的構成中例如如閘電極2 5、 掃描線8-2以及掃描線8-3，以同一陰影線圖示者係藉 由同一製程形成者。關於此等層構造，可分別藉由進 行利用 CVD(Chemical Vapor Deposition:化學氣相沉 積）法等的疊層處理以及利用微影（photolithography) 法的姓刻處理，形成有如第4圖所示的構造。 其次，針對與本實施形態有關的液晶顯示裝置的 動作簡單地說明。第5圖是模式地顯示形成於陣列基 板1上的電路構造的等價電路圖，第6圖是顯示第5 圖所不的抑描線8-1〜8-4以及彳§號線9- 1的電位變動 之時序圖（time chart)。以下適宜地參照第5圖以及第 6圖，針對與本實施形態有關的液晶顯示裝置的動作 簡單地說明。 首先如第6圖所示在期間△ t,中掃描線8-2、8-3 的雙方供給驅動電位。因此，第一薄膜電晶體 14、 第二薄膜電晶體1 5以及第三薄膜電晶體1 7變成接通 狀態，像素電極1 3 -1、1 3 -2、1 3 -4與信號線9-1電性 導通。因此，像素電極13-1、13-2 ' 13、4被供給與在 期間△ 11中的信號線9 -1的電位V a相等的電位。 而且，在期間△ t2中停止來自掃描線8-3的驅動電 位的供給，僅掃描線8-2供給驅動電位。因此，在期 間△ t2中僅第二薄膜電晶體 1 5以及第三薄膜電晶體 9109 A-A3 5183 丁 WF1 (20100830) B42460 第94102845號之專利說明書修正本 修正日期：99,8,30 t 1 7驅動，第一薄膜電晶體1 4的驅動停止。因此，像 素電極1 3 -2與信號線9- 1之間的導通被維持，另一方 面像素電極1 3 -1、1 3 - 4與信號線9 -1之間被絕緣。因 此，在期間△ t2中面像素電極1 3 -1、1 3 -4的電位被維 持於V a，另一方面，像素電極13 - 2的電位變化成期 間△ t2中的信號線9-1的電位Vb(此外，在第6圖中係 顯示V a = V b的情形）。 以後經過同樣的程序進行對各像素電極的電位供 給。即在期間A t3中與期間△ t! 一樣藉由由掃描線8-3 、8-4供給驅動電位，使像素電極 1 3-3、1 3-4、1 3-6 供給信號線9-1的電位Vc。而且，在期間△ t4與期間 A t2 —樣藉由僅由掃描線8 - 3供給驅動電位，僅使像 素電極13-4與信號線9-1導通，供給信號線9-1的電 位Vd。然後也一樣，像素電極13-5、13-6也被供給 預定電位。而且，針對可與信號線9 -】不同的信號線 9-2導通的像素電極 13-7〜13-12，也一樣被供給依照 顯示色調的電位。與本實施形態有關的液晶顯示裝置 由於因起因於像素電極的電位的電場的影響使光透射 率變動，故藉由供給依照顯示色調的電位至各個像素 電極1 3，使在畫面上各顯示像素以預定色調·顯示，整 體上一片圖像被顯示。 其次，針對與本實施形態有關的液晶顯示裝置的 優點來說明。首先，與本實施形態有關的液晶顯示裝 置係關於第二薄膜電晶體1 5，使源/汲電極1 9的接觸 9109A-A35183TWF1(20100830) -22- 1342460 修正日期：99.8.30 第94102845號之專利說明書修正本 c 側端部2 2的寬度d,為比面對面的源/汲電極2 0的接 觸側端部23的寬度d2小的值而形成。因此，與本實 施形態有關的液晶顯示裝置具有可降低不同的掃描線 8間短路的可能性之優點。 如已經敘述的，與本實施形態有關的液晶顯示裝 置為了降低信號線9的條數採用多重像素構造。而且 ，對於採用多重像素構造的情形，會產生配設如第 2 圖、第3圖所示閘電極21與掃描線8-2 —體形成，一 φ 方的源/汲電極1 9與和掃描線8-2不同的掃描線8-3 . 電性連接的第二薄膜電晶體1 5之必要性。因此，對於 在形成於源/汲電極1 9與閘電極2 1之間的絕緣層發生 絕緣破壞，彼此電性短路的情形，本來應電性絕緣的 掃描線8-2與掃描線8-3導通，多數的顯示像素的顯 示特性劣化。因此，儘管僅一個位置發生絕緣破壞， 因源/汲電極1 9與閘電極2 1之間短路會使液晶顯示裝 φ 置全體的顯示特性顯著劣化。 另一方面，在他方的源/汲電極20與閘電極21之 間發生電性的短路與源/汲電極1 9的情形比較，嚴重 度低。即乃因對於源/汲電極2 0短路的情形，在對應 的顳示像素7中僅顯示特性劣化，給予液晶顯示裝置 全體的顯示特性的影響止於輕微的程度。因此，對於 如本實施形態採用多重像素構造的液晶顯示裝置的情 形，令與不同的掃描線 8-3電性連接的源/汲電極 19 與閘電極2 1之間的短路發生機率為比源/汲電極2 0與 9109A-A35183TWF1 (20100830) -23- 1342460 第94102845號之專利說明書修正本 修正日期：99.8.30 閘電極2 1之間的短路發生機率還低的值，由製造良率 等的觀點較佳。 因此，在與本實施形態有關的液晶顯示裝置中以 形成第二薄膜電晶體1 5，俾源/汲電極1 9的接觸側端 部2 2的寬度d 1的值為比源/汲電極2 0的接觸側端部 23的寬度d2的值還小。即源/汲電極1 9與閘電極2 1 之間的電性的短路發生機率係與疊層方向（在第3圖中 為對紙面垂直的方向）中的源/汲電極 1 9和閘電極 2 ] 重疊的面積具有對應關係，藉由重疊的面積減少，電 性的短路發生機率減少。因此，在與本實施形態有關 的液晶顯示裝置中藉由形成第二薄膜電晶體 1 5，俾 dfch，可使源/汲電極19與閘電極21之間的短路發生 機率比源/汲電極2 0與閘電極2 1之間的短路發生機率 還降低。 而且，在本實施形態中係關於第二薄膜電晶體1 5 ，更進一步進行構成上的下工夫以一邊抑制電性特性 的劣化，一邊享受上述優點。即即使例如維持源/汲電 極20的接觸側端部23的寬度d2於習知的值，降低源 /汲電極]9的接觸側端部22的寬度d ,，也能抑制源/ 及電極1 9與閘電極2 1之間的、短珞發生機率。但是， 對於相關構成的情形，電流通過區域的寬度僅降低源/ 汲電極1 9的接觸側端部2 2的寬度d,的部分變窄，重 新發生通過源/汲電極19、20間的載子（carrier)的電流 量減少這種問題。因此，本實施形態中的第二薄膜電 9109A-A35183TWF1 (20100830) -24- 修正日期：99.8.30 1342460 第94102845號之專利說明書修正本 晶體]5係關於接觸側端部的寬度滿足d , <d2的 同時抑制源/汲電極 1 9、2 0間的電流量的減少 〇 第 7圖係用以說明關於本實施形態中的第 電晶體1 5，與習知構造的薄膜電晶體比較抑制 的減少的模式圖。如第7圖所示第二薄膜電晶； 藉由閘電極 2 1被施加預定的驅動電位而形成 ，形成有通道之中在源/汲電極1 9、2 0間分別 φ 側端部 22、23為下底、上底的梯形的電流通 3 8。而且，藉由載子的移動使電流流過電流通 38中。 在源/汲電極1 9、2 0間流動的電流量係依存 通過區域 38中的與電流通過方向垂直的方向 的有效值而變化，隨著有效值變大，變成流過 的強度為大的值。因此，電流通過區域38的寬 φ 效值例如藉由電流通過區域的寬度的平均值定 於梯形的電流通過區域 3 8的情形變成藉由作 的下底的接觸側端部22的寬度d !與作為上底 側端部23的寬度d2的相加平均值而給予。因 上述為了降低源/汲電極1 9與閘電極2 1之間.的 生機率，即使為降低接觸側端部22的寬度d, ，藉由決定接觸側端部23的寬度d2，使與d, 平均值為預定的值，可實現抑制電流量減少之 膜電晶體。 條件， 而形成 二薄膜 電流董 豊15係 有通道 以接觸 過區域 過區域 於電流 的寬度 的電流 度的有 義，對 為梯形 的接觸 此，如 短路發 的情形 的相加 第二薄 9109A-A35183TWF1 (20100830) -25- 1342460 第94102845號之專利說明書修正本 修正日期：99.8.30 r f 例如如第 7圖的虛線所示，習知的第二薄膜電 體具備接觸側端部中的寬度為 d的源/汲電極3 9、 ，令驅動時電流通過電流通過區域4 1。對於實現相 的第二薄膜電晶體滿足液晶顯示裝置的要求的電流 的情形’藉由決定d 2的值以滿足 d 2 = 2 d - d 1 ...(1) 可一邊抑制電流量的減少，一邊降低源/汲電極1 9 閘電極2 1之間的短路發生機率。 而且，本實施形態中的第二薄膜電晶體]5在使 /汲電極1 9的電位比源/汲電極20的電位還高的狀 下使用較佳。對於以相關的構成使用的情形也如曰 特開2 0 0 3 - 8 4 6 8 6號公報所示，與在反方向施加電位 狀態比較，可實現更大的電流量。 (變形例一） 其次，針對與本實施形態有關的液晶顯示裝置 變形例來說明。與本變形例一有關的液晶顯示裝置 具有具備第二薄膜電晶體之構成，該第二薄膜電晶 針對兩個源/汲電極具有互相非對稱的形狀，一方的 極係位於他方的電極的周緣部延長上而具有3字形 ' 形成。 第8圖係顯示本實施例一中的第二薄膜電晶體 構成之模式圖。如第8圖所示，本實施例一中的第 薄膜電晶體包含：與掃描線8 - 3電性連接，具有棒狀 狀的源/汲電極43 ;與第一薄膜電晶體1 4的閘電極 晶 40 關 量 與 源 態 本 的 的 係 體 電 而 的 形 電 9109A-A35183TWF1(20100830) -26- 1342460 修正日期：99.8.30 第94]02845號之專利說明書修正本 性連接，配置於源/汲電極4 3的端部附近，並且覆蓋 源/汲電極4 3的端部附近周邊而形成；？字形之源/汲電 極4 4 ;閘電極4 5。此外，與實施形態的情形一樣在閘 電極45與源/汲電極43、44之間存在閘極絕緣層以及 通道形成層，惟在本實施例一中省略圖示以及說明。 具有上述電極形狀的第二薄膜電晶體的情形如第 8圖所示，當驅動時形成有源/汲電極4 3、4 4間的：？字 形的電流通過區域4 8 ’電流通過相關的電流通過區域 φ 4 8而流動。而且，本實施例中的第二薄膜電晶體係針 . 對與源/汲電極43、44的各個中的電流通過區域48接 觸側的端部之接觸側端部 46、47，使接觸側端部 46 的寬度（ = d3+ d4+ d5)比接觸側端部47的寬度（ = d6+ d7 + d8)還小而形成。藉由實現相關的大小關係，與實施形 態一樣可使與掃描線8 - 3電性連接的源/汲電極4 3與 閘電極45之間的短路發生機率比源/汲電極44與閘電 φ 極45之間的短路發生機率還降低。而且，藉由決定第 二薄膜電晶體的構造使維持電流通過區域48的寬度 的有效值的構造，例如接觸側端部46的寬度與接觸側 端部4 7的寬度的平均值被維持於預定的值，可抑制電 流量的·減少。 再者，對於本變形例一的構造的情形，可一邊降 低陣列基板1中的第二薄膜電晶體的佔有面積，一邊 確保充分的電流量。即在本變形例一中令源/汲電極44 的形狀為口字形，在相關的：？字的内部具有配置有源/ 9109A-A35183TWF1 (20100830) 2Ί - 1342460 第94102845號之專利說明書修正本 修正日期：99.8.30 汲電極4 3的端部附近部分之非對稱形狀。因此，對 例如電流由源/汲電極4 3朝源/汲電極4 4流動的情 ，從僅一方向電流流動改變成半放射狀的流動，與 有同等的尺寸之薄膜電晶體比較，變成電流通過區 中的與電流通過方向垂直的方向的寬度的有效值增 ，不用使全體的尺寸大型化也可得到電流量增大的 果。 (變形例二） 其次，針對與本實施形態有關的液晶顯示裝置 變形例二來說明。在本變形例二中除了變形例一的 成外，關於構成第二薄膜電晶體的閘電極的形狀也 有形成^字形的構成。 第9圖係顯示本實施例二中的第二薄膜電晶體 構成之模式圖。如第9圖所示，在本實施例中源/汲 極5 1具有：？字形，並且源/汲電極5 0的端部係配置 被上述口字形覆蓋的區域内，並且關於閘電極52也 有3字形而形成。 也如第4圖所示，第二薄膜電晶體的較佳構造 在通道形成區域28上具備蝕刻中止層32。蝕刻中 層32本來是在製作第二薄膜電晶體時為了避免通 形成區域 2 8的損傷而配設。即在疊層通道形成區 28後疊層有對應源/汲電極1 9、20的導電層，以將 關的導電層分離成源/汲電極1 9與源/汲電極2 0的 式進行蚀刻處理。為了防止在相關的蝕刻處理時被 於 形 具 域 加 效 的 構 具 的 電 於 具 係 止 道 域 相 方 姓 9109A-A35183TWF1 (20100830) -28· 1342460 修正日期：99.8.30 第941〇2845號之專利說明書修正本 刻到位於導電層下層的通道形成區域28，在通道形成 區域2 8上配設蝕刻中止層3 2。 當製作蝕刻中止層3 2時，一旦同樣地疊層形成姓 刻中止層32的材料後，在疊層的層構造上藉由旋塗 (spin coat)法均勻地塗佈光阻（photoresist)，藉由對相 關的光阻隔著對應蝕刻中止層 32 的形狀之圖案 (pattern)的光罩（photomask)曝光，形成光阻圖案 (resist pattern)。而且，藉由以光阻圖案為罩幕（mask) φ 對層構造進行蝕刻處理，以形成有蝕刻中止層32。 以上為一般的蝕刻中止層32的製作製程，以對位 精度的提高等為理由，除了蝕刻中止層32用的光罩外 ，以已經形成的閘電極2 1為罩幕而利用的手法也被提 出。即在塗佈光阻後，藉由自陣列基板1的背面側曝 光，藉由以由遮光性材料形成的閘電極2 1作為罩幕而 活用，可形成蝕刻中止層32 | 此處，钱刻中止層3 2如上述係用以保護通道形成 區域28，更進一步保護通道形成區域28之中對應實 際上進行有載子的移動的電流通過區域之區域。因此 ，關於相關區域以外無須配置蝕刻中止層3 2 ’對於配 置的情形反而與第二薄膜電晶體的電特性的下降等有 關，故不佳。 由相關的觀點檢討變形例一中的第二薄膜電晶體 的構造。在變形例一中的第二薄膜電晶體的製作時以 閘電極45為罩幕使用的情形’因蝕刻中止層係根據閘 9109A-A3 5183TWF1 (20100830) -29- 1342460 第94102845號之專利說明書修正本 修正日期：99.8.30 r « 電極45的圖案而形成，故不僅對應電流通過區域48 的區域，例如在閘電極4 5與源/汲電極4 3重疊的區域 也形成，故不妥當。 因此，在本變形例二中考慮包含以閘電極為罩幕 由陣列基板1的背面側照射光的製程，形成蝕刻中止 層時的權宜，令閘電極5 2的平面形狀與源/汲電極5 1 一樣為3字形。藉由閘電極5 2具有口字形，例如源/ 汲電極5 0與閘電極5 2重疊的區域與變形例一的情形 比較大幅地減少，故關於形成的蝕刻中止層也能當作 對應源/汲電極5 0、5 1間的電流通過區域之形狀。 以上，遍及實施形態以及變形例一、二說明本發 明，惟本發明不應限定於上述實施形態等來解釋，若 為熟習該項技術者，則可想到各種實施例、變形例等 。例如在實施形態等中雖然僅針對適用薄膜電晶體（ 第二薄膜電晶體）於液晶顯示裝置的例子來說明，但無 須限定於相關的適用例。即本發明中的薄膜電晶體的 優點之一為可使特定電極間（在實施形態中為源/汲電 極1 9與閘電極2 1之間）中的電性的短路發生機率比其 他電極間（在實施形態中為源/汲電極 2 0與閘電極2 1 之間）還能降也，即使是液晶顯示裝置以外也能以降低 特定電極間的電性的短路發生機率為目的來使用。特 別是若為需要一邊抑制電流量等的電特性的下降，一 邊降低特定電極間的電性的短路發生機率，則所有的 裝置均可使用薄膜電晶體。而且在實施形態等中雖然 9109 A-A35183TWF1 (20100830) :30- 1342460 第94102845號之專利說明書修正本 修正日期：99.8.30 α t 液晶顯示裝置使用所謂的 TN (Twisted Nematic:扭轉 向列）方式的例子，但例如使用I P S (I η P1 a n e S w i t c h i n g : 橫向電場）方式等具有其他構造的液晶顯示裝置也可 以。而且，在實施形態以及變形例中雖然針對對陣列 基板1等供給平面光為使用背光1 2的透射型液晶顯示 裝置來說明，但無須限定於相關構成來解釋，例如關 於利用太陽光等的反射型液晶顯示裝置，適用本發明 也可以。而且，在變形例中關於源/汲電極4 4、5 1 (相 φ 當於申請專利範圍中的第二電極）以及閘電極5 2 (相當 於申請專利範圍中的第三電極）雖然以具有彎曲形狀 ，但其他關於例如相當於申請專利範圍中的第一電極 的源/汲電極1 9等，以具有彎曲構造也可以。再者， 彎曲形狀不應限定於口字形來解釋，以採用矩形以外 的任意的彎曲形狀也可以。而且，申請專利範圍中的 • 第一配線、第二配線雖然以掃描線8 - 2、8 - 3為例來進 φ 行說明，但第一配線、第二配線不應限定於如掃描線 8-2、8-3般電位變動的情形來解釋，若為滿足各個電 位被個別獨立規定這種條件，則假設至少任一方的電 位維持定電位也可以。 【發明的功效】 - -、 與本發明有關的薄膜電晶體藉由具有第二電極的接觸 側端部的寬度比第一電極的接觸側端部的寬度還大的 構成，可使第一電極與第三電極之間的短路發生機率 比第二電極與第三電極之間的短路發生機率還降低。 9109A-A35183TWF1 (20100830) 1342460 第94102845號之專利說明書修正本 修正日期：99.8.30 t f 而且，與本發明有關的薄膜電晶體係關於第二電極的 寬度，不光是比第一電極的寬度還大而已，也使在第 一電極與第二電極之間所產生的電流通過區域寬度的 有效值為預定值而決定。因此，儘管使接觸側端部的 寬度變化，也能維持電流量於所希望的值，可一邊抑 制電特性的下降，一邊降低特定電極間（第一電極與第 三電極之間）的短路發生機率。 【圖式簡單說明】 第1圖是顯示與實施形態有關的液晶顯示裝置的 全體構成的模式圖。 第2圖是顯示形成於與實施形態有關的液晶顯示 裝置所具備的陣列基板上的電路構造之模式圖。 第3圖是說明形成於陣列基板上的第二薄膜電晶 體的構造的詳細用的模式圖。 第4圖是顯示第2圖的參考線A中的剖面構造的 模式圖。 第5圖是針對形成於陣列基板上的電路構造所示 的等價電路圖。 第6圖是顯示進行圖像顯示時的信號線以及掃描 線的電位變動之時序圖。 第7圖是說明實施形態中的第二薄膜電晶體的優 點用的模式圖。 第8圖是顯示變形例一中的第二薄膜電晶體的構 造的模式圖。 9109A-A35183TWF1 (20100830) 1342460 修正日期：99.8.30 第94丨02845號之專利說明書修正本 第 9圖是顯示變形例二中的第二薄膜電晶體的構 造的模式圖。 第1 0圖是針對形成於習知的多重像素構造的液晶 顯示裝置所具備的陣列基板上的電路構造所示的等價 電路圖。 【符號說明】' 1:陣列基板 2 :對向基板 φ 3:液晶層 4 .·共通電極 5a' 5b: 配向膜 6a' 6b:偏光板 7 :顯示像素 8:掃描線 9:信號線 φ 10:掃描線驅動電路 1 1 :信號線驅動電路 12:背光 1 3 :像素電極 • 14:第一薄模、電晶體 · 1 5 :第二薄膜電晶體 1 6 :儲存電容 1 7 :第三薄膜電晶體 】9、2 0 : 源/汲電極 9109A-A35183TWF1 00830) 1342460 第94102845號之專利說明書修正本 修正日期：99.8.30 c 2 1 :閘電極 22 > 23:接觸側端部 2 5 :閘電極 2 6 :閘極絕緣層 27 > 28:通道形成區域 29 ' 30: 源/汲電極 3 1 ' 32:蝕刻中止層 3 3 :保護層 34 > 35:連接電極 3 8 :電流通過區域 39 ' 40:源/汲電極 4 1 :電流通過區域 43 ' 44: 源/汲電極 4 5 :閘電極 46 > 47:接觸側端部 4 8 :電流通過區域 5 0、5 1 : 源/汲電極 5 2 :閘電極 A1〜FI .·像素電極1342460 Patent Specification No. 94102845 Revision Date: 99.8.30 IX. Description of the Invention: [Technical Field] The present invention relates to a channel formed with a corresponding applied voltage through which a current passes through a current passing region A flowing thin film transistor and a liquid crystal display device using a thin film transistor. [Prior Art] High resolution of a slow-moving display in a CRT display A leap forward has been made with the introduction of a new technology led by liquid crystal. That is, the liquid crystal display device is easier to perform high-definition by performing microfabrication compared with a CRT display. In the liquid crystal display device, an active matrix type liquid crystal display device using a TFT (Thin Film Transistor) as a switching element is known. In the liquid crystal display device of the active matrix type, a TFT array substrate in which a thin film transistor is disposed at an intersection thereof and a counter substrate disposed at a predetermined interval from the substrate are disposed in a matrix shape in which scanning lines and signal lines are arranged. The liquid crystal material is sealed therebetween, and the voltage applied to the liquid crystal material is controlled by the thin film transistor, and can be displayed by the photoelectric effect of the liquid crystal. The on/off of the thin film transistor is controlled by the potential given by the scanning line and the signal line, and the associated scanning line and signal line are respectively connected to the driving circuit. In recent years, the liquid crystal display device tends to be highly refined, and as the number of pixels increases, the number of scanning lines and signal lines increases, and the number of driving ICs also tends to increase. The related tendency is due to the increase in manufacturing cost and the deterioration of the yield. Therefore, the pixel electrode of the present column is modified for the patent specification belonging to the different plural 9109 A-A3 5183TWF1 (20100830) 1342460 repair · ^ date: 99.8.30 No. 94102845 The group, # is constructed by dividing the number of the potential lowering signal lines by one signal line and the number of driving 1Cs connected to the signal lines (hereinafter referred to as [multiple image ^ 1 豕 struct construction]) (For example, refer to Patent Document 1). Fig. 10 is an equivalent circuit diagram showing an example of a structure of a D-F array substrate provided in a liquid crystal display device having a multiple I-type structure. As shown in Fig. 10, for example, the pixel electrode A1 is connected to the scanning line • Gn+1 and the scanning line Gn + 2 via the first thin film transistor and the second thin film transistor M2, and the display signal is supplied from the signal line Dm. Further, the pixel electrode B1 is connected via the third thin film transistor M3. The display signal is supplied from the signal line in the same manner as the scanning line Gn+1. The other pixel electrodes are also connected to the same circuit configuration, for example, the display signal is sequentially supplied to the pixel electrodes aI, B1, C1, D1 by the same t-line Dm to display an image. By adopting the related structure as shown in Fig. 10, the number of signal lines can be reduced, and the number of connections 1c to the signal line 1c can be reduced, so that the manufacturing cost can be reduced. In addition, in the case of the wiring structure shown in Fig. 10, Japanese Patent Laid-Open No. Hei 6-14880, Japanese Patent Application Laid-Open No. U837, No. 5-265 045, and Japanese Patent Laid-Open No. 5_1 A liquid crystal display device using a multi-pixel structure is also disclosed in Japanese Laid-Open Patent Publication No. 883-95. [Patent Document 1] Japanese Patent Laid-Open No. 2 0 0 2 - 1 9 6 3 5 7 [Invention] 9109A-A35183TWF1 (20100830) 1342460 Patent Specification No. 94102845 Amendment of this revision period: 99.8.30 However, generally The thin film transistor has a defect caused by a defect of an interlayer dielectric layer or the like, and is particularly short among the electrodes forming the thin film transistor in the liquid crystal display device using the above multiple pixel structure. The situation of short circuit between electrodes becomes a big problem. The following is a detailed explanation of related issues. As also shown in FIG. 10, the second thin film transistor M2 provided in the liquid crystal display device using the multi-pixel structure has a source electrode electrically connected to the scanning line Gn + 2, and a gate electrode A configuration in which the scanning line Gn+ is electrically connected. Therefore, in the case where the gate/source is short-circuited between the second thin film transistors M2, a plurality of scanning lines which are originally required to be independently supplied with potentials become short circuits, which poses a major obstacle to the image display function. Therefore, it is not appropriate to ship an image display device in which only one of the second thin film transistors M2 which are formed in a plurality of pixel electrodes arranged in a matrix is short-circuited between the gate and the source. As a result, the liquid crystal display device using the conventional multi-pixel structure has a lower number of signal lines than the general liquid crystal display device which does not have the constituent elements corresponding to the second thin film transistor M2, but the manufacturing yield cannot be improved. This kind of subject. On the other hand, for the second thin film transistor M2, a short circuit between the drain electrode and the gate electrode electrically connected to the gate electrode of the first thin film transistor Μ 1 is compared with the short circuit between the gate and the source. The severity is low. That is, it is ideal that the short circuit between the gate and the drain does not occur. 9) 09Α-Α35183TWF1 (20100830) 1342460 Revision date: 99.8.30 Amendment to the patent specification No. 94102845, but only in case of a short circuit In the case where the display characteristics of the display pixels are deteriorated, the display characteristics of most of the other pixels are not adversely affected. Therefore, assuming a short circuit occurs between the gate and the drain, for a small portion of the majority of the second thin film transistor M2, the problem that occurs is visually confirmed to be extremely difficult, generally as a product shipment. Not causing problems. As described above, the semiconductor element such as a thin film transistor often has a difference in the importance of the short circuit occurring between the electrodes, that is, φ is prevented in advance in addition to the case of the liquid crystal display device, and the importance of the short circuit is high. A thin film transistor that reduces the probability of occurrence of an electrical short is also required in a specific electrode. Further, as a configuration for reducing the probability of occurrence of an electrical short circuit, the electrical characteristics of the thin film transistor are not deteriorated. For example, although the probability of occurrence of a short circuit can be reduced by increasing the film thickness of the interlayer insulating film (gate insulating layer, etc.), the problem that the amount of current that can pass through the channel | (cha η ne 1) is reoccurred by the related structure, It is not appropriate. The present invention has been made in view of the above-described problems, and it is an object of the invention to achieve a thin film transistor that suppresses occurrence of a short circuit between specific electrodes and a liquid crystal display device using a thin film transistor while suppressing a decrease in electrical characteristics. The thin film transistor related to the first aspect of the patent application is formed with a channel according to an applied voltage, and a current flows through the current passing region in the channel, and the feature includes: having a contact side end portion with the current passing region First 9109A-A35183TWF1 (20100830) 1342460 Patent Specification No. 94102845 Amendment This revision date: 99.8.30 ^ c The first electrode of the width of the length; the contact side end with the aforementioned current passing region has a longer than the aforementioned first length a second electrode having a width of a second length determined by passing a current generated between the first electrode and the first electrode to a predetermined value; a third electrode to which a predetermined voltage is applied when the channel is formed; Between the first electrode, the second electrode, and the third electrode, The three electrodes form a channel forming region of the channel when a predetermined voltage is applied. According to the invention of claim 1, the first electrode and the third electrode can be formed by a configuration in which the width of the contact-side end portion of the second electrode is larger than the width of the contact-side end portion of the first electrode. The probability of occurrence of a short circuit between them is lower than the probability of occurrence of a short circuit between the second electrode and the third electrode. Moreover, according to the invention of claim 1, the width of the second electrode is not only larger than the width of the first electrode, but also the current passing through the region between the first electrode and the second electrode. The effective value of the width is determined by a predetermined value. Therefore, even if the width of the end portion on the contact side is changed, the amount of current passing between the first electrode and the second electrode can be maintained at a desired value, and the decrease in electrical characteristics can be suppressed while reducing the specific electrode (the first The probability of a short circuit between an electrode and a third electrode occurs. Further, in the thin film transistor according to the second aspect of the invention, the third electrode system is electrically connected to the first wiring that generates a predetermined potential fluctuation, and the first electrode system and the potential and the first The second wiring is electrically connected to each other independently of the wiring. According to the invention of claim 2, the use of 9109 A-A3 5183TWF1 (20100830) -10. 1342460, date of revision: 99.8.30, patent specification No. 94102845, reduces the between the first electrode and the third electrode Since the structure of the short-circuit probability is generated, it is possible to suppress the occurrence of an electrical short between the first wiring and the second wiring in which the potentials are independently changed independently, and it is possible to realize a thin film electric power that does not impair the functions of the first wiring and the second wiring. Crystal. Further, in the thin film transistor according to the third aspect of the invention, in the above invention, at least one of the first electrode, the second electrode, and the third electrode has a curved shape. Further, in the thin film transistor according to the fourth aspect of the patent application, in the above invention, the second electrode has a square shape, the first electrode is disposed, and the end portion of the contact side is formed by the aforementioned three-shape. Within the area. Further, in the film transistor relating to the fifth aspect of the patent application, in the above invention, the third electrode has a zigzag shape. Further, in the thin film transistor according to the sixth aspect of the invention, in the above invention, the first electrode is supplied with a potential higher than the second electrode when the channel is formed. Further, the liquid crystal display device relating to the seventh aspect of the patent application scope is characterized in that the image display is performed by the photoelectric effect of the liquid crystal material, and is characterized by comprising an array substrate having: a signal line, and a transmission corresponding Displaying a tone display signal; the first pixel electrode and the second pixel electrode are supplied with the display signal via the signal line; the first switching element controls a conduction state between the first pixel electrode and the signal line; The second switching element is formed by a thin film transistor having the following configuration for controlling the driving state of the first switching element. 9109A-A35183TWF1 (20100830) Revision date: 99.8.30 Width of the contact length of the current passing through the region a second electrode, and the predetermined voltage is applied when the current passing region is formed by the second length of the first length; the first electrode, the second electrode, and the third electrode are applied a predetermined voltage step, controlling the second pixel electrode and the first scan line, controlling the second opening and forming the same shape as the third electrode Using the driving state; and the second scanning line, the thin film transistor controls the invention of the seventh item of the third profit range, because the thin element is reduced in probability due to the short circuit, and the third electrode is connected to the The second scanning line can reduce the occurrence of a short circuit between the first, and can prevent the image display characteristic range generated by the short circuit of the first scanning. The second length of the liquid crystal display is related to the second length. A modification of the patent specification of the above-mentioned thin-film transistor, which is the first electrode, and the end of the side on which the first first switching element is electrically connected to the side of the contact The third electrode is disposed in the channel forming region and disposed between the third electrodes, and forms a channel; the conduction state between the third switching element signal lines turns off the driving state of the component, and is controlled The thin film transistor is connected to the first electrode, and in the driving state of a switching element, if the film transistor of the first electrode and the third electrode is formed according to the application, the second switch scan is formed. a line, the first electrode is connected to a scan line and a drop between the second scan line trace and the second scan line. Moreover, in the above invention, the effective value of the width of the front region is determined by the value of the flow rate. 9109A-A35] 83TWF1 (20100830) 1342460 Amendment date: 99.8.30 Patent Specification No. 94102845, and a liquid crystal display device relating to claim 9 in the above invention includes: a signal line driving circuit electrically connected to the line; a scanning line driving circuit electrically connected to the first scanning line and the second scanning line; a facing substrate disposed to face the array substrate; and the array substrate and the opposite direction Liquid crystal material between the substrates. [Embodiment] The following is a preferred embodiment of a liquid crystal display device using a thin film transistor and a thin film transistor according to the present invention (hereinafter referred to simply as "embodiment"), and reference is made to the drawings. One side explained. In addition, the intent plane should be modeled. Unlike the actual one, the drawings also contain different dimensions or ratios. Further, in the following embodiments, the configuration of the thin film transistor to which the present invention is applied is described in the liquid crystal display device. However, it is a matter of course that the application of the thin film transistor according to the present invention is not limited to the liquid crystal display device. Further, in the following description, the thin film transistor has an electrode structure other than the gate electrode and functions as either a source electrode or a germanium electrode, and is called a source/drain electrode. Further, although the thin film electric sputum mentioned below is described by the η channel, the present invention can of course be applied to the ρ channel. Fig. 1 is a schematic view showing the overall configuration of a liquid crystal display device according to the present embodiment. In addition, the first figure is shown in a state in which the array substrate 1 is separated from other components, except that the array substrate 1 is modified in order to make 9109Α-Α35183TWF1 (20100830) 1342460 revision date: 99.8.30 No. 94102845. The understanding of the surface structure is easily and expediently displayed, and has a configuration in which the array substrate 1 and the alignment film 5a are adhered together in an actual liquid crystal display device. The liquid crystal display device according to the present embodiment includes an array substrate in which a predetermined circuit structure is formed as shown in FIG. 1 , an opposite substrate 2 disposed on the array substrate 1 , and an array substrate 1 and a counter substrate 2 . The liquid crystal layer 3 between. More specifically, the alignment film 5a is formed on the array substrate 1, and the common electrode 4 and the alignment film 5b are formed on the bottom surface of the counter substrate 2, and the alignment films 5a and 5b are placed in direct contact with the liquid crystal layer 3. Further, polarizing plates 6a and 6b are disposed on the outer surface of the array substrate 1 and the outer surface of the opposite substrate 2, respectively. Further, a backlight for outputting planar light to the array substrate 1 is disposed on the lower portion of the array substrate 1. The array substrate 1 and the counter substrate 2 are respectively transparent plastic substrates or alkali-free glass having excellent light transmittance. It is formed of a base material and has an excellent structure with a flat surface. Further, the common electrode 4 is disposed on the inner surface of the counter substrate 2, and has a function of generating a predetermined electric field between the pixel electrodes included in the display pixel 7 to be described later. Further, in the case of a liquid crystal display device that performs color display, a configuration in which a color filter having light transmission characteristics corresponding to R, G, and B is disposed on the inner surface or the outer surface of the opposite substrate is usually employed. . The liquid crystal layer 3 is formed mainly of liquid crystal molecules having an alignment property. Examples of the liquid crystal molecules contained in the liquid crystal layer 3 can be modified, for example, by using the 9109A-A35183TWF1 (20100830) 1342460, and the patent specification of 99.8.30, No. 94102845, to modify the fluorine-based nematic (n e m a t i c) liquid crystal molecules. The other liquid crystal molecules are generally used as the liquid crystal molecules of the liquid crystal display device of the TN type, and can be used as the liquid crystal molecules constituting the liquid crystal layer 3. The liquid crystal molecules are not particularly limited. The alignment films 5a and 5b are used to define the alignment direction of the liquid crystal molecules contained in the liquid crystal layer 3. Specifically, the alignment films 5 a and 5 b each have an anisotropic structure on the surface in contact with the liquid crystal layer 3, and the liquid crystal molecules in the vicinity of the alignment films 5a and 5b are arranged in accordance with the related anisotropic structure. The direction of the alignment is specified. The polarizing plates 6a and 6b have a structure including a transmission axis through which only a polarization component of a predetermined direction of the input light passes. According to the optical correlation between the alignment direction of the liquid crystal molecules included in the liquid crystal layer 3 and the polarizing plates 6a, 6b, the light transmittance of each of the display pixels 7 to be described later is controlled to perform image display. . Next, the circuit structure formed on the array substrate 1 is φ. As shown in FIG. 1, the array substrate 1 is provided with a plurality of display pixels 7 arranged in a matrix by pixel electrodes and predetermined circuit elements, and extending in the column direction of the rows and columns formed by the display pixels 7, and displaying the same The pixel 7 supplies a plurality of scanning lines 8 of a predetermined scanning signal; a plurality of signal lines 9 extending in a row direction of the rows and columns formed by the display pixels 7 to the display pixels 7 in accordance with a display signal of the display tone; and a selection display pixel 7 is generated. A scanning line driving circuit 10 for scanning signals is used; a signal line driving circuit 11 for generating a display signal. The configuration of the display pixel 7 and its peripheral circuits will be described in detail. 9109A-A35183TWF1 (20100830) B42460 Patent Specification Revision No. 94102845 Revision date: 99.8.30 r r Fig. 2 is a schematic diagram showing the construction of the display pixel 7 and its peripheral circuits. As shown in Fig. 2, the display pixel 7 has two types of structures, a display pixel 7-] and a display pixel 7-2, and has a configuration in which it is electrically connected to the scanning line 8 and the signal line 9, respectively. Further, as shown in FIG. 2, the display pixels 7-1 and 7-2 arranged adjacent to each other have a configuration in which they are electrically connected to the same signal line 9, respectively, by using display pixels 7-1, 7-2 belonging to different columns. The configuration of the same signal line 9 can reduce the number of signal lines 9 as compared with a general liquid crystal display device. The display pixel 7-1 includes a pixel electrode 13 (corresponding to a first pixel electrode in the patent application range); one source/germanium electrode is connected to the pixel electrode 13, and the other source/germanium electrode is electrically connected to the signal line 9. The first thin film transistor 14 (corresponding to the first switching element in the patent application). Further, the display pixel 7-1 is provided with one source/germanium electrode connected to the scanning line 8.3 of the rear stage, and the other source/germanium electrode electrically connected to the gate electrode of the first thin film transistor 14, the gate electrode and the scanning line. 8_2 - a second thin film transistor 15 (corresponding to a thin film transistor and a second switching element in the patent application); a storage capacitor formed in a portion where the pixel electrode 13 overlaps with the scanning line 8.1 of the preceding stage 1 6. The pixel electrode 13 displays a predetermined hue by supplying a display signal in accordance with the display hue in the display pixel 7-1. Specifically, first, by supplying a predetermined potential corresponding to the display hue to the pixel electrode 13, a predetermined potential difference is generated between the common electrode 4 and the face-to-face disposed common electrode 4. Further, since the liquid crystal layer 3 is disposed between the pixel electrode 3 and the common electrode 4 as shown in Fig. 1, the date is corrected according to the pixel electrode 13 and the total number of 9109 A-A3 5183TWF1 (20100830) -16-: 99, 8.30 1342460 Patent No. 94102845 modifies the potential difference between the through electrodes 4 to change the alignment direction of the liquid crystals included in the liquid crystal layer 3. Therefore, the polarization direction of the light passing through the polarizing plate shown in Fig. 1 changes in accordance with the liquid crystal molecules included in the liquid crystal layer 3, and the light according to the varying intensity is output from the polarizing plate 6b, and the light which becomes the color tone is output. The first thin film transistor 14 functions as a first switching element in the scope of the patent application. Specifically, the first thin film transistor 14 has a driving state controlled by the second thin film transistor 15. When it is controlled to be in an on state, the pixel electrode 13 is supplied as a display signal from the signal line 9. The function of the potential. The second thin film transistor 15 functions as a thin transistor in the patent application. Specifically, the second thin film transistor 15 has a potential driving state as a scanning signal supplied from the scanning line 8-2 (corresponding to an example of the first line and the first scanning line in the patent application), and is controlled. In the ON state, the functional storage capacitor 16 of the scanning line 8-3 (corresponding to an example of the second wiring and the second scanning line in the patent application) is supplied to the gate electrode of the first thin film φ crystal 14. After the potential in accordance with the display color tone is supplied to the image electrode 13 , the potential of the pixel electrode 13 is suppressed from fluctuating due to the influence of the potential fluctuation of the nearby arrangement structure. Specifically, the storage battery 16 is formed by using a part of the scanning line 8.1 overlapping with a partial region of the pixel electrode 13 and an associated partial field as an electrode, and the scanning line 8.1 is more than half of the time when the scanning signal is supplied. The constant potential is maintained, and the potential fluctuation of the pixel electrode 13 is suppressed. 9109A-A35183TWF1 (20100830) Sub 6 a and Depending on the connection film, the control unit is used to control the power of the sinusoidal line area. The patent specification is modified by B42460 No. 94102845. This revision date: 99.8.30 Display pixel 7-2 and display pixel 7 - 1 - a pixel electrode 13 (corresponding to a second pixel electrode in the patent application range) and a storage capacitor 16 are provided, and the circuit element for supplying a display signal to the pixel electrode 13 has only a single The structure of the three-film transistor 17 (corresponding to the third switching element in the patent application). Specifically, the third thin film transistor 17 has one source/drain electrode electrically connected to the pixel electrode 13 , the other source/drain electrode is electrically connected to the signal line 9 , and the gate electrode is electrically connected to the scan line 8 - 2 Construction. Therefore, the case of the display pixel 7-2 is such that the driving state of the third thin film transistor 17 is controlled in accordance with the potential supplied from the scanning line 8-2, when the third thin film transistor 17 is controlled to be in the on state, The potential as a display signal from the signal line 9 is supplied to the pixel electrode 13. Next, a specific structure of the second thin film transistor 15 included in the display pixel 7-1 will be described in detail. Fig. 3 is a schematic view for explaining a specific structure of the second thin film transistor 15. As shown in FIG. 3, the second thin film transistor 15 has a source/germanium electrode 19 electrically connected to the scanning line 8.3 located in the rear stage (corresponding to the first electrode in the patent application); The source/tantalum electrode 20 electrically connected to the gate electrode of the thin film transistor 14 (corresponding to the second electrode in the patent application range); the gate electrode 2 1 formed integrally with the scanning line 8-2 (equivalent to the patent application) The third electrode in the range has a structure in which a channel formation region (not shown in FIG. 3) is formed between a surface on which the active/germanium electrodes 19 and 20 are formed and a surface on which the gate electrode 2 is formed. . Moreover, the second thin film transistor 15 also has the source specification 9109A-A35183TWF1 (20100830) -18- 1342460 w 佘94102845 as shown in Fig. 3. Revision date: 99X30 • < f /汲 electrode 19 and source/汲 electrode 20 are mutually asymmetric structures. Specifically, the widths of the end portions on the channel contact side formed on the channel forming region in the ON state are different from each other so as to be opposite to the contact side end portion 2 in the source/drain electrode 19. The width of d, the width of the contact side end portion 23 of the source/tantalum electrode 20 is d2, which is a larger value than d, and is formed. Further, the width d of the contact-side end portion 2 2 is smaller than the width of the contact-side end portion of the source/germanium electrode of the thin film transistor having the same electrical characteristics, and the width of the contact-side end portion 23 is φ d 2 is formed by a value larger than the width of the contact end portion of the source/germanium electrode of the thin film transistor having the same electrical characteristics. Next, the cross-sectional structure in the reference line A in Fig. 2 will be described. Fig. 4 is a schematic view showing a sectional structure in the reference line A. As shown in Fig. 4, each constituent element in the reference line A has a multilayer structure formed of a predetermined semiconductor material or the like on the array substrate 1. Specifically, for example, the first thin film transistor 4 is: a gate electrode 25 formed on a portion of the array φ substrate 1; a gate insulating layer 2 6 formed on the array substrate 1 and on the gate electrode 25; a channel forming region 27 formed on a portion of the gate insulating layer 26; a source/germanium electrode 29, 30 formed on the channel forming region 27, and an etch stop layer (6: .11丨11 via 5)丨〇卩卩61*)31; formed on the source/absence electrodes 29, 30 and the protective layer 33 on the etch stop layer 31. Moreover, the second thin film transistor 15 is formed by: a scan line 8-2 (gate electrode 2 1 ) formed on a portion of the area on the array substrate 1; formed on the scan line 8-2 and on the array substrate 1. Gates 9109A-A35 in other areas] 83TWF1 (2(M 0083D) 9- B42460 Patent Specification No. 94102845 Amendment Revision Date: 99.8.30 < t insulating layer 2 6; on the gate insulating layer 26, a channel forming region 28 formed in a region corresponding to the scan 8-2; in the channel forming region 28, etching formed on a region corresponding to the gate electrode 2 1 The stop layer 3 2 is formed in the source/germanium electrode on the other regions of the channel formation region 28, 20; and the protective layer 33 formed on the source/germanium electrodes 19, 20. Moreover, as shown in FIG. 2, since the gate electrode 25 constituting the first thin film transistor 14 and the source/germanium electrode constituting the second thin film transistor 15 are electrically connected, the gate electrode 25 has a second extension. The configuration of the thin film transistor 5 side, the source/germanium electrode 20 has a structure extending to the side of the first thin film electric body 14. Further, the end portions of the gate electrode 25 and the source/germanium electrode on the mutually adjacent sides have a structure exposed to the surface, and the surface including the exposed surface has a structure electrically connected to each other by the connection electrode 34. Further, the etching stopper layers 3 1 and 3 2 suppress damage to the surfaces of the channel-shaped regions 27 and 28 in the etching process at the time of the source/germanium electrode 19 and the like, respectively. Therefore, the etching stop layer 3 1 or 3 2 may be omitted in the case where the surface damage of the channel forming regions 2 7 and 28 is slight or in the case of preventing the surface from being damaged. Further, as shown in Fig. 4, on the rear side of the scanning line 8-2 (on the right side in Fig. 4), a scanning line 8-3 is formed on the array substrate, and the scanning line of the 'off, the 8.3 is also the same. 2 is electrically connected to the source/germanium electrode 19 constituting the second thin film crystal 15. Therefore, the source/tantalum 19 has a structure extending to the side of the scanning line 8-3 as shown in Fig. 4, and the end of the source/germanium electrode 9 in the side of the line 8-3 is aligned with the scanning line 8-3. There is a portion exposed on the surface, and a 20-well crystal 20 formed on the line of the connection electrode 3 5 is formed. The phase electrode is scanned in the sex-producing region. 9109A-A3 5183TWF1 (20100830) -20- 1342460 Revision date: 99.8. The modification of the patent specification No. 94102845 includes an associated exposed portion having a configuration in which the connection electrodes 35 are electrically connected to each other. Further, in the configuration shown in Fig. 4, for example, the gate electrode 25, the scanning line 8-2, and the scanning line 8-3 are shown by the same hatching in the same process. The layer structure can be formed by lamination processing by a CVD (Chemical Vapor Deposition) method or the like by photolithography, and forming a pattern as shown in FIG. structure. Next, the operation of the liquid crystal display device according to the present embodiment will be briefly described. Fig. 5 is an equivalent circuit diagram schematically showing the circuit configuration formed on the array substrate 1, and Fig. 6 is a view showing the lines 8-1 to 8-4 and the line 9-1 which are not shown in Fig. 5. The time chart of the potential change. Hereinafter, the operation of the liquid crystal display device according to the present embodiment will be briefly described with reference to Figs. 5 and 6 as appropriate. First, as shown in Fig. 6, in the period Δt, both of the scanning lines 8-2 and 8-3 supply the driving potential. Therefore, the first thin film transistor 14, the second thin film transistor 15 and the third thin film transistor 17 are turned on, and the pixel electrodes 1 3 -1, 1 3 -2, 1 3 -4 and the signal line 9- 1 Electrically conductive. Therefore, the pixel electrodes 13-1, 13-2' 13, 4 are supplied with a potential equal to the potential Va of the signal line 9-1 in the period Δ11. Further, the supply of the driving potential from the scanning line 8-3 is stopped during the period Δt2, and only the scanning line 8-2 is supplied with the driving potential. Therefore, in the period Δt2, only the second thin film transistor 15 and the third thin film transistor 9109 A-A3 5183 butyl WF1 (20100830) B42460 Patent Specification No. 94102845 Amendment date: 99, 8, 30 t 1 7 drive, the driving of the first thin film transistor 14 is stopped. Therefore, conduction between the pixel electrode 13-2 and the signal line 9-1 is maintained, and the other pixel electrode 13-1, 1 3-4 and the signal line 9-1 are insulated. Therefore, in the period Δt2, the potential of the surface pixel electrodes 1 3 -1, 1 3 -4 is maintained at V a , and on the other hand, the potential of the pixel electrode 13 - 2 is changed to the signal line 9 - 1 in the period Δ t2 The potential Vb (in addition, the case where V a = V b is shown in Fig. 6). The potential supply to each pixel electrode is then performed through the same procedure. That is, in the period A t3, the driving potential is supplied from the scanning lines 8-3 and 8-4 as in the period Δt!, so that the pixel electrodes 1 3-3, 1 3-4, 1 3-6 are supplied to the signal line 9- The potential Vc of 1. Further, during the period Δt4 and the period A t2, only the driving potential is supplied from the scanning line 8.3, and only the pixel electrode 13-4 and the signal line 9-1 are turned on, and the potential Vd of the signal line 9-1 is supplied. Then also, the pixel electrodes 13-5, 13-6 are also supplied with a predetermined potential. Further, the pixel electrodes 13-7 to 13-12 which are turned on for the signal line 9-2 which is different from the signal line 9 - are also supplied with the potential in accordance with the display hue. In the liquid crystal display device of the present embodiment, since the light transmittance fluctuates due to the influence of the electric field caused by the potential of the pixel electrode, the display pixels on the screen are supplied to the respective pixel electrodes 13 by supplying the potential in accordance with the display color tone. A predetermined image is displayed in a predetermined color tone and display. Next, the advantages of the liquid crystal display device according to the present embodiment will be described. First, the liquid crystal display device according to the present embodiment relates to the second thin film transistor 15 such that the source/germanium electrode 19 is in contact with 9109A-A35183TWF1 (20100830) -22- 1342460. Revision date: 99.8.30 No. 94102845 In the patent specification, the width d of the c-side end portion 2 2 is formed to be smaller than the width d2 of the contact-side end portion 23 of the source/tantalum electrode 20 facing the surface. Therefore, the liquid crystal display device according to this embodiment has an advantage that the possibility of short-circuiting between different scanning lines 8 can be reduced. As described above, the liquid crystal display device according to the present embodiment employs a multi-pixel structure in order to reduce the number of signal lines 9. Further, in the case of employing a multi-pixel structure, a gate electrode 21 and a scanning line 8-2 as shown in Figs. 2 and 3 are formed, and a source/germanium electrode 19 and a scan of a φ square are formed. Line 8-2 Different Scan Lines 8-3. Necessity of Electrically Connected Second Thin Film Transistor 15. Therefore, for the case where the insulating layer formed between the source/germanium electrode 19 and the gate electrode 21 is insulated and electrically short-circuited with each other, the scanning line 8-2 and the scanning line 8-3 which are originally electrically insulated When turned on, the display characteristics of most display pixels deteriorate. Therefore, although the dielectric breakdown occurs at only one position, the short circuit between the source/germanium electrode 19 and the gate electrode 2 1 causes the display characteristics of the liquid crystal display device to be significantly deteriorated. On the other hand, an electrical short circuit between the other source/germanium electrode 20 and the gate electrode 21 is less severe than the case of the source/germanium electrode 19. That is, in the case where the source/germanium electrode 20 is short-circuited, only the characteristic deterioration is displayed in the corresponding display pixel 7, and the influence on the display characteristics of the entire liquid crystal display device is suppressed to a slight extent. Therefore, in the case of the liquid crystal display device having the multi-pixel structure as in the present embodiment, the probability of occurrence of a short circuit between the source/germanium electrode 19 and the gate electrode 21 electrically connected to the different scanning lines 8-3 is higher than that of the source. /汲Electrode 2 0 and 9109A-A35183TWF1 (20100830) -23- 1342460 Patent specification No. 94102845 This revision date: 99.8.30 The probability of occurrence of a short circuit between gate electrodes 2 1 is still low, due to manufacturing yield, etc. The point of view is better. Therefore, in the liquid crystal display device according to the present embodiment, the second thin film transistor 15 is formed, and the value of the width d 1 of the contact side end portion 2 2 of the germanium source/germanium electrode 19 is larger than that of the source/germanium electrode 2. The value of the width d2 of the contact side end portion 23 of 0 is also small. That is, the electrical short-circuit occurrence probability between the source/germanium electrode 19 and the gate electrode 2 1 is the source/germanium electrode 19 and the gate electrode in the lamination direction (the direction perpendicular to the plane of the drawing in FIG. 3). 2] The overlapping areas have a corresponding relationship, and the area of overlap is reduced, and the probability of occurrence of electrical short circuits is reduced. Therefore, in the liquid crystal display device according to the present embodiment, by forming the second thin film transistor 15 and 俾dfch, the probability of occurrence of a short circuit between the source/germanium electrode 19 and the gate electrode 21 can be made larger than that of the source/germanium electrode 2 The probability of occurrence of a short circuit between 0 and the gate electrode 2 1 is also lowered. Further, in the present embodiment, the second thin film transistor 15 is further subjected to the above-described work to enjoy the above advantages while suppressing deterioration of electrical characteristics. That is, even if, for example, the width d2 of the contact-side end portion 23 of the source/deuterium electrode 20 is maintained at a conventional value, the width d of the contact-side end portion 22 of the source/deuterium electrode 9 is lowered, the source/electrode 1 can be suppressed. The probability of occurrence of short 珞 between 9 and gate electrode 2 1 . However, in the case of the related configuration, the width of the current passing region decreases only the width d of the contact side end portion 2 2 of the source/negative electrode 19, and the portion between the source/drain electrodes 19, 20 reoccurs. The amount of current in the carrier reduces this problem. Therefore, the second film electric power in the present embodiment is 9109A-A35183TWF1 (20100830) -24- Amendment date: 99.8.30 1342460 Patent Specification Revision No. 94102845 The crystal] 5 is about the width of the contact side end portion satisfying d, <d2 Simultaneously suppressing the decrease in the amount of current between the source/germanium electrodes 19 and 20; Fig. 7 is a view for explaining the comparison of the first transistor 15 in the present embodiment with a thin film transistor of a conventional configuration Reduced pattern of suppression. a second thin film transistor as shown in FIG. 7; formed by applying a predetermined driving potential to the gate electrode 21, and forming a φ side end portion 22 between the source/germanium electrodes 19 and 20 in the channel, 23 is a trapezoidal current through the lower bottom and the upper bottom. Moreover, current is caused to flow through the current through 38 by the movement of the carrier. The amount of current flowing between the source/germanium electrodes 19 and 20 varies depending on the effective value in the direction perpendicular to the direction in which the current flows through the region 38, and becomes larger as the effective value becomes larger. value. Therefore, the width φ effect of the current passing region 38 is determined, for example, by the average value of the width of the current passing region, and the current passing through the region 38 becomes the width d of the contact side end portion 22 of the lower bottom. It is given as an average of the width d2 which is the upper end side end portion 23. In order to reduce the productivity between the source/germanium electrode 19 and the gate electrode 21, even if the width d of the contact-side end portion 22 is lowered, by determining the width d2 of the contact-side end portion 23, The average value is a predetermined value, and a film transistor that suppresses a decrease in current amount can be realized. Condition, and the formation of the two-film current Dong 15 system has a channel to contact the over-region of the region over the width of the current of the current sense of the sense, for the trapezoidal contact, such as the short-circuited situation of the second thin 9109A- A35183TWF1 (20100830) -25- 1342460 Patent Specification No. 94102845 Revision This revision date: 99.8.30 rf For example, as shown by the broken line in Fig. 7, the conventional second thin film electric body has a width in the contact side end portion. The source/drain electrode 3 of d is such that the current through the current passes through the region 4 1 during driving. For the case where the second thin film transistor of the phase is satisfied to satisfy the current demand of the liquid crystal display device', by determining the value of d 2 to satisfy d 2 = 2 d - d 1 (1), the amount of current can be suppressed from decreasing. While reducing the probability of occurrence of a short circuit between the source/germanium electrode 1 9 and the gate electrode 2 1 . Further, the second thin film transistor 5 of the present embodiment is preferably used in a state where the potential of the /electrode electrode 19 is higher than the potential of the source/germanium electrode 20. For the case of using the related configuration, as shown in the Japanese Patent Publication No. 2 0 0 3 - 8 4 6 8 6 , a larger amount of current can be realized as compared with the case where the potential is applied in the reverse direction. (First Modification) Next, a modification of the liquid crystal display device according to the present embodiment will be described. The liquid crystal display device according to the first modification has a configuration including a second thin film transistor having mutually asymmetric shapes for the two source/germanium electrodes, and one of the poles is located at the periphery of the other electrode. The part is extended and has a 3-shaped shape. Fig. 8 is a schematic view showing the constitution of a second thin film transistor in the first embodiment. As shown in FIG. 8, the thin film transistor of the first embodiment includes: a source/germanium electrode 43 electrically connected to the scanning line 8-3, and having a rod shape; and a gate of the first thin film transistor 14 The electric quantity of the electrode crystal 40 is the same as that of the source body. 9109A-A35183TWF1 (20100830) -26- 1342460 Revision date: 99.8.30 Patent specification No. 94]02845 Corrective nature connection, configuration in source / The vicinity of the end of the electrode 4 3 and the periphery of the end of the source/germanium electrode 43 are formed; The source of the glyph/汲 electrode 4 4 ; the gate electrode 4 5 . Further, as in the case of the embodiment, the gate insulating layer and the channel forming layer are present between the gate electrode 45 and the source/drain electrodes 43, 44, but the illustration and description are omitted in the first embodiment. The case of the second thin film transistor having the above electrode shape is as shown in Fig. 8, and is formed between the active/germanium electrodes 4 3 and 4 4 when driven. The current of the glyph flows through the region 4 8 'current through the associated current through region φ 4 8 . Further, the second thin film electro-crystalline system needle in the present embodiment is provided to the contact side end portions 46, 47 of the end portions on the contact side with the current passing region 48 in each of the source/deuterium electrodes 43, 44, so that the contact side end The width of the portion 46 (= d3 + d4 + d5) is formed smaller than the width of the contact side end portion 47 (= d6 + d7 + d8). By implementing the related magnitude relationship, the short circuit occurrence probability between the source/germanium electrode 43 and the gate electrode 45 electrically connected to the scan line 8-3 can be made to be higher than that of the source/germanium electrode 44 and the gate electrode φ as in the embodiment. The probability of a short circuit between poles 45 is also reduced. Further, by determining the configuration of the second thin film transistor so as to maintain the effective value of the current passing through the width of the region 48, for example, the average value of the width of the contact side end portion 46 and the width of the contact side end portion 47 is maintained at a predetermined value. The value can suppress the decrease in the amount of current. Further, in the case of the structure of the first modification, it is possible to ensure a sufficient amount of current while reducing the occupied area of the second thin film transistor in the array substrate 1. That is, in the first modification, the shape of the source/germanium electrode 44 is a square shape, which is related to: The internal configuration of the word is configured with active / 9109A-A35183TWF1 (20100830) 2Ί - 1342460 Patent Specification Revision No. 94102845 Revision date: 99.8.30 Asymmetric shape of the portion near the end of the electrode 4 3 . Therefore, for example, when the current flows from the source/deuterium electrode 43 toward the source/deuterium electrode 44, the current flows from only one direction to a semi-radial flow, and becomes a current as compared with a thin film transistor having the same size. The effective value of the width in the direction perpendicular to the direction in which the current flows in the region is increased, and the amount of current is increased without increasing the size of the entire size. (Modification 2) Next, a description will be given of a second modification of the liquid crystal display device according to the present embodiment. In the second modification, in addition to the modification 1, the shape of the gate electrode constituting the second thin film transistor is also formed in a chevron shape. Fig. 9 is a schematic view showing the constitution of the second thin film transistor in the second embodiment. As shown in Fig. 9, in the present embodiment, the source/drain 5 1 has: ? The end portion of the source/germanium electrode 50 is disposed in a region covered by the above-described herringbone shape, and is also formed in a zigzag shape with respect to the gate electrode 52. As also shown in Fig. 4, a preferred configuration of the second thin film transistor is provided with an etch stop layer 32 on the channel formation region 28. The etching intermediate layer 32 is originally disposed in order to avoid damage to the formation region 28 when the second thin film transistor is fabricated. That is, a conductive layer corresponding to the source/germanium electrode 19, 20 is laminated after the laminated channel forming region 28 to etch the separated conductive layer into the source/germanium electrode 19 and the source/germanium electrode 20. deal with. In order to prevent the structure of the structure that is added to the shape of the field during the relevant etching process, the name of the circuit is 9109A-A35183TWF1 (20100830) -28· 1342460. Date of revision: 99.8.30 No. 941〇2845 The patent specification modifies the channel formation region 28 located in the lower layer of the conductive layer, and the etching stop layer 32 is disposed on the channel formation region 28. When the etching stopper layer 3 2 is formed, once the material of the surviving layer 32 is formed in the same manner, the photoresist is uniformly applied to the laminated layer structure by a spin coating method. A resist pattern is formed by exposing the associated photomask to a photomask corresponding to the pattern of the shape of the etch stop layer 32. Further, the layer structure is etched by using a photoresist pattern as a mask φ to form an etch stop layer 32. The above-described manufacturing process of the etch stop layer 32 is based on the improvement of the alignment accuracy, and the like, in addition to the mask for etching the stop layer 32, the method of using the already formed gate electrode 2 as a mask is also used. put forward. That is, after the photoresist is applied, by etching from the back side of the array substrate 1, by using the gate electrode 21 formed of a light-shielding material as a mask, an etching stop layer 32 can be formed. The stop layer 3 2 is used to protect the channel forming region 28 as described above, and further protects the region of the channel forming region 28 corresponding to the current passing region in which the carrier is actually moved. Therefore, it is not preferable that the etching stop layer 3 2 ' is not required to be disposed outside the relevant region, but the configuration is not related to the decrease in the electrical characteristics of the second thin film transistor. The configuration of the second thin film transistor in the first modification is reviewed from a related viewpoint. In the case of the second thin film transistor in the first modification, the gate electrode 45 is used as a mask. The etching stop layer is modified according to the patent specification of the gate 9109A-A3 5183TWF1 (20100830) -29- 1342460 No. 94102845. This correction date: 99.8.30 r « is formed by the pattern of the electrode 45. Therefore, it is not only suitable for the region where the current passing region 48 is formed, for example, the region where the gate electrode 45 and the source/drain electrode 43 overlap. Therefore, in the second modification, a process including irradiating light from the back side of the array substrate 1 with the gate electrode as a mask, and forming an etching stop layer, and the planar shape of the gate electrode 52 and the source/germanium electrode 5 are considered. 1 is the same as the 3-character. Since the gate electrode 52 has a square shape, for example, the region where the source/germanium electrode 50 overlaps with the gate electrode 52 is significantly reduced as compared with the case of the first modification, so that the formed etching stop layer can also be regarded as a corresponding source/ The current between the electrodes 5 0 and 5 1 passes through the shape of the region. The present invention has been described above with reference to the embodiments and the first and second modifications. However, the present invention is not limited to the above-described embodiments and the like, and various embodiments, modifications, and the like are conceivable for those skilled in the art. For example, in the embodiment and the like, only the example in which the thin film transistor (second thin film transistor) is applied to the liquid crystal display device will be described, but it is not necessarily limited to the relevant application example. That is, one of the advantages of the thin film transistor in the present invention is that the probability of occurrence of electrical short-circuit in a specific electrode (in the embodiment between the source/germanium electrode 19 and the gate electrode 21) is higher than that between the other electrodes. (In the embodiment, the source/germanium electrode 20 and the gate electrode 2 1 can be lowered), and even if it is a liquid crystal display device, it can be used for the purpose of reducing the occurrence of a short circuit of electrical properties between specific electrodes. In particular, if it is necessary to suppress the decrease in electrical characteristics such as the amount of current, and to reduce the probability of occurrence of electrical shortness between specific electrodes, a thin film transistor can be used for all devices. Further, in the embodiment, etc., the patent specification of 9109 A-A35183TWF1 (20100830): 30-1342460 No. 94102845 is amended. Date of revision: 99.8.30 α t The liquid crystal display device uses a so-called TN (Twisted Nematic) method. For example, a liquid crystal display device having another structure such as an IPS (I η P1 ane S witching) method may be used. In the embodiment and the modification, the transmissive liquid crystal display device using the backlight 12 for the array substrate 1 or the like is described. However, the present invention is not limited to the related configuration, and for example, reflection by sunlight or the like is used. The liquid crystal display device of the type may be applied to the present invention. Moreover, in the modification, with respect to the source/germanium electrode 4 4, 5 1 (phase φ as the second electrode in the patent application range) and the gate electrode 5 2 (corresponding to the third electrode in the patent application range), The shape is curved, but other sources, such as the source/tantalum electrode 1 9 corresponding to the first electrode in the patent application, may have a curved structure. Further, the curved shape should not be limited to the square shape to explain, and any curved shape other than the rectangular shape may be employed. Further, the first wiring and the second wiring in the patent application range are described by taking the scanning lines 8-2, 8-3 as an example, but the first wiring and the second wiring are not limited to the scanning line 8, for example. In the case of -2, 8-3 general potential fluctuations, if the conditions are individually specified for each potential, it is assumed that at least one of the potentials is maintained at a constant potential. [Effect of the Invention] - The thin film transistor according to the present invention can be made to have a first electrode by having a configuration in which the width of the contact side end portion of the second electrode is larger than the width of the contact side end portion of the first electrode The probability of occurrence of a short circuit with the third electrode is also lower than the probability of occurrence of a short circuit between the second electrode and the third electrode. 9109A-A35183TWF1 (20100830) 1342460 Patent Specification No. 94102845 Revision of this revision date: 99.8.30 tf Moreover, the width of the second electrode of the thin film electro-crystal system relating to the present invention is not only greater than the width of the first electrode Moreover, the effective value of the current passing through the region width generated between the first electrode and the second electrode is also determined as a predetermined value. Therefore, even if the width of the contact side end portion is changed, the current amount can be maintained at a desired value, and the occurrence of a short circuit between the specific electrodes (between the first electrode and the third electrode) can be suppressed while suppressing the decrease in the electrical characteristics. Probability. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the overall configuration of a liquid crystal display device according to an embodiment. Fig. 2 is a schematic view showing a circuit structure formed on an array substrate provided in a liquid crystal display device according to an embodiment. Fig. 3 is a schematic view showing the details of the structure of the second thin film transistor formed on the array substrate. Fig. 4 is a schematic view showing a cross-sectional structure in the reference line A of Fig. 2. Fig. 5 is an equivalent circuit diagram shown for the circuit configuration formed on the array substrate. Fig. 6 is a timing chart showing the fluctuation of the potential of the signal line and the scanning line when the image is displayed. Fig. 7 is a schematic view showing the advantages of the second thin film transistor in the embodiment. Fig. 8 is a schematic view showing the configuration of a second thin film transistor in the first modification. 9109A-A35183TWF1 (20100830) 1342460 Revision Date: 99.8.30 Amendment to Patent Specification No. 94-02845 FIG. 9 is a schematic view showing the configuration of the second thin film transistor in the second modification. Fig. 10 is an equivalent circuit diagram showing a circuit configuration on an array substrate provided in a conventional liquid crystal display device having a multi-pixel structure. [Description of Symbols] ' 1: Array substrate 2: opposite substrate φ 3: liquid crystal layer 4 · common electrode 5a' 5b: alignment film 6a' 6b: polarizing plate 7: display pixel 8: scanning line 9: signal line φ 10 : Scanning line driving circuit 1 1 : Signal line driving circuit 12 : Backlight 1 3 : Pixel electrode • 14: First thin mode, transistor · 1 5 : Second thin film transistor 1 6 : Storage capacitor 1 7 : Third film Transistor] 9, 2 0 : Source/汲 electrode 9109A-A35183TWF1 00830) 1342460 Patent specification No. 94102845 Revision date: 99.8.30 c 2 1 : Gate electrode 22 > 23: Contact side end 2 5 : Gate electrode 2 6 : Gate insulating layer 27 > 28: Channel forming region 29 ' 30: Source/germanium electrode 3 1 ' 32: Etching stop layer 3 3 : Protective layer 34 > 35: Connecting electrode 3 8 : Current passing Region 39 '40: Source/汲 electrode 4 1 : Current passing region 43 ' 44: Source/汲 electrode 4 5 : Gate electrode 46 > 47: Contact side end portion 4 8 : Current passing region 5 0, 5 1 : Source /汲 electrode 5 2 : gate electrode A1 to FI .·pixel electrode
Dm:信號線 、 、Dm: signal line, ,
Gn、Gn+1、Gn + 2、Gn + 3:掃描線 Ml :第一薄膜電晶體 M2:第二薄膜電晶體 M3:第三薄膜電晶體 9109A-A35183TWF1(20100830) ...-34-Gn, Gn+1, Gn + 2, Gn + 3: scan line Ml: first thin film transistor M2: second thin film transistor M3: third thin film transistor 9109A-A35183TWF1 (20100830) ...-34-